Application of high pressure deuterium annealing for improving thehot carrier reliability of CMOS transistors

We present the effect of high pressure deuterium annealing on hot carrier reliability improvements of CMOS transistors. High pressure annealing increases the rate of deuterium incorporation at the SiO₂ /Si interface. We have achieved a significant lifetime improvement (90×) from fully processed wafers (four metal layers) with nitride sidewall spacers and SiON cap layers. The improvement was determined by comparing to wafers that were annealed in a conventional hydrogen forming gas anneal. The annealing time to achieve the same level of improvement is also significantly reduced. The increased incorporation of D at high pressure was confirmed by the secondary ion mass spectrometry characterization     

退火温度对生长在TiO2缓冲层上的ZnO薄膜的影响

采用电子束蒸发技术在TiO2缓冲层上沉积了ZnO薄膜,研究了不同的退火温度对薄膜晶化质量及发光性质的影响. 利用X射线衍射仪和扫描探针显微镜分析了薄膜样品的结构性质,利用荧光光谱仪研究了薄膜样品的光致发光性质. 分析结果表明,退火处理后的ZnO薄膜都沿c轴择优生长. 在600℃下退火的样品具有最强的（002）衍射峰、最强的紫外发射和最弱的可见光发射,其晶粒大小均匀,紧密堆积. 而对于在500和700℃下退火的样品,其可见光发射较强. 这表明在600℃下退火的样品具有最好的晶化质量.     

Effects of Thickness and Annealing on Optoelectronic Properties of Electrodeposited ZnS Thin Films for Photonic Device Applications

Thin layers of ZnS with thicknesses of 400 nm, 500 nm, and 700 nm have been electrodeposited on glass/fluorine-doped tin oxide substrates using a simple two-electrode setup under similar conditions. Structural characterization of the layers using x-ray diffraction (XRD) measurements showed that they were amorphous. The results of optical characterization carried out in the wavelength range of 315 nm to 800 nm using spectrophotometry revealed that the optical properties of the layers are strongly influenced by the film thickness as well as annealing conditions. The values of the refractive index, extinction coefficient, absorption coefficient, and dielectric constant obtained from normal-incidence transmittance spectra were generally lower after annealing, showing also the influence of postdeposition annealing on the deposited ZnS layers. Electrical characterization of the layers, using direct-current current–voltage measurement under dark conditions at room temperature, shows that the resistivity of the as-deposited and annealed layers is in the range of 1.4 × 10⁴ Ω cm to 2.5 × 10⁴ Ω cm and 2.5 × 10⁴ Ω cm to 3.1 × 10⁴ Ω cm, respectively. The results suggest that the optoelectronic properties can be tuned for particular applications by adjusting the thickness of the layers appropriately.     

Porous silicon optical cavity structure applied to high sensitivity organic solvent sensor

The present work reports the thermal annealing process, the number of layer and electrochemical process effect in the optical response quality of Bragg and microcavity devices that were applied as organic solvent sensors. These devices have been obtained by using porous silicon (PS) technology. The optical characterization of the Bragg reflector, before annealing, showed a broad photonic band-gap structure with blue shifted and narrowed after annealing process. The electrochemical process used to obtain the PS-based device imposes the limit in the number of layers because of the chemical dissolution effect. The interface roughness minimizations in the devices have been achieved by using the double electrochemical cell setup. The microcavity devices showed to have a good sensibility for organic solvent detection. The thermal annealed device showed better sensibility feature and this result was attributed to passivation of the surface devices.     

Effects of high-temperature rapid thermal annealing for seed layers on the crystallographic evolution in hydrothermal ZnO nanostructures

In this work, we investigated effects of high temperature rapid thermal annealing for the zinc oxide (ZnO) seed layers on the growth morphology and crystal orientation of hydrothermal ZnO nanorods (NRs). The seed layers were prepared by sol–gel spin coating and annealed by two-step rapid thermal processes at different peak temperatures ranging from 600 to 900 °C for a short time period of 1 min. The seed layers annealed in a temperature range of 600–800 °C were all polycrystalline; however, they exhibited a highly Zn-deficient amorphous state when annealed at 900 °C as observed by X-ray photoelectron spectroscopy, X-ray diffraction (XRD), and cross-sectional transmission electron microscopy (TEM). The vertical NRs normal to the substrate were grown along [001] direction atop the polycrystalline seeds annealed at 600–800 °C, whereas different growth morphology of flower-like NRs was observed on the seeds annealed at 900 °C with the strongest XRD peak along the [100] orientation. From our cross-sectional TEM analysis, this flower-like architecture was initiated from the pioneer crystals laterally grown along [001] direction guiding the subsequent growth of petal NRs oriented by a slight difference in growth direction.     

Ti-Rich Barrier Layers Self-Formed on Porous Low-k Layers Using Cu(1?at.%?Ti) Alloy Films

To investigate the applicability of the technique of barrier self-formation using Cu(Ti) alloy films on porous low-k dielectric layers, Cu(1 at.% Ti) alloy films were deposited on porous SiOCH (low-k) dielectric layers in samples with and without ~6.5-nm-thick SiCN pore seals. Ti-rich barrier layers successfully self-formed on the porous low-k layer of both sample types after annealing in Ar for 2 h at 400°C to 600°C. The Ti-rich barrier layers consisted of amorphous Ti oxides and polycrystalline TiC for the samples without pore sealing, and amorphous TiN, TiC, and Ti oxides for the pore-sealed samples. The amorphous TiN originated from reaction of Ti atoms with the pore seal, and formed beneath the Cu alloy films. This may explain two peaks of Ti segregation at the interface that appeared in Rutherford backscattering spectroscopy (RBS) profiles, and suggests that the Ti-rich barrier layers self-formed by the reaction of Ti atoms with the pore seal and porous low-k layers separately. The total molar amount of Ti atoms segregated at the interface in the pore-sealed samples was larger than that in the samples without pore sealing, resulting in lower resistivity. On the other hand, resistivity of the Cu alloy films annealed on the porous low-k layers was lower than that annealed on the nonporous low-k layers. Coarser Cu columnar grains were observed in the Cu alloy films annealed on the porous low-k layers, although the molar amount of Ti atoms segregated at the interface was similar in both sample types after annealing. The cause could be faster reaction of the Ti atoms with the porous dielectric layers.     

Terahertz time-domain-spectroscopy system using a 1 micron wavelength laser and photoconductive components made from low-temperature-grown GaAs

A terahertz time-domain spectroscopy (TDS) system based on a femtosecond Yb:KGW laser, photoconductive emitters and detectors made from as-grown and from annealed at moderate temperatures (~400°C) low-temperature-grown GaAs (LTG GaAs) layers was demonstrated. The measured photoconductivity of these layers increased linearly with the optical power, showing that transitions from the defect band to the conduction band are dominant. The largest amplitude THz pulse with a useful signal bandwidth reaching 3 THz and its signal-to-noise ratio exceeding 50 dB was emitted by the device made from the LTG GaAs layer annealed at 420°C temperature. The detector made from this material was by an order of magnitude less sensitive than conventional GaBiAs detectors.     

Structure and carrier lifetime in LT-GaAs

The relationship between the structural quality of low-temperature GaAs layers and the photoexcited carrier lifetime has been studied. Transmission electron microscopy, x-ray rocking curves, time-resolved reflectance methods, and photoconductive-switch-response measurements were used for this study. For a variety of samples grown at temperatures in the vicinity of 200°C, subpicosecond carrier lifetimes were observed both in as-grown layers, as well as in the same layers after post-annealing and formation of As precipitates. These results suggest that the carrier lifetime, which was found to be shorter in the as-grown layers than in the annealed ones, might be related to the density of As_Ga antisite defects present in the layers. The annealed layers which contained structural defects before annealing appeared to exhibit the longest carrier lifetime due to gettering of As on these defects (and formation of relatively large As precipitates) and depletion of extra As (As_Ga) defects from the layer. It was found as well that the responsivity of detectors fabricated on these layers depended strongly on the structural quality of the layers, with the greatest response obtained not for the layers with the fewest defects, but for the layers with 10⁷–10⁸/cm² of pyramidal defects.     

Scanning force microscopy studies of GaAs films grown on offcut Ge substrates

The surface morphology of GaAs films grown on offcut Ge substrates is studied using a scanning force microscope (SFM). We investigated the effects of the Ge buffer layer, growth temperature, film thickness, and prelayer on the GaAs surface morphology. The starting Ge substrates are offcut 6° toward the [110] direction to minimize single steps on the substrates before molecular beam epitaxial film growth. We find that comparing with GaAs samples grown without Ge buffer layers or with unannealed Ge buffer layers, samples with annealed Ge buffer layers are much smoother and contain no antiphase boundaries (APBs) on the surface. For thick (≥1 μm) GaAs films with an annealed Ge buffer layer, the surfaces display crosshatch lines and elongated mounds (along , which are associated with the substrate offcut direction. As the film thickness increases, the crosshatch lines become shorter, denser and rougher, and the mounds grow bigger (an indication of GaAs homoepitaxial growth). We conclude that annealed Ge buffer layers are crucial for growing high quality GaAs films with few APBs generated during the growth. In addition, under optimal conditions, different prelayers make little difference for thick GaAs films with annealed Ge buffer layers.     

镉气氛退火对CdS单晶材料性能的影响

硫化镉(CdS)是一种光电性能优异的Ⅱ-Ⅵ族直接跃迁、宽带隙化合物半导体材料。将本征高阻的CdS单晶材料在镉气氛中高温退火,并对退火后的CdS材料进行电学、光学特性表征。测试结果表明,镉气氛退火可使本征高阻的CdS单晶转变为低阻CdS材料,从而实现对CdS材料电学特性调控。     

Al,Al/C and Al/Si implantations in 6H-SiC

Multiple-energy Al implantations were performed with and without C or Si coimplantations into 6H-SiC epitaxial layers and bulk substrates at 850°C. The C and Si co-implantations were used as an attempt to improve Al acceptor activation in SiC. The implanted material was annealed at 1500, 1600, and 1650°C for 45 min. The Al implants are thermally stable at all annealing temperatures and Rutherford backscattering via channeling spectra indicated good lattice quality in the annealed Al-implanted material. A net hole concentration of 8 × 10¹⁸ cm⁻³ was measured at room temperature in the layers implanted with Al and annealed at 1600°C. The C or Si co-implantations did not yield improvement in Al acceptor activation. The co-implants resulted in a relatively poor crystal quality due to more lattice damage compared to Al implantation alone. The out-diffusion of Al at the surface is more for 5Si co-implantation compared to Al implant alone, where 5Si means a Si/Al dose ratio of 5.     

Photoinduced etching of thin films of chalcogenide glassy semiconductors

Photoinduced enhancement of the solubility of annealed films made of chalcogenide glassy semiconductors (ChGSs) in amine-based selective etchants has been observed. The etching rate increases with the illumination intensity, and its spectral dependence is correlated with absorption in the film at the absorption edge. It is demonstrated that the new photoinduced effect enables a photolithographic process (including interference lithography) to occur on ChGS layers, annealed at a temperature close to the glass-transition temperature of a chalcogenide glass by simultaneous illumination and selective etching of layers of this kind. A possible mechanism for the photoinduced etching of ChGSs is discussed.     

High-Vacuum Evaporation of <Emphasis Type="Italic">n</Emphasis>-CuIn<Subscript>3</Subscript>Se<Subscript>5</Subscript> Photoabsorber Films for Hybrid PV Structures

Thin films of Cu-In-Se (CISe) photoabsorber with an overall composition of CuIn₃Se₅ were deposited onto glass/indium tin oxide (ITO) substrates from a polycrystalline bulk CuIn₃Se₅ source using the high-vacuum evaporation technique. Thermal conditions for the substrates during the evaporation process and the subsequent annealing in vacuum were selected to prepare polycrystalline n-CuIn₃Se₅ photoabsorber layers for use in hybrid photovoltaic structures based on an inorganic photoabsorber and conductive polymer functional layers. The CISe layers were deposited at a substrate temperature of 200°C and were annealed at temperatures from 300°C to 500°C in vacuum. Part of the as-deposited CISe was annealed twice, in argon and in vacuum at 500°C. These layers exhibited high photosensitivity and photoconductivity when illuminated with white light at an intensity of 100 mW/cm². The results showed that the chalcopyrite structure of the prepared CISe photoabsorber films adhered well to the glass/ITO substrate. The average value of charge carrier concentration and the profile of charge carrier concentration in the annealed CISe photoabsorber layer were calculated using impedance spectroscopy.     

Growth of polycrystalline silicon films on titanium and aluminum layers

Adherent, polycrystalline silicon films were vacuum deposited onto titanium passivated steel alloy substrates at substrate temperatures between 535 and 650°C and onto aluminum films at substrate temperatures between 480 and 520°C. Silicon films deposited onto titanium layers are characterized by a sub-micron grain size and a preferential orientation of the <110> direction perpendicular to the growth surface. Resistivities of ∿10⁴ ohm-cm are measured for the undoped films. Silicon films deposited onto aluminum layers have a larger grain size, ∿5μm, a columnar morphology and a preferential orientation of the <111> direction perpendicular to the growth surface. As-deposited resistivities of ∿10² ohm-cm are measured for these films. Boron and phosphorus doped silicon films on titanium layers were annealed. The behavior with annealing of the electrical properties of the films depended on which doping impurity was used. Silicon films on aluminum were annealed to reduce lattice damage within the silicon grains and to dope the films with aluminum from the aluminum layer. Resistivities of several ohm-cm were measured for the annealed films on aluminum.     

InGaN/GaN light emitting diodes activated in O2 ambient

Mg-doped GaN epitaxial layers were annealed in pure O₂ and pure N₂. It was found that we could achieve a low-resistive p-type GaN by pure O₂ annealing at a temperature as low as 400°C. With a 500°C annealing temperature, it was found that the forward voltage and dynamic resistance of the InGaN/GaN light emitting diode (LED) annealed in pure O₂ were both smaller than those values observed from InGaN/GaN LED annealed in pure N₂. It was also found that an incomplete activation of Mg will result in a shorter LED lifetime     

Cu(In,Ga)Se2太阳电池缓冲层ZnS薄膜性质及应用

在含有ZnSO4,SC(NH2)2,NH4OH的水溶液中采用CBD法沉积ZnS薄膜,XRF和热处理前后的XRD测试表明,ZnS沉积薄膜为立方相结构,薄膜含有非晶态的Zn(OH)2.光学透射谱测试表明,制备的薄膜透过率(λ＞500nm)约为90%,薄膜的禁带宽度约为3.51eV.ZnS薄膜沉积时间对Cu(In,Ga)Se2太阳电池影响显著,当薄膜沉积时间在25～35min时,电池的综合性能最好.对比了不同缓冲层的电池性能,采用CBD-CdS为缓冲层的电池转换效率、填充因子、开路电压稍高于CBD-ZnS为缓冲层的无镉电池,但无镉电池的短路电流密度高于前者,两者转换效率相差2%左右.ZnS可以作为CIGS电池的缓冲层,替代CdS,实现电池的无镉化.     

Metalorganic vapor phase epitaxial growth,characterization and annealing experiments on InP doping superlattices

InP doping superlattices (DSLs) were grown by atmospheric pressure metalorganic vapor phase epitaxy (MOVPE) and their stability was examined by annealing at high temperatures. Diethylzinc (DEZ) and H₂S were used asp- andn-type doping sources, respectively. Photoluminescence (PL) measurements performed on as grown layers show a shift of the main emission peak with increasing excitation power in very good agreement with theoretical models. A comparison of the PL results between these structures and the annealed samples show that even at very high temperatures (up to 850° C) the tunability of the effective bandgap of the annealed superlattices is possible, although less pronounced than for the as grown layers. This is due to diffusion of the dopants, into adjacent layers and partial compensation of each other. Secondary ion mass spectrometry (SIMS) done on the as grown and annealed samples shows that only the Zn atoms diffuse. Diffusion coefficients obtained from the SIMS profiles give values in the range 1 × 10⁻¹⁴ <D < 9 × 10⁻¹⁴ cm²/s, still smaller than other published values estimated on layers, which did not suffer any treatment. This shows the high quality and stability of our layers even at high temperatures.     

On the photon annealing of silicon-implanted gallium-nitride layers

The conditions for the formation of ion-doped layers in gallium nitride upon the incorporation of silicon ions followed by photon annealing in the presence of silicon dioxide and nitride coatings are analyzed. The conditions of the formation of ion-doped layers with a high degree of impurity activation are established. The temperature dependences of the surface concentration and mobility of charge carriers in ion-doped GaN layers annealed at different temperatures are studied.     

A high-performance polycrystalline silicon thin film transistorwith a silicon nitride gate insulator

We have fabricated a high performance polycrystalline silicon (poly-Si) thin film transistor (TFT) with a silicon-nitride (SiN_x ) gate insulator using three stacked layers: very thin laser of hydrogenated amorphous silicon (a-Si:H), SiN_x and laser annealed poly-Si. After patterning thin a-Si:H/SiN_x layers, gate, and source/drain regions were ion-doped and then Ni layer was deposited. This structure was annealed at 250°C to form a NiSi silicide phase. The low resistive Ni silicides were introduced as gate/source/drain electrodes in order to reduce the process steps. The poly-Si with a grain size of 250 nm and low resistance n⁺ poly-Si for ohmic contact were introduced to achieve a high performance TFT. The fabricated poly-Si TFT exhibited a field effect mobility of 262 cm²/Vs and a threshold voltage of 1 V     

Postgrowth Annealing of CdTe Layers Grown on Si Substrates by Metalorganic Vapor-Phase Epitaxy

Annealing conditions of CdTe layers grown on Si substrates by metalorganic vapor-phase epitaxy were studied. Typically, 3-μm-thick n-type (211) CdTe layers were annealed for 60 s in flowing hydrogen at atmospheric pressure by covering their surfaces with bulk CdTe wafers. At annealing temperatures above 700°C, improvement of crystal quality was confirmed from full-width at half-maximum values of double-crystal rocking-curve measurements and x-ray diffraction measurements. Photoluminescence measurements revealed no deterioration of electrical properties in the annealed n-CdTe layers. Furthermore, annealing at 900°C improved the performance of radiation detectors with structure of p-like CdTe/n-CdTe/n ⁺-Si substrate.