Novel hydrogen annealing for forming SiO2 film by rapidthermal processing

Hydrogen annealing at 700-1100°C for 0-300 s has been combined with SiO₂ formation by rapid thermal processing (RTP). The SiO₂ films formed with the above processes were evaluated by C-V and I-V measurements and by time-dependent dielectric breakdown (TDDB) tests. These films provide longer time to breakdown andless positive charge generation than SiO₂ films formed without H₂ annealing. In particular, the SiO₂ formation-H₂ annealing SiO ₂ formation process is quite effective in improving the dielectric strength of the thin RTP-SiO₂ film     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Optimized silicon-rich oxide (SRO) deposition process for 5 V onlyflash EEPROM applications

A process for depositing in-situ very-thin (<10 nm) SiO₂ films on top of a silicon-rich oxide (SRO) layer in a standard low-pressure chemical vapor deposition (LPCVD) reactor has been optimized. Polysilicon-gate MOS capacitors using this stacked dielectric have shown high tunneling current at low voltages and an extraordinary endurance to electrical stress. Capacitors with 7 nm LPCVD SiO₂ on top of 10 nm SRO did not show any relevant shift on either the low or high portion of the I-V characteristic, after a fluence of more than 500 C/cm² at J=0.1 A/cm² . The results add further support to the usefulness of implementing these stacked dielectric structures in a variety of nonvolatile memory devices     

Rapid isothermal processing of strained GeSi layers

A cold-wall rapid thermal processor was used to study the oxidation and annealing properties of Ge_xSi_1-x strained layers. The dry oxidation rate of Ge_xSi_1-x was found to be the same as that of Si, while the wet oxidation rate was found to be higher than that of Si, and the oxidation rate increases with the Ge concentration (up to 20% in this study). A high fixed oxide charge density (>5×10¹¹ /cm²) and interface trap level density (>10¹² /cm²-eV) at the oxide interface have been determined from capacitance-voltage measurements. Using techniques such as X-ray rocking curve analysis and I-V and C-V measurements of the p-n heterojunction it was found that the degradation of electronic properties of metastable Ge_xSi_1-x strained layers during rapid thermal annealing are related to the formation of structural defects at the heterointerfaces     

Electrical transport properties of crystalline siliconcarbide/silicon heterojunctions

The electrical transport properties of β-SiC/Si heterojunctions were investigated using current-voltage (I-V) and capacitance-voltage (C-V) characteristics. The heterojunctions were fabricated by growing n-type crystalline β-SiC films on p-type Si substrates by chemical vapor deposition (CVD). The I-V data measured at various temperatures indicate that at relatively high current, the heterojunction forward current is dominated by thermionic emission of carriers and can be expressed as exp(-qV_bi/kT ) exp(V/ηkT), where V_bi is the built-in voltage of the heterojunction and η(=1.3) is a constant independent of voltage and temperature. At lower current, defect-assisted multitunneling current dominates. The effective density of states and the density-of-states effective mass of electrons in the conduction band of SiC are estimated to be 1.7×10²¹ cm ^-3 and 0.78m₀, respectively. This study indicates that the β-SiC/Si heterojunction is a promising system for heterojunction (HJ) devices such as SiC-emitter heterojunction bipolar transistors (HBTs)     

Ion-dosage-dependent room-temperature hysteresis in MOS structureswith thin oxides

Two sets of metal-oxide-silicon (MOS) structures with oxide thicknesses of 115 and 350 Å, respectively, were exposed to 16-keV Si ion beams after dry oxidation. Small-signal capacitance-voltage measurements at room temperature revealed a hysteresis effect in the ion exposed samples, whose magnitude and direction depended on the ion dosage. No hysteresis could be detected in the control (unimplanted) samples. Mobile charge species in the oxide dominated the hysteresis effect for dosages below 10¹³/cm². Around this dosage, electron trapping/detrapping at the Si-SiO₂ interface began to take place. From the rate of the parallel voltage shifts of the C-V characteristics with respect to time, electron trapping and the mobile oxide charge transfer from the silicon/oxide to the aluminum/oxide interface were found to be faster than electron detrapping and the mobile oxide charge transfer form the oxide/Al to the Si-SiO₂ interface. With increasing dosage, the magnitude of the hysteresis came down and reversed its sign as the dosage approached 10¹³/cm². Experimental results suggest immobilization of the mobile oxide charge by lattice disorder induced by the energetic ions, and generation of oxide electron traps in the vicinity of the silicon/oxide interface after the lattice damage becomes heavy     

A gate-quality dielectric system for SiGe metal-oxide-semiconductordevices

The authors present a high-quality dielectric system for use with Si_1-xGe_x alloys. The system employs plasma-enhanced chemical vapor deposited (PECVD) SiO₂ on a thin (6-8-nm) layer of pure silicon grown epitaxially on the Si_1-x Ge_x layer. The buffer layer and the deposited oxide prevent the accumulation of Ge at the oxide-semiconductor interface and thus keep the interface state density within acceptable limits. The Si cap layer leads to a sequential turn-on of the Si_1-xGe_x channel and the Si cap channel as is clearly observed in the low-temperature C-V curves. The authors show that this dual-channel structure can be designed to suppress the parasitic Si cap channel. The MOS capacitors are also used to extract valence-band offsets     

Magnetotransconductance profiling of mobility and doping in GaAsMESFETs

Electron mobility profiles of GaAs MESFETs have been measured using the magnetotransconductance technique and corrected using in situ measurements of parasitic resistances. It is shown that with this technique both mobility and carrier density profiles versus depth can be calculated without C-V data. This enables complete mobility and carrier density profiles to be obtained on short-gate-length packaged devices without the inherent difficulties of the C-V method and its attendant inaccuracies near the active layer-substrate interface. The results for two commercial packaged devices at room temperature, which indicate mobilities of 3500 to 4500 cm²/V/s and peak carrier concentrations of 1.2 to 2.0×10¹⁷ cm^-3, are given     

Studies of yttrium oxide films prepared by RF magnetron sputtering

Films of yttrium oxide (Y₂O₃) were deposited on Si substrates from a Y₂O₃ target by RF magnetron sputtering. MIS capacitors in the form of Al and Y₂O₃ (400 Å)-Si were then fabricated. The leakage current density was about 10^-6 A/cm² at 1.3×10⁶ V/cm, and the breakdown field of the films was about 2.75×10⁶ V/cm. The dielectric constant of the sputtered Y₂O₃ was found to be about 12-12.7     

Threshold voltage and C-V characteristics of SOIMOSFET's related to Si film thickness variation on SIMOX wafers

C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of ±150 Å was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed     

Electrical properties of low-temperature pyrolytic SiO2on InP

The first application of a new technique (SiH₄+O₂ at 83-330°C and 2-12 torr) for deposition of SiO₂ on InP is reported. SiO₂ deposited at 150-330°C has breakdown strength of 8-10 MV/cm, resistivity >10¹⁵ Ωcm, and refractive index of 1.45-1.46 comparable to thermal SiO ₂ grown at 1100°C. C/V measurements on Al/SiO₂/InP MIS structures suggest that very low temperature oxides (90-100°C) have the best interfacial properties     

Interpretation and control of C-V measurementsusing pattern recognition and expert system techniques

The authors demonstrate how a pattern-recognition system can be applied to the interpretation of capacitance-voltage (C-V ) curves on an MOS test structure. By intelligently sequencing additional measurements it is possible to accurately extract the maximum amount of information available from C-V and conductance-voltage (G-V) measurements. The expert system described, (CV-EXPERT), is completely integrated with the measurement, instrumentation, and control software and is thus able to call up a sequence of individually tailored tests for the MOS test structure under investigation. The prototype system is able to correctly identify a number of process faults, including a leaky oxide, as shown. Improvements that could be gained from developing rules to coordinate G-V, capacitance-time, and doping profile measurements simply by recognizing the important factors in the initial C- V measurement are illustrated     

Effect of dopant redistribution, segregation, and carrier trappingin As-implanted MOS gates

Anomalous capacitance-voltage behavior of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi₂ layer is reported. The C-V characteristics and specifically the inversion and accumulation capacitances are gate-bias-dependent and are strongly affected by annealing temperature, silicidation, and polysilicon gate microstructure (i.e. polysilicon versus amorphous gate). The results can be explained by insufficient As redistribution, coupled with carrier trapping, and As segregation at polysilicon grain boundaries and in TiSi₂. All these effects lead to the formation of a depletion region in the polysilicon gate and thus to the anomalous C-V behavior     

A comprehensive study on p+ polysilicon-gate MOSFET'sinstability with fluorine incorporation

It is reported that fluorine can jeopardize p⁺-gate devices under moderate annealing temperatures. MOSFETs with BF₂ or boron-implanted polysilicon gates were processed identically except at gate implantation. Evidence of boron penetration through 12.5-nm oxide and a large quantity of negative charge penetration (10 ¹² cm^-2) by fluorine even at moderate annealing conditions is reported. The degree of degradation is aggravated as fluorine dose increases. A detailed examination of the I-V characteristics of PMOSFET with fluorine incorporated p⁺-gate revealed that the long gate-length device had abnormal abrupt turn-on I_d-V_g characteristics, while the submicrometer-gate-length devices appeared to be normal. The abnormal turn-on I_d-V_g characteristics associated with long-gate-length p⁺-gate devices vanished when the device was subjected to X-ray irradiation and/or to a high-voltage DC stressing at the source/drain. The C-V characteristics of MOS structures of various gate dopants, processing ambients, doping concentrations, and annealing conditions were studied. Based on all experimental results, the degradation model of p⁺-gate devices is presented. The incorporation of fluorine in the p⁺ gate enhances boron penetration through the thin gate oxide into the silicon substrate and creates negative-charge interface states. The addition of H/OH species into F-rich gate oxide will further aggravate the extent of F-enhanced boron penetration by annealing out the negative-charge interface states     

Time-dependent dielectric breakdown characteristics ofN2O oxide under dynamic stressing

Time-dependent dielectric breakdown (TDDB) characteristics of MOS capacitors with thin (120-Å) N₂O gate oxide under dynamic unipolar and bipolar stress have been studied and compared to those with control thermal gate oxide of identical thickness. Results show that N₂O oxide has significant improvement in t _BD (2×under-V_g unipolar stress, 20×under+V_g unipolar stress, and 10×under bipolar stress). The improvement of t_BD in N₂O oxide is attributed to the suppressed electron trapping and enhanced hole detrapping due to the nitrogen incorporation at the SiO₂/Si interface     

Anomalous C-V characteristics of implanted polyMOS structure in n+/p+ dual-gate CMOS technology

The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900°C/30 min to rapid thermal annealing at 1050°C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G_m of NMOS transistors with 125-Å Gate oxide thickness     

Defect electrical conduction in SIMOX buried oxides

It is pointed out that the buried oxide (BOX) layers in SIMOX structures exhibit localized defect conduction superimposed on the background (bulk) conduction. Type I defects show a pre-breakdown quasi-linear I-V characteristic with 10^-7<I<10^-3 A in the voltage range of 0.01-10 V. Type II defects exhibit a superlinear I-V behavior above 5 V and breakdown, usually occurs at 10-50 V. A large number of samples prepared in various manners has been studied with automatic test equipment by which the number of Type I defects has been determined from several hundreds of capacitors on a given wafer. For annealed samples the calculated defect density values range from 0.01 to 10 defects/cm², while for un-annealed samples the range is 40-120 defects/cm². Type I defects are very probably Si pipes in the BOX which result from particulate contamination during implantation. Statistical analysis revealed that the sample preparation technique has improved significantly in 1992. The situation regarding the Type II defects is more complicated as these defects appear to be closely related to some fundamental aspects of bulk conduction of the BOX layer in which electron traps play an important role     

Electrical characterization and modeling of alternating-currentthin-film electroluminescent devices

Electrical characterization of evaporated ZnS:Mn alternating-current thin-film electroluminescent (ACTFEL) devices is accomplished by capacitance-voltage (C-V) analysis. Interpretation of these C-V characteristics is aided by SPICE modeling and by electrical characterization of an ideal ACTFEL device constructed from discrete components, based on a simple equivalent circuit for the ACTFEL device. Various features of the C -V curve are ascribed to equivalent circuit parameters and associated device physics parameters     

Charge control, DC, and RF performance of a 0.35-μmpseudomorphic AlGaAs/InGaAs modulation-doped field-effecttransistor

The authors describe a study of charge control in conjunction with DC and RF performance of 0.35-μm-gate-length pseudomorphic AlGaAs/InGaAs MODFETs. Using C-V measurements, they estimate that a two-dimensional electron gas (2DEG) with density as high as 1.0×10¹² cm^-2 can be accumulated in the InGaAs channel at 77 K before the gate begins to modulate parasitic charges in the AlGaAs. This improvement in charge control of about 10-30% over a typical AlGaAs/GaAs MODFET may partially be responsible for the superior DC and RF performance of the AlGaAs/InGaAs MODFET. At room temperature, the devices give a maximum DC voltage gain g _m/g_d of 32 and a current gain cutoff frequency f_T of 46 GHz. These results are state of the art for MODFETs of similar gate length     

Time-resolved studies of the C-A transition inavalanche discharges: fluorescence and gain-loss studies

Time-resolved XeF C-A fluorescence and gain-loss studies were conducted in an avalanche discharge using arc-type UV preionization in a variety of devices that deliver peak powers from 1 to 13 MW/cm³ in time intervals from 10 to 30 ns. The results coupled with extensive fluorescence measurements give indications of the possibility of developing a successful XeF C-A transition avalanche discharge tester. Fluorescence studies giving relative upper state densities as a function of different gas mixtures correlate well with the peak gain observed. Thus, relative peak fluorescence intensities are a good gauge for the best mixture for C -A transition lasing