A review on the humidity reliability of high power white light LEDs

High power white LEDs are replacing current lighting sources, not only for indoor usage, but also for outdoor and harsher environmental applications. This calls for higher reliability with respect to electrical, thermal as well as humidity. In this work, a comprehensive review on the study of humidity reliability of high power LEDs is provided, and the humidity induced degradation mechanisms in packaged high power white LEDs and their failure sites are described. The failure degradation mechanisms are divided into three groups, namely the package level, chip level and interconnect level degradations. Modeling of the moisture degradation is also described, and new test designed for the humidity study is also introduced. The inability of current acceleration model to extrapolate accelerated test results to normal operating conditions for high power LEDs is shown, and this provides a new challenge for the estimation of the lifetime of high power LEDs under normal applications, along with other challenges that need to be addressed.     

Fabrication process simulation and reliability improvement of high-brightness LEDs

To enhance the light extraction efficiency and thermal performance of AlGaInP light-emitting diodes (LEDs), the wafer bonding technique which can replace the GaAs substrate with other high thermal conductivity substrates was applied. However, this technique may make the film crack during either the removal etching process of the GaAs substrate or the annealing process after the GaAs removal. Therefore, this crack problem is an important issue in the reliability/yield of high-brightness LEDs. In this research, a detailed finite element model of the high-brightness AlGaInP LED, which is replaced by the GaAs substrate with high thermal conductivity substrate through the Au–In metal bonding technique, was developed and fabricated. In addition, the mechanical behavior of wafer-level metal bonding was also simulated by finite element analysis (FEA) and validated by experimental measurements. Hence, the above validated simulation technique combined with process modeling is used to understand the stress variation of the multilayer structure of AlGaInP LED during the fabrication process and to find the principal cause of the film crack.     

大功率白光LED封装设计与研究进展

封装设计、材料和结构的不断创新使发光二极管(LED)性能不断提高.从光学、热学、电学、机械、可靠性等方面,详细评述了大功率白光LED封装的设计和研究进展,并对封装材料和工艺进行了具体介绍.提出LED的封装设计应与芯片设计同时进行,并且需要对光、热、电、结构等性能统一考虑.在封装过程中,虽然材料(散热基板、荧光粉、灌封胶)选择很重要,但封装工艺(界面热阻、封装应力)对LED光效和可靠性影响也很大.     

Wafer-Level Modular Testing of Core-Based SoCs

Product cost is a major driver in the consumer electronics market, which is characterized by low profit margins and the use of core-based system-on-chip (SoC) designs. Packaging has been recognized as a significant contributor to the product cost for such SoCs. To reduce packaging cost and the test cost for packaged chips, wafer-level testing (wafer sort) is used in the semiconductor industry to screen defective dies. However, since test time is a major practical constraint for wafer sort, even more so than for package test, not all the scan-based digital tests can be applied to the die under test. We present an optimal test-length selection technique for wafer-level testing of core-based SoCs. This technique, which is based on a combination of statistical yield modeling and integer linear programming, allows us to determine the number of patterns to use for each embedded core during wafer sort such that the probability of screening defective dies is maximized for a given upper limit on the SoC test time. We also present a heuristic method to handle large next-generation SoC designs. Simulation results are presented for five of the ITC'02 SoC Test benchmarks, and the optimal test-length selection approach is compared with the heuristic method.     

晶圆级封装非制冷大面阵红外探测器应用分析

红外成像系统已经应用到军事和民用领域多年,但一直没得到广泛应用,主要原因是其分辨率低、成本高、工艺不稳定和技术门槛高等。解决这些问题需要从传感器工艺、探测器封装、红外图像处理芯片等方面加以改进。红外技术未来会朝低成本、专用处理芯片、高分辨率等方向发展。目前,国内厂商陆续推出了晶圆级封装(Wafer-Level Package,WLP)、高分辨率探测器和专用图像处理芯片等方面的新产品。但采用这些新器件的红外成像系统却没有得到相应的研究。本文主要基于烟台艾睿光电科技有限公司新推出的晶圆级封装的1280×1024元红外探测器以及专用图像处理芯片的实际应用,在系统架构、结构散热、成像算法等方面对由新器件构建的红外成像系统进行了验证分析。     

Wafer-level packaging of silicon to glass with a BCB intermediate layer using localised laser heating

Adhesive wafer-level bonding is an excellent solution to meet the stringent requirements in micro-electro-mechanical systems (MEMS) packaging, one of the challenges in MEMS manufacturing, in a steadily growing micro-systems market. A range of bonding processes for commercially available substrate bonders have been developed, which apply global heating during the bonding procedure. This article, however, describes an approach where heating is kept to a minimum by combining the merits of laser joining, a truly localised heating technique, and adhesive wafer-level bonding. This unique bonding technique, which enables the use of temperature-sensitive materials within the package, is demonstrated for bonding of silicon to glass - materials commonly used in MEMS fabrication - with a benzocyclobutene (BCB) intermediate bonding layer. As a proof of concept for wafer-level packaging, bonding of two simplified patterns is demonstrated, one with five individual samples on the same wafer, and the other with nine samples. To verify the influence of this innovative bonding technique on the quality of the seal the devices are shear force tested and the results are compared with those of devices packaged at chip-level.     

380‐nm Ultraviolet Light‐Emitting Diodes with InGaN/AlGaN MQW Structure

In this paper, we demonstrate the capabilities of 380‐nm ultraviolet (UV) light‐emitting diodes (LEDs) using metal organic chemical vapor deposition. The epi‐structure of these LEDs consists of InGaN/AlGaN multiple quantum wells on a patterned sapphire substrate, and the devices are fabricated using a conventional LED process. The LEDs are packaged with a type of surface mount device with Al‐metal. A UV LED can emit light at 383.3 nm, and its maximum output power is 118.4 mW at 350 mA.     

一种电容间隙精确可控的高对称加速度传感器

提出了一种高对称电容式微加速度传感器,该传感器为硅四层键合三明治结构,在完成传感器整体结构制作的同时,实现了圆片级真空封装。利用多次氧化的方法,既精确控制了加速度传感器的初始电容间距,又实现了限位凸点的制作。该加速度传感器的谐振频率为657Hz,品质因子为198,灵敏度为0.59V/g。     

Luminous efficacy and color rendering index of high power white LEDs packaged by using red phosphor

We packaged a series of high power white LEDs by covering the blue LED chips with yellow phosphor, red phosphor and the two phosphors mixed by appropriate mass ratio,respectively,and discussed the excitation and emission spectrum of yellow phosphor and red phosphor and the characteristics of the LEDs.We found that the luminous efficacy of the white LEDs covered with the two phosphors mixed by appropriate mass ratio was lower than that of the white LEDs covered with yellow phosphor,but the color rendering index was improved observably.     

Large area flexible lighting foils using distributed bare LED dies on polyester substrates

Integration of LEDs on flexible foil substrates is of interest for flexible lighting applications and for backlights for flexible displays. Such a large area lighting device can be made by integrating a matrix of closely spaced LEDs on a flexible foil substrate. Preferably, these LEDs are integrated unpackaged, i.e. as bare dies, as this reduces footprint, thickness and cost. As substrates, low cost materials like polyethylene terephthalate (PET) should preferably be used. However, the use of these materials also imposes limitations. Especially, their low thermal stability limits the maximum temperatures during the processing and the thermal dissipation of the LED during operation will pose constraints on the thermal design. This paper describes the results of research on possibilities for integrating bare die LEDs with such low cost flexible PET foils. Bonding of LED dies on PET substrates with copper circuitry using conductive adhesives was performed. Both anisotropic conducting adhesives and isotropic conducting adhesives were investigated. An experimental comparison is made between the different techniques based on temperature/humidity reliability and flexural stability of the bonded LEDs. Additionally, finite element (FE) thermal modeling results of adhesively bonded LED-on-foil configurations are presented. The role of the different materials and the effect of their geometries on the temperature distribution in the simulated devices are discussed. The results are compared to experimentally observed temperature distributions using infrared thermal imaging in LED on PET foil reference devices. Finally a demonstrator device of 64 LEDs on flexible copper–PET substrate is presented.     

Effect of Different Quantum Well Structures on the Output Power Performance of GaN-Based Light-Emitting Diodes

We investigated the effect of two different quantum well (QW) structures having different indium contents on the optical performance of fully packaged GaN-based light-emitting diodes (LEDs). Dual-spectrum QW LEDs exhibit ～4% higher external quantum efficiency (at 350 mA) than single-spectrum QW LEDs. However, the two types of LEDs exhibit similar efficiency droop behavior. For both types of LEDs, the output power decreases with increasing junction temperature. When the junction temperature exceeds 70°C, the dual-spectrum QW LEDs exhibit lower output power than the single-spectrum QW LEDs. The wavelength dependence of the output power (at 350 mA) of single-spectrum QW LEDs shows that the LEDs with shorter wavelengths experience more rapid optical degradation than the LEDs with longer wavelengths. Based on the wavelength- and junction-temperature-dependent output power, the droop behavior of the dual-spectrum QW LEDs is described and discussed.     

超薄型圆片级芯片尺寸封装技术

ShellCase公司的圆片级封装技术工艺,采用商用半导体圆片加工设备,把芯片进行封装并包封到分离的腔体中后仍为圆片形式。圆片级芯片尺寸封装(WL-CSP)工艺是在固态芯片尺寸玻璃外壳中装入芯片。玻璃包封防止了硅片的外露,并确保了良好的机械性能及环境保护功能。凸点下面专用的聚合物顺从层提供了板级可靠性。把凸点置于单个接触焊盘上,并进行回流焊,圆片分离形成封装器件成品。WL-CSP封装完全符合JEDEC和SMT标准。这样的芯片规模封装(CSP),其测量厚度为300μm-700μm,这是各种尺寸敏感型电子产品使用的关键因素。     

Ultrathin wafer level chip size package

The ShellCase wafer-level packaging process uses commercial semiconductor wafer processing equipment. Dies are packaged and encapsulated into separate enclosures while still in wafer form. This wafer level chip size package (WLCSP) process encases the die in a solid die-size glass shell. The glass encapsulation prevents the silicon from being exposed and ensures excellent mechanical and environmental protection. A proprietary compliant polymer layer under the bumps provides on board reliability. Bumps are placed on the individual contact pads, are reflowed, and wafer singulation yields finished packaged devices. This WLCSP fully complies with Joint Electron Device Engineering Council (JEDEC) and surface mount technology (SMT) standards. Such chip scale packages (CSP's) measure 300-700 μm in thickness, a crucial factor for use in various size sensitive electronic products     

Luminous efficacy and color rendering index of high power white LEDs packaged by using red phosphor

We packaged a series of high power white LEDs by covering the blue LED chips with yellow phosphor, red phosphor and the two phosphors mixed by appropriate mass ratio, respectively, and discussed the excitation and emission spectrum of yellow phosphor and red phosphor and the characteristics of the LEDs. We found that the luminous efficacy of the white LEDs covered with the two phosphors mixed by appropriate mass ratio was lower than that of the white LEDs covered with yellow phosphor, but the color rendering index was improved observably.     

Vertical InGaN light-emitting diodes with Ag paste as bonding layer

Vertical InGaN-based light-emitting diodes (LEDs) were fabricated with a Si substrate using Ag paste as bonding layer. Vertical LEDs with Ag paste bonding layer were bonded with Si substrate at a low temperature of 140 °C. In addition to the low-temperature bonding process, the soft property of Ag paste could better alleviate thermal stress compared with conventional eutectic metal bonding layer such as Au–Sn. Under the same test conditions, these two LEDs showed similar optical and electrical properties and reliability. However, LEDs with Ag-paste bonding layer were fabricated through a low-temperature bonding process. The characteristic of soft solder enables a relatively wider process window, such as bonding pressure and temperature, and a higher yield as compared with the vertical LEDs with Au–Sn eutectic bonding layer.     

Ohmic-Contact Technology for GaN-Based Light-Emitting Diodes: Role of P-Type Contact

GaN-based semiconductors are of great technological importance for the fabrication of optoelectronic devices, such as light-emitting diodes (LEDs) and laser diodes. The further improvement of LED performance can be achieved through the enhancement of external quantum efficiency. In this regard, high-quality p-type ohmic electrodes having low contact resistance and high transmittance (or reflectivity), along with thermal stability, must be developed because p-type ohmic contacts play a key role in the performance of LEDs. In this paper, we review recent advances in p-type ohmic-contact technology for GaN-based LEDs. A variety of methods for forming transparent and reflective ohmic contacts are introduced.     

GaN基功率型LED芯片散热性能测试与分析

与正装LED相比,倒装焊芯片技术在功率型LED的散热方面具有潜在的优势.对各种正装和倒装焊功率型LED芯片的表面温度分布进行了直接测试,对其散热性能进行了分析.研究表明,焊接层的材料、焊接接触面的面积和焊接层的质量是制约倒装焊LED芯片散热能力的主要因素;而对于正装LED芯片,由于工艺简单,减少了中间热沉,通过结构的优化,工艺的改进,完全可以达到与倒装焊LED芯片相同的散热能力.     

Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die

The cost and quality of a multichip assembly is highly dependentupon the cost and quality of the incoming die. In the case of a baredie assembly, it is often highly desirable to use either Known Good Die(KGD) or die that have been burned-in and tested to the same level ofquality and reliability as their packaged die equivalents. However,performing full bare die burn-in and test may not always becost-effective. This paper examines the question of whether it isalways necessary to use KGD to produce a cost-effective multichipmodule (MCM) of acceptable quality. A process-flow based cost modelis used to compare the cost and quality of MCMs assembled with KGD toMCMs assembled with die that have received wafer-level test only. Inaddition to test effectiveness at the wafer, die, and module level,factors that are considered include die complexity (size and I/O), number of die per MCM, the cost of producing the KGD, andrework costs and effectiveness. The cost model captures inputs fromwafer fabrication through MCM assembly and rework. Monte Carlosimulation is used to account for uncertainty in the input data.The resulting sensitivity analyses give final MCM cost and quality asa function of the various factors for both KGD and die that havereceived wafer-level test only.     

Critical issues of wafer level chip scale package (WLCSP) withemphasis on cost analysis and solder joint reliability

Some of the critical issues of wafer level chip scale package (WLCSP) are mentioned and discussed in this investigation. Emphasis is placed on the cost analysis of WLCSP through the, important parameters such as wafer-level redistribution, wafer-bumping, and wafer-level underfilling. Useful and simple equations in terms of these parameters are also provided. Furthermore, the effects of microvia build-up layer on the solder joint reliability of WLCSP on printed circuit board (PCB) through the creep responses such as the deformation, hysteresis loops, and stress and strain are presented. Only solder-bumped with pad-redistribution WLCSPs are considered in this study     

Development of a thermal resistance model for chip-on-board packaging of high power LED arrays

The performance of high power LEDs strongly depends on the junction temperature. Operating at high junction temperature causes degradation of light intensity and lifetime. Therefore, proper thermal management is critical for LED packaging. While the design of the heat sink is a major contributor to lowering the overall thermal resistance of the packaged luminaire, another area of concern arises from the need to address the large heat fluxes that exist beneath the die. In this study we conduct a thermal analysis of high power LED packages implementing chip-on-board (COB) architecture combined with power electronic substrate focusing on heat spreading effect. An analytical thermal resistance model is presented for the LED array and validated by comparing it with finite element analysis (FEA) results. By using the analytical expression of thermal resistance, it is possible to understand the impact of design parameters (e.g., material properties, LED spacing, substrate thickness, etc.) on the package thermal resistance, bypassing the need for detailed computational simulations using FEA.