并行BIST可测性设计

提出了ＢＩＳＴ的并行结构，分析了其工作原理。实验结果表明，该方法的测试速度比一般ＢＩＳＴ的速度快Ｋ倍（Ｋ为并行度），而硬件花费与一般ＢＩＳＴ结构相当。     

并行折叠计数器的BIST方案

 本文提出了一种新的基于初始状态的并行折叠计数结构,并给出了建议的多扫描链的BIST方案.与国际上同类方法相比,该方案需要更少的测试数据存储容量、更短的测试应用时间,其平均测试应用时间是同类方案的0.265%,并且能很好地适用于传统的EDA设计流程.     

An on-line BIST RAM architecture with self-repair capabilities

The emerging field of self-repair computing is expected to have a major impact on deployable systems for space missions and defense applications, where high reliability, availability, and serviceability are needed. In this context, RAM (random access memories) are among the most critical components. This paper proposes a built-in self-repair (BISR) approach for RAM cores. The proposed design, introducing minimal and technology-dependent overheads, can detect and repair a wide range of memory faults including: stuck-at, coupling, and address faults. The test and repair capabilities are used on-line, and are completely transparent to the external user, who can use the memory without any change in the memory-access protocol. Using a fault-injection environment that can emulate the occurrence of faults inside the module, the effectiveness of the proposed architecture in terms of both fault detection and repairing capability was verified. Memories of various sizes have been considered to evaluate the area-overhead introduced by this proposed architecture     

Parallel architecture for prototype training

The letter suggests an efficient parallel hardware architecture for prototype training in pattern recognition. Sample means and covariance matrices are computed by the same architecture and much attention is paid to the implementation of covariance matrices. A k2-chip of processor elements is used to implement covariance matrices.     

Test Cycle Count Reduction in a Parallel Scan BIST Environment

This paper describes a novel method that can be used to reduce test cycle count in a parallel access scan based Built-In-Self-Test (BIST) environment. An algorithm that allows the efficient application of deterministically generated patterns is proposed. This approach allows BIST fault coverage to be increased using deterministic vectors, while minimizing the cost, in terms of test cycles, of applying the vectors.     

BIST architecture for oscillation test of analog ICs and investigation of test hardware influence

In this article, a fully on-chip implementation of the oscillation-based test for analog and mixed-signal systems is presented. The proposed test hardware uses an on-chip reference oscillator to compensate the undesired impact of process parameter variations. Thus, this approach can be easily and effectively implemented also in nanoscale technologies. As the circuit under test (CUT), an operational amplifier designed in a 90 nm CMOS technology was used. The possible influence of additional test hardware on the CUT performance as well as the test reliability were investigated and analyzed. Finally, results obtained by this analysis are discussed.     

Parallel architecture for high-speed Viterbi decoding of convolutional codes

A parallelisation algorithm of decoding convolutional codes with the Viterbi algorithm is presented. The architecture of parallel decoding analysed here suits the VLSI realisation very well and allows high-speed decoding.<>     

BIST scheme for DAC testing

A low-cost, built-in self-test (BIST) scheme for a digital-to-analogue converter (DAC) is presented. The basic idea is to convert the DAC output voltages corresponding to different input codes into different oscillation frequencies through a voltage controlled oscillator (VCO), and further transfer these frequencies to different digital codes using a counter. According to the input and output codes, performances of a DAC, such as offset error, gain error, differential nonlinearity (DNL), integral nonlinearity (INL), could be effectively detected by simply using digital circuits rather than complex analogue ones. In addition, the annoying DAC output noise could be naturally filtered out by this BIST method     

Bit-swapping LFSR for low-power BIST

A modified linear feedback shift register (LFSR) is presented that reduces the number of transitions at the inputs of the circuit-under-test by 25% using a bit-swapping technique. Experimental results on ISCAS'85 and 89 benchmark circuits show up to 45% power reduction during test. They also show that the proposed design can be combined with other techniques to achieve a very substantial power reduction of up to 63%.     

嵌入式系统的在线自测试技术

嵌入式系统必须满足用户对其越来越高的安全性和可靠性的要求，作者首先审视了用于测试数字系统故障的各种在线可测试技术，然后重点讨论了一种将被广泛应用于嵌入式系统的在线测试技术－内建自测试技术。     

片上网络通信架构的BIST测试方法

为了保证NoC(network on chip,片上网络)中IP核之间的正确通信,需要对片上网络通信架构进行测试。本文针对Mesh NoC的功能测试,提出了一种测试通信架构的BIST(built-in self test,内建自测试)方法。该方法在NI(network interface,资源网络接口)中添加BIST模块TPG(test pattern generator,测试向量产生器)和TRA(test response analyzer,测试响应分析器),利用TPG产生测试数据,TRA分析测试响应,来实现通信架构的测试过程。实验结果表明,该方法在增加面积开销较小的情况下,不仅降低了测试成本,还降低了测试时间。     

BIST structure for DAC testing

A built-in self-test (BIST) structure for digital-to-analogue converter (DAC) testing is presented. The basic idea is to divide the input codes (0, 1, ..., 2ⁿ-1) of the DAC under test into a number of segments. The DAC output voltages corresponding to different codes in the same segment are amplified to the same voltage value. Such that one single reference voltage can be used to test all codes in the same segment. By this method, the number of reference voltages required for DAC testing can be greatly reduced. We show that offset error, gain error, integral nonlinearity (INL) and differential nonlinearity (DNL) are effectively detected in the proposed BIST structure     

Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders

Standard VLSI implementations of turbo decoding require substantial memory and incur a long latency, which cannot be tolerated in some applications. A parallel VLSI architecture for low-latency turbo decoding, comprising multiple single-input single-output (SISO) elements, operating jointly on one turbo-coded block, is presented and compared to sequential architectures. A parallel interleaver is essential to process multiple concurrent SISO outputs. A novel parallel interleaver and an algorithm for its design are presented, achieving the same error correction performance as the standard architecture. Latency is reduced up to 20 times and throughput for large blocks is increased up to six-fold relative to sequential decoders, using the same silicon area, and achieving a very high coding gain. The parallel architecture scales favorably: latency and throughput are improved with increased block size and chip area.     

一种新型低峰值功耗的BIST设计研究

随着手持设备的兴起和芯片对晶片测试的要求越来越高,内建自测试的功耗问题引起了越来越多人的关注。文章对目前内建自测试的可测性设计技术进行了分析,并提出了折叠种子优化降低节点峰值功耗的模型,通过调整种子结构和测试向量的相关性的办法来避免过高的SoC测试峰值功耗。采取了屏蔽无效测试模式生成、提高应用测试向量之间的相关性以及并行加载向量等综合手段来控制测试应用,使得测试时测试向量的输入跳变显著降低,从而大幅度降低节点的峰值功耗。实验结果表明,该方案可以有效地避免BIST并行执行可能带来的过高峰值功耗。     

实用模拟BIST的基本原则

实用模拟BIST有潜力降低IC测试成本,以及产品上市时间。20多年来,研究人员和半导体制造商一直在试图开发一种针对混合信号IC的实用模拟BIST(内置自检)。这种技术能够用数字测试仪作混合信号IC测试,以及简化的多址测试,从而能减少IC测试成本,以及IC上市时间。其它预期优点还有更快的测试开发,以及系统上的自检等。     

存储器内建自测试的程序控制方法

文中提出了一种利用处理器的指令系统编写特定程序,通过程序运行来控制完成整个存储器内建自测试过程的方法.基于此方法的设计已经成功应用于一款处理器中,有效地提高了芯片的可测试性和应用系统的容错性.     

片上网络存储器的BIST电路设计

片上网络（Network-on-Chip ,NoC）作为解决片上系统存在的问题而提出的一种解决方案,正受到越来越多的关注,测试技术是NoC设计工作的重要组成部分。该设计针对NoC系统中SRAM存储器模块,研究了SRAM的故障模型,建立了片上网络通信架构的功能模型,复用片上网络作为测试存取路径,设计完成了基于M arch C＋算法的BIST电路设计。该方案采用Verilog语言完成设计,并且在基于FPGA的NoC系统平台上实现了对SRAM的测试。实验结果表明,在面积开销增加较小的情况下,该方法具有较高的故障覆盖率。     

Efficient test-point selection for scan-based BIST

We propose a test point selection algorithm for scan-based built-in self-test (BIST). Under a pseudorandom BIST scheme, the objectives are (1) achieving a high random pattern fault coverage, (2) reducing the computational complexity, and (3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing information is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits. The experimental results show the proposed algorithm achieves higher fault coverages than previous approaches,with a significant reduction of computational complexity. By taking timing information into consideration, the performance degradation can he minimized with possibly more test points     

Testability Trade-Offs for BIST Data Paths

Power dissipation during test application is an emerging problem due to yield and reliability concerns. This paper focuses on BIST for RTL data paths and discusses testability trade-offs in terms of test application time, BIST area overhead and power dissipation.