高速多媒体桌域网的结构体系技术研究

桌域网是一种适合于多媒体业务传输的小型高速网络。本文论述高速多媒体桌域网的概念,结构体系和主机接口。在介绍桌域网的设计目标和特性之后着重分析桌域网的结构体系和两种主机接口的特点,并给出其应用前景。     

桌域网及其新技术的研究

桌域网是一种适合于多媒体业务需要的小型ATM网 ,是对传统计算机网络的体系结构的一种补充。本文介绍了设计桌域网的基本策略 ,讨论了它的设计目标和特性 ,给出了桌域网的体系结构、网络接入设备及其性能 ,最后提出研究桌域网的几点建议。     

宽带城域网技术和体系结构的探讨

通过对ＩＰ和ＡＴＭ技术的分析及优缺点的比较,阐述了ＡＴＭ＋ＩＰ将是城域网建设量佳的技术选择。通过分析宽带城域网的体系结构,阐明了各网络节点的功能,为我国宽带载域网的建设提供一种参考。     

基于Native Mode ATM API的应用系统模型及关键技术

ＡＴＭ技术作为Ｂ－ＩＳＤ的基础，在传输包括话音、图像、数据的综合业务环境中具有现有其它网络技术所不具备的技术优势，然而目前真正基于ＡＴＭＮａｔｉｖｅＭｏｄｅ的应用还很少，而大量基于Ｏｖｅｒｌａｙ Ｍｏｄｅ的ＡＴＭ应用不能充分发挥ＡＴＭ技术的优势。随着信息技术的发展，将会有大量的综合业务应用出现，它具有和传统数据通信安全不同的业务特性，必须通过一种灵活，高效的应用程序接口给予支持，本文提出基于Ｎａｔ     

ATM局域网的业务要求和交换要求

ＩＥＥＥ８０２系列规定了局域网的协议。如何提供ＡＴＭ接口使其与现有局域网互连，支持ＡＴＭ局域网的ＡＴＭ交换技术需要考虑哪些因素，本文对这两个问题作了一些探讨。     

智能终端对WCDMA核心网分组域网络影响的探讨

文章分析了智能终端引起信令剧增的原因,探讨了快速增长的信令对现有分组域网的影响,并从现有网元扩容和引入新技术两方面提出了解决方法。     

ATM网络拥塞控制的新策略

文章简要介绍了ＡＴＭ网络的虚通路概念和ＡＴＭ网络拥塞产生的原因，分析了现有拥塞控制方案的不足，并通过分析提出了基于虚通路（ＶＰ）改善ＡＴＭ的拥塞控制和新策略。     

电信英语及其缩略语解释(三)

ＡＡＮ Ａｌｌ Ａｒｅａ Ｎｅｔｗｏｒｋｉｎｇ 全域网ＡＡＲ Ａｕｔｏｍａｔｉｃ Ａｌｔｅｒｎａｔｉｖｅ Ｒｏｕｔｅｉｎｇ 自动迂回路由ＡＢＩ Ａｐｐｌｉｃａｔｉｏｎ Ｂｉｎａｒｙ Ｉｎｔｅｒｆａｃｅ 应用程序二进制接口ＡＢＴ ＡＴＭ Ｂｌｏｃｋ Ｔｒａｎｓｆｅｒ ＡＴＭ成组传送ＡＣ Ａｌｔｅｒｎａｔｉｎｇ Ｃｕｒｒｅｎｔ 交（变电）流ＡＣＥＣ Ａｄｖｉｓｏｒｙ Ｃｏｍｍｉｔｔｅｅ ｏｎ　Ｅｌｅｃｔｒｏｍａｇｎｅｔｉｃ Ｃｏｍｐａｔｉｂｉｌｉｔｙ 电磁兼容咨询委员会ＡＣＥＴ Ａｄｖｉｓｏｒｙ Ｃｏｍｍｉｔｔｅｅ ｏｎ Ｅｌ…     

诺基亚成功完成DSLAM连接IP接口实验

近日,诺基亚在中国成功完成了最新版本的Ｄ５０ｅ系统连接ＩＰ接口的用户现场实验,使用效果良好。为满足没有ＡＴＭ网络或ＡＴＭ端口不足的地区开展ＡＤＳＬ业务的需求,诺基亚在其已广泛使用的ＤＳＬＡＭ设备Ｄ５０ｅ上开发了网络侧１００Ｍ以太网接口。该接口可将用户端ＡＤＳＬ数据流集中到现有的城域网上,充分利用城域网的传输能力为ＡＤＳＬ用户提供高速以太网接入等业务。最新版本的Ｄ５０ｅ系统可以同时或分别提供ＡＴＭ和以太网上行接口,为用户提供最大的组网灵活性并提高现有网络利用率。（）诺基亚成功完成DSLAM连接IP接口…     

基于TMN的ATM网络管理

ＡＴＭ已从一种标准和原型变成了下一代的变换技术，随着大量的ＡＴＭ交换机进入网络，迫切需要与之相应的ＡＴＭ网络管理技术。本文重点讨论了如何将计算机和电信方法综合用于ＡＴＭ网络管理，特别是ＳＮＭＰ和ＣＭＩＰ协议在ＡＴＭ网络中的应用。另外，本文也讨论了ＴＭＮ接口及其与ＡＴＭ的网络元素ＮＥ的通信方式。     

Hierarchical Krylov subspace based reduction of large interconnects

In this paper, we propose a new model order reduction approach for large interconnect circuits using hierarchical decomposition and the Krylov subspace projection-based model order reduction methods. The new approach, called hiePrimor, first partitions a large interconnect circuit into a number of smaller subcircuits and then performs the projection-based model order reduction on each of subcircuits in isolation and on the top-level circuit thereafter. The new approach is very amenable for exploiting the multi-core based parallel computing platforms to significantly speed up the reduction process. Theoretically we show that hiePrimor can deliver the same accuracy as the flat reduction method given the same reduction order and it can also preserve the passivity of the reduced models as well. We also show that partitioning has large impacts on the performance of hierarchical reduction and the minimum-span objective should be required to attain the best performance for hierarchical reduction. The proposed method is suitable for reducing large global interconnects like coupled bus, transmission lines, large clock nets in the post-layout stage. Experimental results demonstrate that hiePrimor can be significantly faster and more scalable than the flat projection methods like PRIMA and be order of magnitude faster than PRIMA with parallel computing without loss of accuracy. Interconnect circuits with up to 4 million nodes can be analyzed in a few minutes even in Matlab by the new method.     

Satellite ATM for broadband ISDN

This paper presents the development of satellite ATM for broadband ISDN based on the Research in Advanced Communications in Europe (RACE) CATALYST project. The purpose of the project is to develop an experimental ATM satellite link for the future B-ISDN services, particularly for the interconnections of the ATM testbeds which are in the form of broadband islands developed in Europe. Then initial ATM based B-ISDN can be introduced by interconnections of these broadband islands. An evolutionary approach has been adopted in the development of the ATM networks that the CATALYST project has developed the equipment to be able to interconnect the newly developed ATM testbeds as well as the existing networks such as DQDB, FDDI and Ethernet networks. In March 1994, the project carried out an experiment on the second demonstratoras the Laboratories of Alcatel Telespace in Nanteere near Paris to demonstrate the capability of the satellite ATM connections supporting data, voice, video and multimedia applications. This experiment provided a real system demonstration of satellite ATM for B-ISDN. In the light of the experiment, this paper presents the model and architecture of the ATM satellite equipment, studies the relevant issues and the impact of ATM-via-satellite on the applications and the protocols, and evaluates of satellite ATM based on some measured and simulated results.     

Frame Relay to ATM interworking

Frame Relay is a well-established technology that has attracted a large number of customers world-wide. It is typically used to interconnect large, multi-site company local area networks (LANs). These data connections are usually at low to medium speeds. Asynchronous transfer mode (ATM) is a newer, broadband technology that is capable of very high speed LAN interconnection. In addition, it is arguably an ideal transport medium for legacy protocols such as Frame Relay.This paper describes the data transport features of each technology and discusses how ATM may be used to interconnect existing Frame Relay networks, and how an ATM user may exchange data with a Frame Relay user.     

基于Xilinx MicroBlaze多核嵌入式系统的设计

MicroBlaze核是嵌入在Xilinx FPGA之中的属于32位RISC Harvard架构软处理器核。针对Xilinx MicroBlaze软处理器的核间互连,实现多处理器核之间的快速通信的目的,采用了PLB和FSL总线混连的方法,利用xps_mail-box和xps_mutex核完成核间的通信与同步,通过在Xilinx EDK平台下,将3个软处理器核嵌入到FPGA Spartan-3E芯片上的试验,开发出了一个运行在FPGA上的基于多处理器的嵌入式可编程片上系统,得出此种多核处理器混连的可行性与实用性,核间通信速度得到提升的结论。     

宽带应用及其特点

本文研究了远程数学，ＬＡＮ互连、医疗图像传递和业务量聚集这４种宽带应用的特点，并说明了用于支持这些宽带应用的技术－异步转移模式（ＡＴＭ）。ＡＴＭ之所以被选用是因为它能灵活支持这些应用的千差万别的需要。本文讨论的正是ＡＴＭ技术的直接应用。     

基于PCI总线的ATM网络适配卡设计

ATM终端设备因其综合的业务特点，高效呆靠的传输，可协商的QoS保证等特点而具有独特的优势。但是由于其较高的成本等原因一直未能被广泛的接受。针对这一特点，本文利用EDA技术，设计了一种用于ATM终端设备的基于PCI总线的ATM网络适配卡。     

SSMCB: Low-Power Variation-Tolerant Source-Synchronous Multicycle Bus

In this paper, a variation-tolerant low-power source-synchronous multicycle bus (SSMCB) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3-D ICs. SSMCB replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMCB scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die process variations. Monte Carlo circuit simulations show that SSMCB eliminates 90% of the variation-induced performance degradation in a six-cycle 9-mm-long 16-bit conventional bus.      

Scalable optoelectronic ATM networks: the iPOINT fully functionaltestbed

Our prototype of a fully-functional asynchronous transfer mode (ATM) switch validates the design of a 128 Gb/s optoelectronic ATM switch. Optoelectronics, rather than all optical components, are used to simultaneously address all of the specific requirements mandated by the ATM protocol. In this paper, we present the Illinois pulsar-based optical interconnect (iPOINT) testbed, and present our results obtained for the prototype switch in a working environment consisting of an optical network of Sun SPARC Stations and other local and wide-area ATM switches     

Accurate on-chip interconnect evaluation: a time-domain technique

This paper describes an on-chip sampling and measurement technique for accurate (<15 ps) evaluation of interconnect delays and coupled noise. We have used this nonintrusive time-domain technique to extract in situ driver/receiver waveforms, propagation delays, and coupled noise in 120 interconnect structures. The effects studied include multiple AC returns through active devices, gridded planes on adjacent layers, via impedances, variable driver impedances, and noise in bus structures. The results provide a comprehensive evaluation of interconnect delays and noise in a 1.8 V, 0.25 μm process