以智能型混合信号FPGA开发真正符合需求的系统

单芯片系统对嵌入式系统设计师来说，往往会随着其面对的不同的系统设计而各有不同。例如，在庞大的娱乐或通信消费产品市场中，S0C意味着一颖具有数百万逻辑门的集成电路（IC），其中包含许多大型定制逻辑模块，并有将芯片的数字处理性能与外部世界连接的混合信号功能。     

Self: a self-timed systems design technique

An asynchronous CMOS circuit technique that can realise both combinatorial and sequential logic is introduced. Circuits so designed exhibit correct operation that is independent of wiring delays. An example of a first-in, first-out (FIFO) memory will be used to illustrate the technique.     

用SPartan-3 FPGA实现高性能DSP

Spartan-3 FPGA实现嵌入式DSP突破性成本点 所有低成本FPGA都能够以具有吸引力的价格提供基本逻辑能力,满足范围广泛的通用设计需求.但是,当您考虑在FPGA结构内实现嵌入式DSP功能时,您也许会觉得必须得选择一款高端FPGA,才能获得诸如嵌入式乘法器和分布式存储器等平台特性.     

FPGA视频和图像处理方案

引言 在本文中,我们将关注视频和图像处理技术的发展趋势,在这种趋势下,开发人员不得不重新审视他们过去一直采用的体系结构.本文将讨论不同体系结构的优缺点,阐述Altera在该领域中新方案的详细情况和基本要求.采用低成本FPGA和结构化ASIC,高清晰解决方案的实施成本现在已经低于25美金.     

利用FPGA实现低成本汽车多总线桥接

汽车中的电子单元持续快速增长,因此对比一下汽车电子发展和消费类电子便携式产品的发展会有很大启发.今天的消费者希望在汽车中获得手持便携式电子设备所提供的方便与舒适性.汽车电子将不再专门用于引擎管理系统或车身控制,而是扩展应用到新的领域,如信息娱乐、通信以及司机/乘客辅助系统.     

用CPLD实现码速变换

本文介绍利用可编程器件ＣＰＬＤ实现计算机异步速率(５７．６ｋ、２３０．４Ｋ、４６０．８ｋ等)向相邻标准速率(６４k、２５６ｋ、５１２ｋ等)变换的原理及设计方法,为实现ＰＣ机异步数据与同步设备相连接提供了一种简易的实现方法。     

Using expert systems to implement a semantic data model of a large mass store system

The successful development of large volume data storage systems will depend not only on the ability of the designers to store data, but on the ability to manage such data once it is in the system. Our hypothesis is that mass storage data management can only be implemented successfully based on highly “intelligent” meta data management services. Such services would allow database administrators and users to manipulate, update, and access data and related information and knowledge in a logical manner, and yet would be powerful enough to support the performance needs of a large mass store system. Historically, there have been attempts at building data management services for very large volume data systems; however, when the amount of data being managed got large the meta database itself failed as a consequence of its own size and complexity.

However, if the standard were expanded to include the semantics and pragmatics of the data domain using a Semantic Data Model (SDM), the result would be an overall information system design that is organized and accessible in the context of the data's user and purpose. The implementation of an SDM requires the application of Artificial Intelligence (AI) and related computer science technologies such as object oriented representation, property inheritance, and rule-based decision making. Presently, there does not exist unique software for developing SDMs that addresses the complex representation of data meta data and related information and knowledge.

This paper presents the results of a demonstration prototype SDM implemented using the expert system development tool NEXPERT OBJECT. In the prototype, a simple instance of a SDM was created to support a hypothetical application for the Earth Observing System, Data Information System (EOS-DIS). The massive amounts of data that EOSDIS will manage requires the definition and design of a powerful information management system to support even the most basic needs of the project. The application domain is characterized by a semantic-like network that represents the data content and the relationships between the data based on user views and on more generalized domain architectural views of the information world. The data in the domain are represented by objects that define classes, types, and instances of the data. In addition, data properties are selectively inherited between parent and daughter relationships in the domain. Based on the SDM, a simple information system design is developed from the low-level data storage media, through record management and meta data management, to the user interface.     

The roles of FPGAs in reprogrammable systems

Reprogrammable systems based on field programmable gate arrays are revolutionizing some forms of computation and digital logic. As a logic emulation system, they provide orders of magnitude faster computation than software simulation. As a custom-computing machine, they achieve the highest performance implementation for many types of applications. As a multimode system, they yield significant hardware savings and provide truly generic hardware. In this paper, we discuss the promise and problems of reprogrammable systems. This includes an overview of the chip and system architectures of reprogrammable systems as well as the applications of these systems. We also discuss the challenges and opportunities of future reprogrammable systems     

如何用FPGA构建更出色的DC/DC调节器

设计人员此前一直使用模拟元件来构建开关模式DC/DC转换器(定制型IC、运算放大器、电阻、电容等),控制反馈回路,并生成开关所需的脉宽调制.使用这种模拟元件时,我们必须考虑一系列因素,包括容差、电气应力、老化漂移以及温度漂移,这样才能确保设计方案的稳定性.现在,我们拥有低成本低功耗FPGA以及模数转换器,使得FPGA能够取代传统的模拟设计方法.     

使用低成本FP晰妙地扩展微处理器的连接

在现代电子系统设计中,微处理器是不可缺少的一个部件。然而,随着系统变得越来越复杂,拥有更广泛的功能和用户接口时,     

利用VMware部署图书馆服务器虚拟化解决方案

以昆明理工大学图书馆的数字资源管理的虚拟化解决方案作为实例,说明采用VMware虚拟化管理服务器在图书馆经费节约、服务器数量增长、管理效率等方面所具有的优势.     

Run-time management of systems with partially reconfigurable FPGAs

Partial reconfiguration (PR) of FPGAs can be used to dynamically extend and adapt the functionality of computing systems by swapping in and out HW tasks. To coordinate the on-demand task execution, we propose and implement a Run-Time System Manager (RTSM) for scheduling software (SW) tasks on available processor(s) and hardware (HW) tasks on any number of reconfigurable regions (RRs) of a partially reconfigurable FPGA. Fed with the initial partitioning of the application into tasks, the corresponding task graph, and the available task mappings, the RTSM controls system operation considering the status of each task and region (e.g. busy, idle, scheduled for reconfiguration/execution, etc). Our RTSM supports task reuse and configuration prefetching to minimize reconfigurations, task movement among regions to efficiently manage the FPGA area, and region reservation for future reconfiguration and execution. We validate the correctness and portability of our RTSM executing an image processing application on two Xilinx-based platforms: ZedBoard and XUPV5. We also perform a more extensive evaluation of its features using a simulation framework, and find that – despite the technology limitations – our approach can give promising results in terms of scheduling quality. Since our RTSM supports also the scheduling of parallel SW tasks, we use it to manage the execution of the entire parallel Edge Detection application on a desktop; we compare the application execution time with that using the OpenMP framework and find that with our RTSM execution is 2.4 times faster than the unoptimized OpenMP version. When processor affinity optimization is enabled for OpenMP, our RTMS and the OpenMP are on par, indicating that the scheduling efficiency of our RTSM is competitive to this state-of-the-art scheduler, while supporting in addition the management of HW tasks.     

基于FPGA的载波调制系统

线路调制单元是电力线载波机的关键部件之一.本文提出并实现了一种利用FPGA芯片完成线路调制的方案.在FPGA芯片中完成信号的正交变换,由FIR滤波器和CIC滤波器实现采样率的变化.通过与载波的相乘完成整个调制过程     

Use of current sensing technique in designing asynchronous staticRAM for self-timed systems

The conventional static RAM was modified so that it can communicate with other self-timed systems. The four-phase handshake control protocol was used and the current-sensing completion detection (CSCD) technique was studied for the read completion signal generation. The authors present the implementation and simulation results of a test circuit     

用MSP430实现斜率A/D转换

本文结合斜率A/D转换的原理详细说明了MSP430F1121单片机在A/D转换中的应用,给出了典型应用电路和A/D转换的源程序.     

A self-timed real-time sorting network

High-speed networks are expected to carry traffic classes with diverse quality of service (QoS) guarantees. For efficient utilization of resources, sophisticated scheduling protocols are needed; however, these must be implemented without sacrificing the maximum possible bandwidth. This paper presents the architecture and implementation of a self-timed real-time sorting network to be used in packet switches that support a diverse mix of traffic. The sorting network receives packets with appropriately assigned priorities and schedules the packets for departure in a highest-priority-first manner. The circuit implementation uses zero-overhead, self-timed, and self-precharging domino logic to minimize the circuit latency. An experimental sorting network chip has been designed using the techniques described in this paper to support 10 Gb/s links with ATM-size packets     

On-chip timing reference for self-timed microprocessor

A calibratable on-chip timing reference circuit has been developed to enable a self-timed microprocessor to interface to standard offchip memory and peripheral devices. The circuit exhibits several of the desirable properties of self-timed circuitry such as low power consumption and low electromagnetic interference (EMI). In addition, it is highly testable.     

Low-power self-timed circuit design technique

An implementation of self-timed circuits whose hardware and control signals are significantly reduced is proposed. A globally asynchronous locally synchronous design using the proposed self-timed circuits is also demonstrated. A design example shows that in this implementation less power is consumed with only a small circuit overhead     

采用FPGA实现医学成像的DSP解决方案

医学成像系统需要基于高级数字信号处理算法进行诊断。过去通常采用软件进行算法开发、编写和修改。然后将软件装入到DSP或ASSP、ASIC中实现，而今采用DSP和FPGA相结合的方案。比传统方案提供更高的性能、更灵活的设计、更低的成本和更短的面市时间。