Continuous-wave frequency synthesis of a laser diode based ondiscrete-time negative frequency feedback. I. Experiment

The absolute frequency synthesis of a distributed-feedback (DFB) laser diode (LD) is demonstrated by use of a loss-compensated optical ring circuit with a frequency shifter and a frequency-stabilized master laser system containing an acetylene (¹³C₂H₂ ) absorption cell. A lightwave from the master laser is modulated into a pulse and circulated around the ring to shift its frequency in the 0~100 GHz range. A continuous-wave from the DFB LD is mixed with a recirculated pulse with a desirable reference frequency, and their beat frequency is counted in order to obtain the error signal. The absolute frequency of the DFB LD is locked to the reference frequency based on discrete-time negative frequency feedback control for the injection current. The accuracy of the absolute frequency was experimentally confirmed to be within a few MHz for an averaging time of 1 s and an operation time of 1 hour     

A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SCtuning loop

A 900-MHz phase-locked loop frequency synthesizer implemented in a 0.6-μm CMOS technology is developed for the wireless integrated network sensors applications. It incorporates an automatic switched-capacitor (SC) discrete-tuning loop to extend the overall frequency tuning range to 20%, while the VCO gain (K_VCO) resulting from the CMOS varactor continuous-tuning is kept low at only 20 MHz/V in order to improve the reference spurs and noise performance. This frequency synthesizer achieves a phase noise of -102 dBc/Hz at 100 kHz offset frequency and reference spurs below -55 dBc. The synthesizer, including an on-chip VCO, dissipates only 2.5 mA from a 3-V supply     

一种实现自调谐频率综合器的算法和结构

在集成的频率综合器中 ,工艺、温度和电源电压的变化使得频率综合器产生的中心频率和频率调谐范围与期望值发生偏移。文中指出了一种自调谐频率综合器的算法和结构 ,利用特殊结构的可编程压控振荡器和自调谐算法实现宽调谐范围的频率综合器 ,进而充分涵盖期望的输出频段。用 0 2 5 μmCMOS工艺设计了一个中心频率 2 2GHz,调谐范围为 338MHz的频率综合器 ,用于IEEE80 2 11b/g无线局域网系统的超外差收发机中 ,可以充分满足标准要求的 80MHz的调谐范围 ;给出了锁定某一目标频率时自调谐算法的具体工作过程 ,结果表明该算法和结构是正确的。     

A fully integrated low-noise 1-GHz frequency synthesizer design formobile communication application

This paper describes a fully monolithic phase-locked loop (PLL) frequency synthesizer circuit implemented in a standard 0.8-μm CMOS technology. To be immune to noise, all the circuits in the synthesizer use differential schemes with the digital parts designed by static logic. The experimental voltage controlled oscillator (VCO) has a center frequency of 800 MHz and a tuning range of ±25%. The measured frequency synthesizer performance has a frequency range from 700 MHz to 1 GHz with -80 dBc/Hz phase noise at a 100 kHz carrier offset. With an active area of 0.34 mm², the test chip consumes 125 mW at maximum frequency from a 5 V supply. The only external components are the supply decoupling capacitors and a passive filter     

The Design and Analysis of a Fully Integrated Multiplying DLL With Adaptive Current Tuning

A multiplying-DLL-based frequency synthesizer with a fully integrated loop capacitor employs an adaptive current-adjusting loop to generate a low-jitter clock. The nonidealities in the general impedance converter (GIC) which is used as the loop capacitor are thoroughly discussed. Additionally, the discrete-time model for the clock generator with adaptive current tuning is presented and the analysis of the loop stability is provided. The frequency synthesizer occupies an active area of 0.09 mm² in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply. The measured rms jitter is 3.5 ps for a 229.5-MHz output clock.     

A Ku-Band Frequency Synthesizer in 0.18-μm CMOS Technology

This letter presents a fully integrated frequency synthesizer implemented in a 0.18-mum foundry CMOS process. By employing a modified differential Colpitts voltage controlled oscillator to improve the tuning range and the phase noise, the integer-N frequency synthesizer demonstrates an output frequency from 14.8 to 16.9GHz, allowing wideband operations at Ku-band. Operated at an output frequency of 15GHz, the proposed synthesizer exhibits a reference sideband power of -50dBc and a phase noise of -104.5dBc/Hz at 1-MHz offset. The fabricated circuit consumes a dc power of 70mW from a 2-V supply voltage     

A technique to improve the linearization of frequency–voltage characteristic of LC-VCO

This paper presents a very low-power linearization technique to improve the linearity of frequency-voltage characteristic of LC-VCO (voltage controlled oscillator) using MOS varactor. This reduces the VCO gain (K _VCO) variation and its required value over the tuning voltage range. Low K _VCO improves noise and reference spur performances at the output of phase lock loop/frequency synthesizer (FS). Low K _VCO variation reduces FS loop stability problem. Using this VCO circuit, a fully on-chip integer-N frequency synthesizer has been fabricated in 0.18 μm epi-digital CMOS technology for 2.45 GHz ZigBee application. The measured VCO phase noise is ?115.76 and ?125.23 dBc/Hz at 1 and 3 MHz offset frequencies, respectively from 2.445 GHz carrier and the reference spur of the frequency synthesizer is ?68.62 dBc. The used supply voltage is 1.5 V.     

A millimeter wave frequency synthesizer covering the 40–60 GHz waveguide band

This paper describes a millimeter wave frequency synthesizer based on a single broadband backward wave oscillator tube which is capable of covering the entire 40–60 GHz waveguide band with useful power output, low phase noise, and rapid frequency switching. The synthesizer is controlled by an internal microcomputer which sets the reference oscillator frequency through a General Purpose Interface Bus (GPIB) and generates synthesizer coarse tuning corrections through a programmable digital-to-analog converter. The phase/frequency control system uses a frequency discriminator for capture of the source from large frequency errors and a complementary phase lock for precise phase and frequency control.     

GHz band frequency hopping PLL-based frequency synthesizers

In this paper we describe a full-integrated circuit containing all building blocks of a completed PLL-based synthesizer except for low pass filter（LPF）. The frequency synthesizer is designed for a frequency hopping （FH） transceiver operating up to 1.5 GHz as a local oscillator. The architecture of Voltage Controlled Oscillator （VCO） is optimized to get better performance, and a phase noise of -111.85-dBc/Hz @ 1 MHz and a tuning range of 250 MHz are gained at a centre frequency of 1.35 GHz. A novel Dual-Modulus Prescaler（DMP） is designed to achieve a very low jitter and a lower power. The settling time of PLL is 80 μs while the reference frequency is 400 KHz. This monolithic frequency synthesizer is to integrate all main building blocks of PLL except for the low pass filter, with a maximum VCO output frequency of 1.5 GHz, and is fabricated with a 0.18 μm mixed signal CMOS process. Low power dissipation, low phase noise, large tuning range and fast settling time are gained in this design.     

适用于超宽带系统的低功耗CMOS频率合成器研究

针对脉冲无线电超宽频(IR-UWB)接收系统,提出了一种低功耗频率合成器设计。合成器的设计以一个整数N分频II型四阶锁相环结构为基础,包括一个调谐范围为31%的7位压控振荡器,一组基于单相时钟逻辑的高速分频器。分频器能够合成八个由IEEE标准802.15.4a定义的频率。该集成频率合成器运用65 nm CMOS技术制造而成,面积为0.33 mm2,工作频率范围为7.5–10.6 GHz。测试结果显示,在1.2 V供电下,该合成器的3-dB闭环带宽为100 kHz,稳定时间为15 。测量相位噪声低于-103 dBc/Hz@1MHz,抵消频率为1 MHz。杂散信号功率低于低于-58 dBc。相比其他先进的合成器,提出合成器的工作电流为5.13 mA,功耗仅为6.23mW。     

Rapid, Precise, and Stable Control of Optical Frequency for SG-DBR LD Using Quartz Etalon

This paper presents rapid, precise, and stable control of optical frequency for sampled-grating distributed Bragg reflector (SG-DBR) laser diode (LD) using a Z-cut quartz etalon supported at the middle point. The optical frequency of SG-DBR LD was controlled by the mode-hop-free three-electrode control method. As a result, stable mode operation and wide continuous tuning range without mode hopping have been realized. A 0.2-ms optical frequency tuning speed with a 4.35-THz tuning range and a 130-MHz control error of the optical frequency was demonstrated. A 1.1-MHz Allan deviation was reached at an integration time of 12 times 10³ s.     

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

A 0.8-V 4.9-mW 1.2-GHz CMOS Fractional-N Frequency Synthesizer for UHF RFID Readers

A fully integrated CMOS frequency synthesizer for UHF RFID reader is implemented in a 0.18-$mu$m CMOS technology. Due to the large self-interference and the backscatter scheme of the passive tags, reader synthesizer's phase noise requirement is stringent to minimize the sensitivity degradation of the reader RX. The modified transformer feedback voltage-controlled oscillator (VCO) exhibits enhanced tank impedance and even harmonic noise filtering to achieve low phase noise. A third-order 2-bit single-loop $Sigma Delta$ modulator is optimized for the proposed synthesizer in terms of phase noise and power. The synthesizer provides a frequency resolution of 25-kHz with a tuning range from 1.03 GHz to 1.4 GHz . Phase noise of ${-}$70 dBc/Hz inband, ${-}$104 dBc/Hz at 200-kHz offset and ${-}$ 121 dBc/Hz at 1-MHz offset with a reference spur of ${-}$84 dBc are measured at a center frequency of 1.17 GHz and a loop bandwidth of 35 kHz. Power dissipation is 4.92 mW from a 0.8 V supply.      

A 1-V 9.7-mW CMOS Frequency Synthesizer for IEEE 802.11a Transceivers

A 1-V CMOS frequency synthesizer is proposed for wireless local area network 802.11a transceivers using a novel transformer-feedback voltage-controlled oscillator (VCO) for low voltage and a stacked frequency divider for low power. Implemented in a 0.18-mum CMOS process and operated at 1-V supply, the VCO measures a phase noise of -140.5 dBc at an offset of 20 MHz with a center frequency of 4.26 GHz and a power consumption of 5.17 mW. Its tuning range is as wide as 920 MHz (23%). By integrating the VCO into a frequency synthesizer, a phase noise of -140.1 dBc/Hz at an offset of 20 MHz is measured at a center frequency of 4.26 GHz. Its output frequency can be changed from 4.112 to 4.352 GHz by switching the 3-bit modulus of the programmable divider. The synthesizer consumes only 9.7 mW and occupies a chip area of 1.28 mm².     

A spur-reduction technique for a 5-GHz frequency synthesizer

A spur-reduction technique is presented to achieve low reference spurs for a 5-GHz frequency synthesizer. A dual-path control scheme incorporated with a pair of the proposed smoothed varactors reduces the gain of voltage-controlled oscillator to less than 15 MHz/V, attenuates the spurious tones, and shortens the simulated settling time by 56%. In, addition, a digital frequency-calibration circuit is used to enlarge the tuning range to overcome process variations. A 5-GHz frequency synthesizer has been fabricated for verification in a 0.18-/spl mu/m CMOS process. It exhibits phase noise of -79 and -113 dBc/Hz at 10-kHz and 1-MHz offset, respectively. The reference spur level of -74 dBc is achieved by using a second-order loop filter. The overall tuning range is 16.3% and power consumption is 36 mW from a 1.8-V supply. The total switching time including digital frequency calibration takes no more than 110 /spl mu/s.     

Broadband-Frequency-Tunable Sub-Terahertz Wave Generation Using an Optical Comb, AWGs, Optical Switches, and a Uni-Traveling Carrier Photodiode for Spectroscopic Applications

We present a monochromatic sub-terahertz signal generation technique using an optical comb signal, arrayed waveguide gratings (AWGs), and a uni-traveling carrier photodiode (UTC-PD) for spectroscopic applications. This scheme offers random or continuous frequency tuning in the range between 100 GHz and up to 1 THz. In addition, since a RF synthesizer is employed as a reference signal source of the photonic frequency multiplier, frequency locking with external instruments and reliable operation are offered. Highly coherent optical comb signal for the photonic frequency multiplication provides a narrow linewidth and very low phase noise in the generated sub-terahertz signal. For 125 GHz, the phase noise is approximately $-92$ dBc/Hz at the offset frequency of 10 kHz. This is larger than that of the 25-GHz RF source by about 13 dB and agrees well with the theory regarding phase noise multiplications due to frequency multiplication. For generating monochromatic signals, unwanted spurious signals are suppressed in the optical domain over a wide range with two AWGs, and the suppression ratio is expected to be better than 46 dBc. Utilizing the implemented sub-terahertz signal generator with a J-band UTC-PD module, absorption lines of N$_{2}$O were measured in the frequency range between 240 and 360 GHz and compared with theoretical calculations.      

使用三位三阶Δ∑调制器的集成1GHz小数频率合成器

本文实现了一个采用三位三阶Δ∑调制器的高频谱纯度集成小数频率合成器.该频率合成器采用了模拟调谐和数字调谐组合技术来提高相位噪声性能,优化的电源组合可以避免各个模块之间的相互干扰,并且提高鉴频鉴相器的线性度和提高振荡器的调谐范围.通过采用尾电流源滤波技术和减小振荡器的调谐系数,在片压控振荡器具有很低的相位噪声,而通过采用开关电容阵列,该压控振荡器达到了大约100MHz的调谐范围,该开关电容阵列由在片数字调谐系统进行控制.该频率合成器已经采用0.18μm CMOS工艺实现,仿真结果表明,该频率频率合成器的环路带宽约为14kHz,最大带内相位噪声约为-106dBc/Hz;在偏离载波频率100kHz处的相位噪声小于-120dBc/Hz,具有很高的频谱纯度.该频率合成器还具有很快的反应速度,其锁定时间约为160μs.     

A /spl Sigma/-/spl Delta/ fractional-N frequency synthesizer using a wide-band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications

A fractional-N frequency synthesizer (FNFS) in a 0.5-/spl mu/m SiGe BiCMOS technology is implemented. In order to operate in a wide-band frequency range, a switched-capacitors bank LC tank voltage-controlled oscillator (VCO) and an adaptive frequency calibration (AFC) technique are used. The measured VCO tuning range is as wide as 600 MHz (40%) from 1.15 to 1.75 GHz with a tuning sensitivity from 5.2 to 17.5 MHz/V. A 3-bit fourth-order /spl Sigma/-/spl Delta/ modulator is used to reduce out-of-band phase noise and to meet a frequency resolution of less than 3 Hz as well as agile switching time. The experimental results show -80 dBc/Hz in-band phase noise within the loop bandwidth of 25 kHz and -129 dBc/Hz out-of-band phase noise at 400-kHz offset frequency. The fractional spurious is less than -70 dBc/Hz at 300-kHz offset frequency and the reference spur is -75 dBc/Hz. The lock time is less than 150 /spl mu/s. The proposed synthesizer consumes 19.5 mA from a single 2.8-V supply voltage and meets the requirements of GSM/GPRS/WCDMA applications.     

2.06GHz～3.43GHz自校准频率综合器设计

提出了一种自校准频率综合器,通过采用开关电容阵列使该设计具有较低的相位噪声和较宽的调谐范围.自校准 控制回路的引入,使该综合器能根据输入参考频率,温度,分频比等参数自动调整开关阵列中开关的开启和关断,达到快速锁 定的目的.采用SMIC 0.18 μm CMOS工艺进行仿真,结果显示,频率综合器输出频率范围从2.06 G...     

一种用于双波段GPS接收机的低功耗宽带CMOS频率合成器

提出了一种用于双波段GPS接收机的宽带CMOS频率合成器.该GPS接收机芯片已经在标准O.18μm射频CMOS工艺线上流片成功,并通过整体功能测试.其中压控振荡器可调振荡频率的覆盖范围设计为2～3.6GHz,覆盖了L1,L2波段的两倍频的频率点.并留有足够的裕量以确保在工艺角和温度变化较大时能覆盖所需频率.芯片测试结果显示,该频率综合器在L1波段正常工作时的功耗仅为5.6mW,此时的带内相位噪声小于-82dBc/Hz,带外相位噪声在距离3.142G载波1M频偏处约为-112dBc/Hz,这些指标很好地满足了GPS接收芯片的性能要求.