Digitally programmable switched-current FIR filter for low-voltageapplications

In this paper, we describe a switched-current (SI) finite-impulse response (FIR) filter, suitable for equalizer architectures. The basic cell of the FIR filter is a SI sample-hold (S/H) circuit, appropriate for low-voltage operation. The programmability of the FIR filter structure is achieved via MOSFET-only current dividers. The FIR filter has been designed and implemented using a 0.8 μm CMOS process and operates at a power-supply voltage of 2 V     

A low-power 170-MHz discrete-time analog FIR filter

A 170-MHz analog finite impulse response (FIR) filter operating from a single 3.3-V supply is described. The design has been fabricated in the HP 1.2-μm CMOS process and has an area of 2.35 mm by 1.97 mm including bonding pads. This 9-tap filter dissipates 70 mW when operating at 170 MHz. The multipliers are implemented using multiplying digital-to-analog converters (MDAC's) with 6-b resolution     

A programmable FIR digital filter using CSD coefficients

An area-efficient programmable FIR digital filter using canonic signed-digit (CSD) coefficients was implemented that uses a switchable unit-delay to allocate the desired number of nonzero CSD coefficient digits to each filter tap. The prototype chip can allocate up to 16 pairs of nonzero CSD coefficient digits for a linear-phase filter, thus realizing filters with 32 linear-phase taps operating at 180 MHz with two nonzero CSD digits per filter tap. Additional nonzero CSD digits can be allocated to filter taps at the penalty of a reduced filter length and a reduced data-rate. The chip was implemented with 16-bit I/O in a die size of 5.9 mm by 3.4 mm using 1.0-μm CMOS technology     

A programmable transversal filter for voice-frequency applications

A fully integrated, programmable transversal filter optimized for low-noise, low-power, voice-frequency applications is described. The filter, fabricated with a standard double-poly NMOS process, achieves convolution of an analog input signal with digital tap weightings using a structure with sample-and-hold gates for analog storage and a multiplexed MDAC for multiplication. The design of the filter eliminates fixed pattern noise usually associated with such structures and enables a dynamic range in excess of 70 dB (LPF, f/SUB o//f/SUB s/=0.08) to be achieved at an 8 kHz sampling rate with a power dissipation of less than 80 mW. This area efficient device forms the basis for a range of possible voice-band signal processing functions.     

Vertically integrated SOI circuits for low-power and high-performance applications

Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.     

High-performance FIR filter design based on sharing multiplication

Finite impulse response (FIR) filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR filter based on computation sharing multiplier can be reduced to 41% of the FIR filter based on the Wallace tree multiplier for the same frequency of operation.     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

A low-power 5-70-MHz seventh-order log-domain filter with programmable boost, group delay, and gain for hard disk drive applications

A seventh-order 0.05/spl deg/ equiripple linear-phase continuous-time filter employing log-domain-based instantaneous companding was designed and integrated in a mature bipolar process. The amount of boost (up to 13 dB) and group-delay adjustment (/spl plusmn/30%) are digitally programmable. The dc gain is controllable up to 10 dB, and the -3-dB frequency (f/sub c/) is tunable from 5 to 70 MHz. The output swing for 1% total harmonic distortion is higher than 100 mV/sub pp/, with a 1.5-V supply. The filter consumes very low power (5-13 mW for f/sub c/=70 MHz) compared to conventional implementations (e.g., 120 mW for f/sub c/=100MHz ).     

基于MAC单元的低功耗低延时FIR滤波器的设计与分析

乘法器在数字信号处理系统中承担了很重要的作用,而乘法器消耗相当大的功耗,因此有必要进行乘法器的低功耗研究。介绍一种基于乘法累加(MAC)单元的FIR滤波器的设计,其中乘法器利用基4华莱士树乘法器,加法器利用超前进位加法器,在优化整合之后,得到低延时低功耗FIR滤波器。实验证明,该文设计的FIR滤波器具有很小的延时与很低的动态功耗。     

Flexibly tunable microwave photonic FIR filter incorporating wavelength spacing programmable, arrayed micro-mirror based optical filter

A novel tunable microwave photonic FIR filter incorporating a wavelength spacing tunable multiwavelength filter based on a programmable arrayed micro-mirror device (AMMD) is demonstrated. Owing to the unique characteristic of the AMMD, that an arbitrary optical filter shape can be produced by defining a desired spatial pattern on an array of /spl sim/800 000 micro-mirrors, a wavelength spacing tunable multiwavelength optical filtering pattern is readily obtainable. By controlling the optical filter wavelength spacing, flexible resonance RF frequency tuning is achieved over a range of 2.3 GHz.     

A low-power transponder IC for high-performance identificationsystems

A novel CMOS integrated circuit for a batteryless transponder system is presented. Batteryless transponders require contactless transmission of both the information and power between a mobile data carrier and a stationary or handheld reader unit. The operating principle of this system gives a superior performance in reading distance due to separation of the powering and data transmission phases-compared to systems with continuous powering and damping modulation. This paper describes the function of the transponder IC and the circuit design techniques used for the various building blocks     

Circuit techniques for CMOS low-power high-performance multipliers

In this paper we present circuit techniques for CMOS low-power high-performance multiplier design. Novel full adder circuits were simulated and fabricated using 0.8-μm CMOS (in BiCMOS) technology. The complementary pass-transistor logic-transmission gate (CPL-TG) full adder implementation provided an energy savings of 50% compared to the conventional CMOS full adder. CPL implementation of the Booth encoder provided 30% power savings at 15% speed improvement compared to the static CMOS implementation. Although the circuits were optimized for (16×16)-b multiplier using the Booth algorithm, a (6×6)-b implementation was used as a test vehicle in order to reduce simulation time. For the (6×6)-b case, implementation based on CPL-TG resulted in 18% power savings and 30% speed improvement over conventional CMOS     

Algorithm-based low-power and high-performance multimedia signalprocessing

Low power and high performance are the two most important criteria for many signal-processing system designs, particularly in real-time multimedia applications. There have been many approaches to achieve these two design goals at many different implementation levels ranging from very-large-scale-integration fabrication technology to system design. We review the works that have been done at various levels and focus on the algorithm-based approaches for low-power and high-performance design of signal processing systems. We present the concept of multirate computing that originates from filterbank design, then show how to employ it along with the other algorithmic methods to develop low-power and high-performance signal processing systems. The proposed multirate design methodology is systematic and applicable to many problems. We demonstrate that multirate computing is a powerful tool at the algorithmic level that enables designers to achieve either significant power reduction or high throughput depending on their choice. Design examples on basic multimedia processing blocks such as filtering, source coding, and channel coding are given. A digital signal-processing engine that is an adaptive reconfigurable architecture is also derived from the common features of our approach. Such an architecture forms a new generation of high-performance embedded signal processor based on the adaptive computing model. The goal of this paper is to demonstrate the flexibility and effectiveness of algorithm-based approaches and to show that the multirate approach is an effective and systematic design methodology to achieve low-power and high throughput signal processing at the algorithmic and architectural level     

A high-performance low-power CMOS AGC for GPS application

In this paper, a wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of variable gain amplifier (VGA), comparator and charge pump, and the dB-linear gain is controlled by charge pump. The AGC was implemented in a 0.18um CMOS technology. The dynamic range of the VGA is more than 55dB, the bandwidth is 30MHz and the gain error lower than ±1.5dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8V power supply. The AGC power consumption is less than 5mW and area of the AGC is 700*450um2.     

为低功耗无线应用选择天线

天线是RF系统中的一个重要组件，并且对性能有着重大的影响。高性能、小尺寸以及低成本是许多RF应用最常见的要求。为了满足这些要求，实施一个适当的天线并概括描述其性能特点是非常重要的。本文描述了典型的天线类型并阐述了选择天线时应该考试的重要参数。     

A high-performance low-power CMOS AGC for GPS application

A wide tuning range, low power CMOS automatic gain control (AGC) with a simple architecture is proposed. The proposed AGC is composed of a variable gain amplifier (VGA), a comparator and a charge pump, and the dB-linear gain is controlled by the charge pump. The AGC was implemented in a 0.18 μm CMOS technology. The dynamic range of the VGA is more than 55 dB, the bandwidth is 30 MHz, and the gain error is lower than ±1.5 dB over the full temperature and gain ranges. It is designed for GPS application and is fed from a single 1.8 V power supply.The AGC power consumption is less than 5 mW, and the area of the AGC is 700 × 450 μm~2.     

CMOS digitally programmable filter for multi-standard wirelessreceivers

The technique exhibits the wide frequency range of the transconductance amplifier filters while offering improved linearity. It utilises digitally controlled current followers to provide precise frequency characteristics that can be tuned over a wide range. A digitally tuned lowpass filter is designed for implementing the channel-select filter in the baseband chain of a multi-standard CMOS wireless receiver. Simulation and experimental results obtained from a 1.2 μm chip show a programmable frequency response covering the IS-54, GSM, IS-95 and WCDMA wireless standards