Surface micromachined solenoid on-Si and on-glass inductors for RFapplications

RF performance of surface micromachined solenoid on-chip inductors fabricated on a standard silicon substrate (10 Ω·cm) has been investigated and the results are compared with the same inductors on glass. The solenoid inductor on Si with a 15-μm thick insulating layer achieves peak quality (Q-) factor of 16.7 at 2.4 GHz with inductance of 2.67 nH. This peak Q-factor is about two-thirds of that of the same inductor fabricated on glass. The highest performance has been obtained from the narrowest-pitched on-glass inductor, which shows inductance of 2.3 nH, peak Q-factor of 25.1 at 8.4 GHz, and spatial inductance density of 30 nH/mm². Both on-Si and on-glass inductors have been modeled by lumped circuits, and the geometrical dependence of the inductance and Q-factor have been investigated as well     

Self-passivated copper gates for amorphous silicon thin-filmtransistors

A solution to the amorphous silicon transistor gate metallization problem in active matrix liquid crystal displays (AMLCD's) is demonstrated, in the form of a self-passivated copper (Cu) process. Cu is passivated by a self-aligned chromium (Cr) oxide encapsulation formed by surface segregation of Cr in dilute Cu-10-30 at.%Cr alloys at 400°C, solving the problems of chemical reactivity during the plasma deposition, diffusion, poor adhesion to the substrate, and oxidation. The performance of self-passivated Cu bottom-gate thin-film transistors (TFT's) and their stability during thermal bias stress testing is comparable to that of Cr-gate reference TFT's. The gate line resistivity (including encapsulation) is 4.5 μΩ·cm at present     

Low-loss CPW on low-resistivity Si substrates with a micromachinedpolyimide interface layer for RFIC interconnects

The measured and calculated propagation constant of coplanar waveguide (CPW) on low-resistivity silicon (1 Ω·cm) with a micromachined polyimide interface layer is presented in this paper. With this new structure, the attenuation (decibels per centimeter) of narrow CPW lines on low-resistivity silicon is comparable to the attenuation of narrow CPW lines on high-resistivity silicon. To achieve these results, a 20-μm-thick polyimide interface layer is used between the CPW and the Si substrate with the polyimide etched from the CPW slots. Only a single thin-film metal layer is used in this paper, but the technology supports multiple thick metal layers that will further lower the attenuation. These new micromachined CPW lines have a measured effective permittivity of 1.3. Design rules are presented from measured characteristics and finite-element method analysis to estimate the required polyimide thickness for a given CPW geometry     

Effects of epitaxial lift-off on the DC, RF, and thermal propertiesof MESFET's on various host materials

In this paper, we present an in-depth investigation on the effects of epitaxial lift-off (ELO) on GaAs MESFET's. DC and microwave characteristics as well as thermal effects are considered. Devices were fabricated on a GaAs foundry process and transplanted by ELO. ELO is a technology by which epitaxially grown layers are lifted off from their growth substrate and are subsequently re-attached to a new host substrate. Host materials considered are InP, quartz and silicon with resistivities ranging from 11 mΩcm to 50 Ωcm     

In situ semiconductor materials characterization by emissionFourier transform infrared spectroscopy

The results of a novel emission Fourier transform infrared (E/FT-IR) spectrometer for in-situ characterization of semiconductor materials is presented. For the experiments, the wafers were heated and the infrared emission profiles from the substrates were collected by a standard FT-IR spectrometer. Differences in the emission spectra from different substrates are explained through correlation to the optical properties of the corresponding substrates. The in-situ infrared emission spectrum of a lightly doped (10-20 Ω·cm) silicon wafer at 200°C is very similar to its ex-situ transmission spectrum at room temperature, although the spectrum is inverted. This similarity makes possible the analysis of E/FT-IR spectra by using existing spectral libraries. Finally, it is shown that the E/FT-IR technique can be used for noncontact and noninvasive real-time identification and possibly quantification of impurities during silicon oxidation and for real-time epi-film thickness monitoring during silicon epitaxy     

Threshold voltage uniformity and characterization of microwaveperformance for GaAs/AlGaAs high electron-mobility transistors grown onSi substrates

We report on DC and microwave characteristics for high electron-mobility transistors (HEMT's) grown on Si substrates by metal-organic chemical vapor deposition (MOCVD). Threshold voltage (V _th) distribution in a 3-in wafer shows standard deviation of V_th (σV_th) of 36 mV with V_th of -2.41 V for depletion mode HEMT's/Si and σV_th of 31 mV with V_th of 0.01 V for enhancement mode, respectively. The evaluation of V_th in a 1.95×1.9 mm² area shows high uniformity for as-grown HEMT's/Si with σV_th of 9 mV for V_th of -0.10 V, which is comparable to that for HEMT's/GaAs. Comparing the V_th distribution pattern in the area with that for annealed HEMT's/Si, it is indicated that the high uniformity of V_th is obtained irrelevant of a number of the dislocations existing in the GaAs/Si. From microwave characteristic evaluation for HEMT's with a middle-(10~50 Ω·cm) and a high-(2000~6000 Ω·cm) resistivity Si substrate using a new equivalent circuit model, it is demonstrated that HEMT's/Si have the disadvantage for parasitic capacitances and resistances originated not from the substrate resistivity but from a conductive layer at the Si-GaAs interface. The parasitic parameters, especially the capacitances, can be overcome by the reduction of electrode areas for bonding pads and by the insertion of a dielectric layer under the electrode, which bring high cut-off frequency (f_T) and maximum frequency of operation (f_max) of 24 GHz for a gate length of 0.8 (μm). These results indicate that HEMT's/Si are sufficiently applicable for IC's and discrete devices and have a potential to be substituted for HEMT's/GaAs     

Tantalum nitride metal gate FD-SOI CMOS FETs using low resistivityself-grown bcc-tantalum layer

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology using low-resistivity (~15 μΩcm), bcc (body-centered-cubic)-phase tantalum metal layer has been developed, featuring low-temperature processing below 550°C except for gate oxide formation. It was found for the first time that TaNx works not only as a buffer layer which prevents tantalum metal film and gate oxide film from reacting with each other, but also as a seed layer which helps self-growth of bcc-phase tantalum films by hetero-epitaxy. Furthermore, we have demonstrated that the work function of TaNx gate is close to midgap of silicon, hence similar to titanium nitride (TiNx) gate. We have also demonstrated that MOS capacitors on bulk and fully-depleted silicon-on-insulator (FD-SOI) CMOS with TaNx/bcc-Ta/TaNx stacked metal gate structure have excellent electrical characteristics and that the ring-oscillator fabricated using the stacked metal gate CMOS can be operated successfully with 3.8 nm-thickness gate oxide     

Video CMOS power buffer with extended linearity

A CMOS power buffer suitable for video applications is discussed. The use of a high-speed push-pull output stage and a highly linear high-speed driver allows good linearity to be maintained even with very high input frequencies. Indeed, total harmonic distortions (THDs) as good as -66 and -58 dB are achieved at 0.5 and 1 MHz, respectively, with a load resistance of 75 Ω. The integrated prototype, realized using a 1.2-μm CMOS process, occupies a silicon area of 280 mils²     

Low-resistance self-aligned Ti-silicide technology for sub-quartermicron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-μm CMOS devices with low-resistance and uniform TiSi₂ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi₂ films were achieved on all narrow, long n⁺ and p⁺ poly-Si and diffusion layers of 0.15-μm CMOS devices. TiSi₂ films with a sheet resistance of 5 to 7 Ω/sq were stably and uniformly formed on 0.15-μm-wide n⁺ and p⁺ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi₂ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-μm NMOSFET's and PMOSFET's with self-aligned TiSi₂ films     

High frequency electrical circuits on a planar lightwave circuitplatform

We investigated the propagation losses and the characteristic impedances Z_L of coplanar waveguides (CPWs) and microstrip lines (MSLs) on a planar lightwave circuit (PLC)-platform formed on a silica/silicon substrate. The loss of the CPWs was 2.7 dB/cm at 10 GHz on the PLC-platform with 30 μm thick silica layer. Thus, a cm-order circuit of this CPW is difficult to fabricate in the 10 Gb/s module. This is because the silicon substrate has a large loss tangent (tan δ). On the other hand, the loss of the MSLs, where a ground plane shielded the high loss silicon substrate, could be improved to 0.9 dB/cm at 10 GHz with 30 μm thick polyimide. These lower loss MSLs on a PLC-platform can be applied to module operation at 10 Gb/s. Furthermore they have the advantage that they are suitable for application to array device circuits or circuits in a module where several devices are integrated because unlike CPWs the ground planes are not divided by signal lines or DC bias lines. The structure of CPWs and MSLs on a PLC-platform with a Z_L of 50 Ω was also studied in detail     

Ultra-High-Voltage Charge Pump Circuit in Low-Voltage Bulk CMOS Processes With Polysilicon Diodes

An on-chip ultra-high-voltage charge pump circuit realized with the polysilicon diodes in the low-voltage bulk CMOS process is proposed in this work. Because the polysilicon diodes are fully isolated from the silicon substrate, the output voltage of the charge pump circuit is not limited by the junction breakdown voltage of MOSFETs. The polysilicon diodes can be implemented in the standard CMOS processes without extra process steps. The proposed ultra-high-voltage charge pump circuit has been fabricated in a 0.25-mum 2.5-V standard CMOS process. The output voltage of the four-stage charge pump circuit with 2.5-V power-supply voltage (VDD=2.5 V) can be pumped up to 28.08 V, which is much higher than the n-well/p-substrate breakdown voltage (~18.9 V) in a 0.25-mum 2.5-V bulk CMOS process     

N掺杂MgZnO薄膜的p型导电稳定性研究

利用磁控溅射技术,以Mg0.06Zn0.94O为陶瓷靶材,制备了N掺杂p型Mg0.1 3Zn0.8 7O薄膜,薄膜的电阻率为42.45Ω·cm,载流子浓度为3.70×1017/cm3,迁移率为0.40cm2·V-1·s-1。研究了该薄膜p型导电性质在室温空气下随时间的变化情况。实验结果表明,薄膜的电阻率逐渐升高,载流子浓度降低,五个月以后,薄膜转变为n型导电,电阻率为85.58Ω·cm,载流子浓度为4.53×1016/cm3,迁移率为1.61cm2·V-1·s-1。真空热退火后重新转变为p型。结果显示,其p型导电类型的转变与在空气中吸附H2O或H2等形成浅施主有关。     

Design and simulation of integrated inductors on porous silicon in CMOS-compatible processes

We present a comprehensive approach of designing on-chip inductors using a CMOS-compatible technology on a porous silicon substrate. On-chip inductors realized on standard CMOS technology on bulk silicon suffer from mediocre Q-factor values partly because of the loss created by the Si substrate at higher frequencies, in addition to the metal losses. We examine the alternative of using porous Si as a thick layer isolating the Si substrate from the metallization in an otherwise standard CMOS technology. We present theoretical designs produced with full-wave Method-of-Moments simulations, verified by measurements in standard 0.18 μm CMOS technology using Al metallization. When porous Si is introduced in that technology, the same inductor metallization produced Q-factor enhancements of the order of 50%, compared to the same inductor on bulk crystalline silicon. We also produce optimized single-ended inductor designs using Cu on porous Si, in a 0.13 μm-compatible CMOS technology. The resulting Q-factors are enhanced by a factor of 2 and reach values of 30 or more in the 2–3 GHz frequency range. Even higher quality factors can be obtained in this technology when differential designs are used.     

Scaled CMOS technologies with low sheet resistance at 0.06-μmgate lengths

A novel Ti self-aligned silicide (salicide) process using a combination of low dose molybdenum and preamorphization (PAI) implants and a single rapid-thermal-processing (RTP) step is presented, and shown to be the first Ti salicide process to achieve low sheet resistance at ultrashort 0.06-μm gate lengths (mean=5.2 Ω/sq, max=5.7 Ω/sq at 0.07 μm; mean=6.7 Ω/sq, max=8.1 Ω/sq at 0.06 μm, TiSi₂ thickness on S/D=38 nm), in contrast with previous Ti salicide processes which failed below 0.10 μm. The process was successfully implemented into a 1.5 V, 0.12-μm CMOS technology achieving excellent drive currents (723 and 312 μA/μm at I_OFF=1 nA/μm for nMOS and pMOS, respectively)     

Isolation on Si wafers by MeV proton bombardment for RF integratedcircuits

This paper studies issues related with using high energy protons to create local semi-insulating silicon regions on IC wafers for device isolation and realization of high-Q IC inductors. Topics on two approaches, i.e., one using Al as the radiation mask and the other using proton direct-write on wafers were studied. It was shown that Al can effectively mask the proton bombardment of 15 MeV up to the fluence of 10¹⁷ cm^-2. For the unmasking direct write of the proton bombardment, isolation in the silicon wafer can be achieved without damaging active devices if the proton fluence is kept below 1×10¹⁴ cm^-2 with the substrate resistivity level chosen at 140 Ω-cm, or kept at 1×10¹⁵ cm ^-2 with the substrate resistivity level chosen at 15 Ω-cm. Under the above approaches, the 1 h-200°C thermal treatment, which is necessary for device final packaging, still gives enough high resistivity for the semi-insulating regions while recovering somewhat the active device characteristics. For the integrated passive inductor fabricated on the surface of the silicon wafer, the proton radiation improves its Q value     

CMOS substrate coupling modeling and analysis flow for submicron SoC design

CMOS technology substrate crosstalk modeling and a respective analysis flow that captures the affected circuit performance is described. The proposed methodology can be seamlessly integrated into any industrial Analog/RF circuit design flow, and be compatible within standard design environments. It provides accurate estimation of the substrate coupling effects and can estimate adequately all the mask design level isolation performance trends by adapting an advanced substrate modeling concept based on geometrical and process data. Different substrate model accuracy constraints can be invoked depending on the design phase and the simulation time needs. The provided accuracy is validated by correlating simulation results versus on wafer silicon measurements in a 28 nm CMOS set of ring oscillators with carrier frequency of 670 MHz. The mean error of the proposed method is 665 μV while the error sigma is 765 μV.     

An all-implanted CCD/CMOS process

A process has been developed that combines double-polysilicon, surface-type, n-channel charge-coupled devices (CCD's) with silicon-gate CMOS circuits on the same substrate. The process is all ion-implanted (including the getter step), requires only one more masking step than the 18-V CMOS flow, and is fully compatible with the 5-µm-gate-length silicon-gate Planox (localized oxidation of silicon) CMOS process. To demonstrate the design flexibility afforded by the availability of both p- and n-channel transistors, CCD shift registers with CMOS peripheral circuits and a silicon-gate CMOS operational amplifier have been designed and characterized. Low-pass and band-pass filters have also been designed and characterized and found to be comparable with those fabricated through the conventional CCD/NMOS process.     

体硅衬底上的CMOS Fin FET

介绍了一种制作在普通体硅上的 CMOS Fin FET.除了拥有和原来 SOI上 Fin FET类似的 Fin FET结构 ,器件本身在硅衬底中还存在一个凹槽平面 MOSFET,同时该器件结构与传统的 CMOS工艺完全相容 ,并应用了自对准硅化物工艺 .实验中制作了多种应用该结构的 CMOS单管以及 CMOS反相器、环振电路 ,并包括常规的多晶硅和 W/Ti N金属两种栅电极 .分析了实际栅长为 110 nm的硅基 CMOS Fin FET的驱动电流和亚阈值特性 .反相器能正常工作并且在 Vd=3V下 2 0 1级 CMOS环振的最小延迟为 14 6 ps/门 .研究结果表明在未来 VL SI制作中应用该结构的可行性     

Substrate current characterization and optimization of high voltage LDMOS transistors

A 30-V LDMOS integrated with a standard 0.15 μm CMOS process is investigated for its double-hump substrate current (I_b) characteristics. The origin of this abnormal second substrate current hump is explained by Kirk effect. The impact of this second hump of I_b on reliability and device performance is observed. An analytical expression for the second hump of I_b is established by calculating the impact ionization in the drift region according to the electric field distribution obtained by solving Poisson’s equation. The calculated results are compared against the silicon data under various gate/drain bias voltages showing excellent consistency. Additionally, based on the derived expressions for substrate current, the process parameters are optimized achieving much lower substrate current and better reliability performance.     

Overlaid CMOS

A CMOS structure where the source and drain terminals of the MOSFETs are in polysilicon overlaid on top of a thick oxide and the channel is in single-crystal silicon is described, utilising a 970°C SiH4 CVD process which simultaneously deposits epitaxial silicon on the exposed silicon substrate and polysilicon on oxide. The structure allows a more compact CMOS inverter layout and reduced source/drain parasitic capacitances.