Optimizing n-type contact design and chip size for high-performance indium gallium nitride/gallium nitride-based thin-film vertical light-emitting diode

The effects of the n-contact design and chip size on the electrical, optical and thermal characteristics of thin-film vertical light-emitting diodes (VLEDs) were investigated to optimize GaN-based LED performance for solid-state lighting applications. For the small (chip size: 1000×1000 µm²) and large (1450×1450 µm²) VLEDs, the forward bias voltages are decreased from 3.22 to 3.12 V at 350 mA and from 3.44 to 3.16 V at 700  mA, respectively, as the number of n-contact via holes is increased. The small LEDs give maximum output powers of 651.0–675.4 mW at a drive current of 350 mA, while the large VLEDs show the light output powers in the range 1356.7–1380.2 mW, 700 mA, With increasing drive current, the small chips go through more severe degradation in the wall-plug efficiency than the large chips. The small chips give the junction temperatures in the range 51.1–57.2 °C at 350  mA, while the large chips show the junction temperatures of 83.1–93.0 °C at 700  mA, The small LED chips exhibit lower junction temperatures when equipped with more n-contact via holes.     

Investigation of n-ohmic contact of vertical GaN-based light-emitting diodes on graphite substrate with Ag-In bonding

Vertical light-emitting diodes (VLEDs) were successfully transferred from a GaN-based sapphire substrate to a graphite substrate by using low-temperature and cost-effective Ag-In bonding, followed by the removal of the sapphire substrate using a laser lift-off (LLO) technique. One reason for the high thermal stability of the AgIn bonding compounds is that both the bonding metals and Cr/Au n-ohmic contact metal are capable of surviving annealing temperatures in excess of 600 °C. Therefore, the annealing of n-ohmic contact was performed at temperatures of 400 °C and 500 °C for 1 min in ambient air by using the rapid thermal annealing (RTA) process. The performance of the n-ohmic contact metal in VLEDs on a graphite substrate was investigated in this study. As a result, the final fabricated VLEDs (chip size: 1000 µm×1000 µm) demonstrated excellent performance with an average output power of 538.64 mW and a low operating voltage of 3.21 V at 350 mA, which corresponds to an enhancement of 9.3% in the light output power and a reduction of 1.8% in the forward voltage compared to that without any n-ohmic contact treatment. This points to a high level of thermal stability and cost-effective Ag-In bonding, which is promising for application to VLED fabrication.     

A novel low voltage very low power CMOS class AB current output stage with ultra high output current drive capability

In this paper a novel low voltage (LV) very low power (VLP) class AB current output stage (COS) with extremely high linearity and high output impedance is presented. A novel current splitting method is used to minimize the transistors gate–source voltages providing LV operation and ultra high current drive capability. High linearity and very high output impedance are achieved employing a novel resistor based current mirror avoiding conventional cascode structures to be used. The operation of the proposed COS has been verified through HSPICE simulations based on TSMC 0.18 μm CMOS technology parameters. Under supply voltage of ±0.7 V and bias current of 5 μA, it can deliver output currents as high as 14 mA with THD better than ?53 dB and extremely high output impedance of 320 MΩ while consuming only 29 μW. This makes the proposed COS to have ultra large current drive ratio (I_outmax/I_bias or the ratio of peak output current to the bias current of output branch transistors) of 2800. By increasing supply voltage to ±0.9 V, it can deliver extremely large output current of ±24 mA corresponding to 3200 current drive ratio while consuming only 42.9 μW and exhibiting high output impedance of 350 MΩ. Interestingly, the proposed COS is the first yet reported one with such extremely high output current and a THD even less than ?45 dB. Such ultra high current drive capability, high linearity and high output impedance make the proposed COS an outstanding choice for LV, VLP and high drive current mode circuits. The superiority of the proposed COS gets more significance by showing in this work that conventional COS can deliver only ±3.29 mA in equal condition. The proposed COS also exhibits high positive and negative power supply rejection ratio (PSRR+/PSRR?) of 125 dB and 130 dB, respectively. That makes it very suitable for LV, VLP mixed mode applications. The Monte Carlo simulation results are provided, which prove the outstanding robust performance of the proposed block versus process tolerances. Favorably the proposed COS resolves the major limitation of current output stages that so far has prevented designing high drive current mode circuits under low supply voltages. In brief, the deliberate combination of so many effective novel methods presents a wonderful phenomenal COS block to the world of science and engineering.     

GaN-based LEDs with Ar plasma treatment

The authors propose a simple Ar plasma treatment method to selectively damage the area underneath p-pad electrode of GaN-based light-emitting diodes (LEDs). It was found that we could form a highly resistive area so that the injected carriers will be forced to spread out horizontally for the LED. Under 20 mA current injection, it was found that the output powers were 16.0, 17.9 and 17.3 mW while the forward voltages were 3.17, 3.19 and 3.20 V for conventional LED and LED with SiO₂ layer, respectively. Moreover, the LED with Ar plasma treatment is superior to the other LEDs while operating at a higher injection current.     

Electrical and photovoltaic properties of SnSe/Si heterojunction

Thin film of SnSe is deposited on n-Si single crystal to fabricate a p-SnSe/n-Si heterojunction photovoltaic cell. Electrical and photoelectrical properties have been studied by the current density–voltage (J–V) and capacitance–voltage (C–V) measurements at different temperatures. The fabricated cell exhibited rectifying characteristics with a rectification ratio of 131 at ±1 V. At low voltages (V<0.55 V), the dark forward current density is controlled by the multi-step tunneling mechanism. While at a relatively high voltage (V>0.55 V), a space charge-limited-conduction mechanism is observed with trap concentration of 2.3×10²¹ cm⁻³. The C–V measurements showed that the junction is of abrupt nature with built-in voltage of 0.62 V which decreases with temperature by a gradient of 2.83×10⁻³ V/K. The cell also exhibited strong photovoltaic characteristics with an open-circuit voltage of 425 mV, a short-circuit current density of 17.23 mA cm⁻² and a power conversion efficiency of 6.44%. These parameters have been estimated at room temperature and under light illumination provided by a halogen lamp with an input power density of 50 mW cm⁻².     

Non-ohmic effect and pulse aging behavior of V/Mn/Co/Bi/Dy co-doped ZnO semiconducting varistors with sintering processing

We examined the effect of sintering on the microstructure, non-ohmic properties, clamping characteristics, and pulse aging behavior of V/Mn/Co/Bi/Dy codoped ZnO semiconducting varistors. The average grain size increased from 4.7 to 10.4 µm and the densities of the sintered pellets decreased from 5.47 to 5.37 g/cm³ with the increase in sintering temperature. The maximum non-ohmic coefficient (35.3) was obtained at a sintering temperature of 900 °C. Varistors sintered at 900 °C exhibited the best clamp characteristics, a clamp voltage ratio of 1.74–2.54 at a pulse current of 1–25 A. Varistors sintered at 925 °C exhibited the strongest electrical stability; variation rates for the breakdown field measured at 1.0 mA/cm², for the non-ohmic coefficient, and for the leakage current density were 3.4%, 6.6%, and −11.2%, respectively, after application of a pulse current of 100 A.     

Young's modulus of a sintered Cu joint and its influence on thermal stress

Al₂O₃ chips and pure Cu plates were joined by Cu nanoparticles at 250 °C and 350 °C, and the Young's moduli of the sintered Cu were evaluated by nanoindentation tests. The average Young's moduli were 52.7 ± 19.8 GPa and 76.5 ± 29.7 GPa at 250 °C and 350 °C, respectively, indicating that the sintered structures were strengthened at higher temperatures. The calculation results indicated that the joint at 350 °C has a high Young's modulus, but make the stress higher than the chip strength, resulting in breakage of the chip during 65/250 °C power cycling.     

Process optimization of RTA on the characteristics of ITO-coated GaN-based LEDs

We present a detailed study on the optimization of rapid thermal annealing (RTA) on GaN-based light emitting diodes (LEDs). 14 mil × 28 mil GaN-based LED chips are fabricated with indium tin oxide (ITO) layer treated by RTA under various temperatures and times. Through the optical and electrical property analyses of ITO film, it is found that the transmittance and sheet resistance are improved after RTA process due to the better ITO crystallization and bigger grain size, compared with ITO treated by conventional furnace annealing. By employing electroluminescence measurement for the LED chips with RTA treatment, the forward voltage is found to be low as a result of low sheet resistance and contact resistance, and light output power (LOP) is high due to high ITO transmittance and good current density uniformity. Under RTA temperature of 550 °C and time of 3 min, the optimized LOP and forward voltage at 60 mA injection current are 71.2 mW and 2.97 V, respectively. Moreover, the reliability of the chips with RTA is better than those with furnace annealing.     

Common-base multi-finger submicron InGaAs/InP double heterojunction bipolar transistor with fmax of 305 GHz

A layout of a common-base four-finger InGaAs/InP double heterostructure bipolar transistor (DHBT) has been designed and the corresponding DHBT has been fabricated successfully by using planarization technology. The area of each emitter finger was 1 × 15 μm². The breakdown voltage was more than 7 V, the current could be more than 100 mA. The maximum output power can be more than 80 mW derived from the DC characteristics. The maximum oscillation frequency was as high as 305 GHz at I_C = 50 mA and V_CB = 1.5 V. The DHBT is thus promising for the medium power amplifier and voltage controlled oscillator (VCO) applications at W band and higher frequencies.     

An amphiphilic C60 penta-addition derivative as a new U-type molecular rectifier

Unimolecular rectification behavior of a known amphiphilic fullerene derivative, 1,4,11,15,30-pentakis(4-hydroxyphenyl)-2H-1,2,4,11,15,30-hexahydro-[60]fullerene, (4-HOC₆H₄)₅HC₆₀ (referred to here as the fullerene pentapod), is reported. The HOMO and LUMO energy levels of the pentapod were determined by density functional theory calculations (B3LYP/6-31G⁷). It was found that the HOMO of the donor moiety and the LUMO of the acceptor are in the same fullerene cage, quite unlike the fullerene derivatives so far reported as molecular rectifiers. The molecule formed a stable Langmuir-Blodgett film at the air–water interface. Characterization of the film indicated that it constitutes mostly a monolayer of molecules with the hydrophobic C₆₀ moiety pointing upwards. The LB film was transferred over Au(1 1 1) substrate and electrical conductivity of the film was measured by conducting atomic force microscopy. An asymmetric electrical rectification behavior was observed in the voltage range of ±1.0 V to ±2.0 V. Beyond a bias voltage of ±2.0 V, rectification ratio decreased steadily, until at ±2.5 V the current–voltage curve became symmetric. The observed electrical rectification behavior was ascribed to resonant electron tunneling between the Fermi level of the electrode and the molecular orbital levels of the fullerene pentapod. Charge transport in the preferred direction under a suitable applied bias was facilitated due to efficient electronic interactions of the molecular orbitals through a combined effect of homo- and peri-conjugation. This constitutes a new class of donor–acceptor system and a step forward in the field of molecular electronics.     

Measurement of the lowest unoccupied molecular orbital energies of molecular organic semiconductors

The lowest unoccupied molecular orbital (LUMO) energies of a variety of molecular organic semiconductors have been evaluated using inverse photoelectron spectroscopy (IPES) data and are compared with data determined from the optical energy gaps, electrochemical reduction potentials, and density functional theory (DFT) calculations. A linear fit to the electrochemical reduction potential (relative to an internal ferrocene reference) vs. the LUMO energy determined by IPES gives a slope and intercept of ?1.19 ± 0.08 eV/V and ?4.78 ± 0.17 eV, respectively, and 0.92 ± 0.04 and ?0.44 ± 0.11 eV, respectively, based on the DFT calculated LUMO energies. From these fits, we estimate the LUMO and exciton binding energies of a wide range of organic semiconductors.     

P-silicon thin film fabricated by magnetron sputtering and aluminium induced crystallization for Schottky silicon solar cells

Solar cells consist of n-Si wafer and p-Si polycrystalline thin film, which was solely fabricated by magnetron sputtering, and aluminium induced crystallization, are presented in this paper. Firstly, the material and electrical properties of the fabricated p-Si thin films including the crystallization ratio, grain size, morphology, carrier density and mobility were studied by Raman spectroscopy, X-ray diffraction (XRD), scanning electron microscopy and Hall Effect measurement, respectively. The p-Si polycrystalline thin film formed under optimal process conditions had the crystallization ratio of ~ 99% and the grain size of ~ 64.6 nm, determined from the data of Raman spectroscopy and XRD. The hole concentration in the fabricated p-Si polycrystalline thin films was mainly in the order of 10¹⁷ cm⁻³ to 10¹⁹ cm⁻³, and their corresponding mobility values ranged from 15 cm²/V s to 65 cm²/V s. Then solar cells with the device structure of Al electrode/n-Si wafer/p-Si thin film/Al electrode were fabricated, and their electrical properties were measured both under dark and illumination conditions by the semiconductor performance tester and solar simulator. The measured J-V curves under dark condition confirmed the creation of a p-n junction with the ideality factor of 1.55, rectification ratio of 410 at ± 1 V, and the reverse saturation current of 246 nA/cm². The efficiency of 2.19%, with an open circuit voltage of 448 mV and a short circuit current density of 11.2 mA/cm², was achieved under AM1.5G standard illuminations.     

Influence of annealing temperature on field emission from tetrapod-shaped ZnO-whisker films obtained by screen printing

Tetrapod-shaped zinc oxide whisker-film emitters were fabricated on indium tin oxide glass substrates using a screen-printing method. The influence of annealing temperature on field emission of tetrapod-whisker ZnO-based emitters was investigated. X-ray diffraction and scanning electronic microscopy were applied to characterize the structure and the surface morphology of the deposited films. It was found that ZnO-based emitters annealed at 250 °C have the best field emission properties with the lowest turn-on field of 2.6 V/μm at a current density of 1 μA/cm², the lowest threshold field of 5.2 V/μm at a current density of 1 mA/cm² and high field emission enhancement factor of 4129. Moreover, films with homogeneous, fine and dense light spots with low emission current fluctuation of 1.7% were obtained from samples annealed at 250 °C.     

A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.     

Formation of low-resistance and transparent indium tin oxide ohmic contact for high-brightness GaN-based light-emitting diodes using a Sn–Ag interlayer

We report on the formation of low-resistance and highly transparent indium tin oxide (ITO) ohmic contacts to p-GaN using a Sn–Ag alloy interlayer. Although the as-deposited Sn–Ag(6 nm)/ITO(200 nm) contacts show non-ohmic behaviors, the scheme becomes ohmic with specific contact resistance of 4.72×10⁻⁴ Ω cm² and produce transmittance of ∼91% at wavelength of 460 nm when annealed at 530 °C. Blue light-emitting diodes (LEDs) fabricated with the Sn–Ag/ITO contacts give forward-bias voltage of 3.31 V at injection current of 20 mA. LEDs with the Sn–Ag/ITO contacts show the improvement of the output power by 62% (at 20 mA) compared with LEDs with Ni/Au contacts.     

Cobalt phosphide nanowire arrays grown on carbon cloth as novel electrode material for supercapacitors

It is very important to exploit new electrode materials to enhance supercapacitor performances. In this study, the mesoporous cobalt phosphide (CoP) nanowire arrays on carbon cloth have been fabricated by low-temperature phosphidation of hydrothermally obtained Co precursor. The CoP electrode shows a remarkable areal capacitance of 1.89 F/cm² at current densities of 3 mA/cm². Furthermore, the electrode exhibits excellent cycling stability (~3% loss after the repetitive 4000 cycles at 18 mA/cm²) and Coulombic efficiency (~97.6% after 4000 cycles).     

Vertically aligned ZnO nanowires prepared by thermal oxidation of RF magnetron sputtered metallic zinc films

ZnO nanowires have been successfully grown by thermal oxidation of metallic zinc films at 430 °C. Polycrystalline zinc films were deposited on Si (100) substrates by RF magnetron sputtering utilizing discharge power from 70 to 180 W. Experimental results show that 70 W discharge power results in the formation of porous zinc nanoparticles that prevent zinc atom from diffusion and thus does not result in the formation of ZnO nanowires by subsequent thermal oxidation. By increasing discharge power to 120 W the zinc film transforms to Zone II with a columnar structure, while further increase in discharge power to 180 W results in re-crystallization and formation of micron-sized hexagonal structures on the surface. Vertically aligned ZnO nanowires can only be obtained by thermal oxidation of columnar zinc films that exhibit a field emission threshold of 5.3 V/μm (at a current density of 10 μA/cm²) with a field enhancement factor of 1834. A target current density of 0.75 mA/cm² is achieved with a bias field less than 10 V/μm.     

Aging characteristics of ZnO–V2O5-based varistors for surge protection reliability

The effect of sintering temperature on clamping characteristics and pulse aging behavior of V₂O₅/MnO₂/Nb₂O₅ co-doped zinc oxide varistors was systematically investigated at 875–950 °C. Experimental results related to varistor effect showed that the breakdown field decreased dramatically from 6830 to 968 V/cm with the increase in the sintering temperature and the non-ohmic coefficient exhibited a maximum (49.5) at 900 °C in the sintering temperature. Varistors sintered at 900 °C exhibited the best clamp characteristics for the pulse current of 1–100 A, with the clamp voltage ratio of K = 1.86–2.77. Varistors sintered at 875 °C exhibited the strongest stability; variation rates for the breakdown field, for the non-ohmic coefficient, and for the leakage current density were −14.2%, −63.6%, and 59.0%, respectively, after application of a multi-pulse current of 100 A.     

Transimpedance amplifier with a compression stage for wide dynamic range optical applications

A high dynamic input transimpedance amplifier was implemented in 130 nm CMOS technology. The proposed TIA is an inverter with a diode connected NMOS and a gate controlled PMOS loads which is cascode connected with the inverter. The square law compression NMOS increases the input photocurrent up to 10 mA. The TIA has an integrated input referred noise current of 135 nA, 227 MHz bandwidth. The TIA shows a transimpedance gain of 59 dBΩ and a 97 dB dynamic range. The TIA consumes 2.3 mA from 1.5 V voltage supply.     

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1 V and its dynamic range is ±1 V too. The designed circuit is simulated in an industrial 65 nm CMOS process. The linear version is tunable over the wide resistance range of 7 kΩ–37 GΩ.