新型RESURF AlGaN/GaN HEMTs器件耐压分析

本文首先从器件有源区耗尽过程分析表明AlGaN/GaN HEMTs器件具有与传统Si功率器件不同的耗尽过程,针对AlGaN/GaN HEMTs器件特殊的耐压机理,提出了一种降低表面电场,提高击穿电压的新型RESURF AlGaN/GaN HEMTs结构.新结构通过在极化的AlGaN层中引入分区负电荷,辅助耗尽二维电子气,有效降低了引起器件击穿的栅极边缘高电场,并首次在漏极附近引入正电荷使漏端高电场峰降低.利用仿真软件ISE分析验证了AlGaN/GaN HEMTs器件具有的"虚栅"效应,通过电场和击穿特性分析获得,新结构使器件击穿电压从传统结构的257V提高到550V.     

Novel high voltage RESURF AlGaN/GaN HEMT with charged buffer layer

A novel reduced surface field (RESURF) Al GaN /GaN high electron mobility transistor(HEMT)with charged buffer layer is proposed. Its breakdown mechanism and on-state characteristics are investigated.The HEMT features buried Fluorine ions in the GaN buffer layer both under the Drift and the Gate region (FDG). The section of FDG under the drift region (FD) not only reduces the electric field (E-field) peak at the gate edge but also enhances the E-field in the drift region by the assisted depletion, leading to a significant improvement in breakdown voltage (BV). Moreover, the section of FDG under the gate (FG) enhances the back barrier and effectively prevents electron injecting from the source to form leakage current, thus a higher BV is achieved. The BV of the proposed HEMT sharply increases to 750 V from 230 V of conventional AlGaN /GaN HEMT with the same dimensional parameters, and the specific on-resistance (Ron,sp) just increases to1.21 m?·cm~2from 1.01 m?·cm~2.     

Enhancement of Johnson figure of merit in III‐V HEMT combined with discrete field plate and AlGaN blocking layer

The performance of AlGaN/GaN HEMT is enhanced by using discrete field plate (DFP) and AlGaN blocking layer. The AlGaN blocking layer provides an excellent confinement of electrons toward the GaN channel, resulting very low subthreshold drain current of 10^?8 A/mm. It reveals very high off state breakdown voltage (BV) of 342 V for 250 nm gate technology HEMT. The breakdown voltage achieved for the proposed HEMT is 23% higher when compared to the breakdown voltage of conventional field plate HEMT device. In addition, the DFP reduces the gate capacitance (C_G) from 12.04 × 10^?13 to 10.48 × 10^?13 F/mm. Furthermore, the drain current and transconductance (g_m) reported for the proposed HEMT device are 0.82 A/mm and 314 mS/mm, respectively. Besides, the cut‐off frequency (f_T) exhibited for the proposed HEMT is 28 GHz. Moreover, the proposed HEMT records the highest Johnson figure of merit (JFOM) of 9.57 THz‐V for 250 nm gate technology without incorporating T‐gate.     

具有高斯型的倾斜表面漂移区的LDMOS的器件特性研究

本文提出一种具有高斯型的倾斜表面漂移区的LDMOS结构。P阱、沟道、源区、栅极等位于高斯中心的一侧,而漏端位于高斯中心的另一侧并靠近高斯中心,器件既具有倾斜表面漂移区的高耐压性,又具有VDMOS结构的高开态击穿特性和良好的安全工作区域。我们研究了高斯表面的弯曲程度对高斯型倾斜表面漂移区的影响。结果表明,P阱的长时间退火对具有高斯表面的漂移区的掺杂浓度分布有一定影响。具有高斯表面的倾斜漂移区的LDMOS结构在不同弯曲程度下器件耐压性和表面电场分布均匀性不同。高斯弯曲参数P在0.5左右时开态耐压性能最优,并且表面电场分布相对均匀;当弯曲参数P增大时,击穿特性基本饱和或略有下降。     

Improvements on voltage-resistant performance of bipolar static induction transistor (BSIT) with buried gate structure

The breakdown mechanism of power bipolar static induction transistor (BSIT) with buried gate structure is analyzed in depth.A power BSIT sample with high voltage-resistant capability has been designed and fabricated in this paper.The technological methods for improving high voltage performances are represented.The active region of BSIT is surrounded with a deep trench to avoid any probable influences of various defects on device performances.Two field-limiting ring-shape junctions and one channel termination ring-shape junction are arranged around the gate region to reduce the electric field intensity.The gate-source breakdown voltage BV GS of power BSIT has been increased to 110 V from previous value of 50-60 V,and its blocking voltage is increased to 1700 V.The optimal geometrical dimensions for achieving the maximum breakdown voltage BV GS and blocking voltage V block are also represented in the paper.     

An improved empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs

A complete empirical large‐signal model for the GaAs‐ and GaN‐based HEMTs is presented. Three generalized drain current I–V models characterized by the multi‐bias Pulsed I–V measurements are presented along with their dependence on temperature and quiescent bias state. The new I–V equations dedicated for different modeling cases are kept accurate enough to the higher‐order derivatives of drain‐current. Besides, an improved charge‐conservative gate charge Q–V formulation is proposed to extract and model the nonlinear gate capacitances. The composite nonlinear model is shown to accurately predict the S‐parameters, large‐signal power performances as well as the two‐tone intermodulation distortion products for various types of GaAs and GaN HEMTs. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE , 2011.     

New small‐signal extraction method applied to GaN HEMTs on different substrates

In this article, a new extraction technique is proposed to extract the small‐signal parameters of gallium nitride (GaN) high electron mobility transistors (HEMTs) on three different substrates namely, Si, SiC, and Diamond. This extraction technique used a single small‐signal circuit model to efficiently describe the physical and electrical properties of GaN on different substrates. This technique takes into account any asymmetry between the gate‐source and gate‐drain capacitances on the asymmetrical GaN HEMT structure, charge‐trapping effects, passivation layer inclusion, as well as leakage currents associated with the nucleation layer between the GaN buffer layer and the different substrates. The extracted values were then optimized using the grey wolf optimizer. The proposed technique was demonstrated through a close agreement between simulated and measured S‐parameters.     

AlGaN/GaN C-HEMT structures for dynamic stress detection

In our work, we investigated the possibility of dynamic stress detection based on the piezoelectric polarization using AlGaN/GaN circular high electron mobility transistors (C-HEMTs). In our knowledge, stress sensors in that account are introduced for the first time. The sensor structures exhibit good linearity in the piezoelectric response under dynamic stress conditions. The measurements reveal excellent stress detection sensitivity that is independent on the measured frequency range. The sensitivity of the devices can be easily increased by increase of the area of the Schottky gate ring electrode. The further increase of the sensitivity can be tuned by an optimal selection of the DC drain and gate bias.     

A simplification method for capacitance models in AlGaN/GaN high electron mobility transistors under large drain voltage using channel analysis

This article analyzes the bias dependence of gate‐drain capacitance (C_gd) and gate‐source capacitance (C_gs) in the AlGaN/GaN high electron mobility transistors under a high drain‐to‐source voltage (V_ds) from the perspective of channel shape variation, and further simplifies C_gd and C_gs to be gate‐to‐source voltage (V_gs) dependent only at high V_ds. This method can significantly reduce the number of parameters to be fitted in C_gd and C_gs and therefore lower the difficulty of model development. The Angelov capacitance models are chosen for verifying the effectiveness of simplification. Good agreement between simulated and measured small‐signal S‐parameters, large‐signal power sweep, and power contours comprehensively proves the accuracy of this simplification method.     

Growth and characterization of 0.8-μm gate length AlGaN/GaN HEMTs on sapphire substrates

AlGaN/GaN high electron mobility transistor (HEMT) structures were grown on 2 inch sapphire substrates by MOCVD, and 0.8-μm gate length devices were fabricated and measured. It is shown by resistance mapping that the HEMT structures have an average sheet resistance of approximately 380 Θ/sq with a uniformity of more than 96%. The 1-mm gate width devices using the materials yielded a pulsed drain current of 784 mA/mm atV _gs=0.5 V andV _ds=7 V with an extrinsic transconductance of 200 mS/mm. A 20-GHz unity current gain cutoff frequency (f _T) and a 28-GHz maximum oscillation frequency (f _max) were obtained. The device with a 0.6-mm gate width yielded a total output power of 2.0 W/mm (power density of 3.33 W/mm) with 41% power added efficiency (PAE) at 4 GHz.     

Analysis of drain ac stress‐induced hot‐carrier degradation in low‐temperature poly‐Si TFTs

We investigated hot‐carrier degradation in low‐temperature (≤425° C) polycrystalline‐silicon thin‐film transistors (poly‐Si TFTs). When the appropriate stress is applied to the TFTs, a decrease in on‐current and an increase in off‐current are induced by the drain avalanche hot carriers (DAHC). The extent of the degradation is quite large, however, when the ac stress is applied to the drain (drain ac stress). Moreover, the degradation is accelerated by an increase in the frequency of the drain ac stress. We found that the pulse number of the drain ac stress dominated this degradation. It is well known that hot carriers are generated by impact ionization, and the impact ionization rate increases with an increase in the carrier density and the electric field in the channel. When the dc stress is supplied to the drain (drain dc stress), the electric field near the drain is high, while the electron density near the drain is low because of the formation of a pinch‐off region. On the other hand, for the case of drain AC stress, both the electric field and electron density near the drain become high during the transition when the voltage of the stress pulse changes from low to high. The impact ionization rate increases at this point. As this cycle is repeated, it is thought that the degradation of TFTs is accelerated.     

Impact of ZnO gate interfacial layer on piezoelectric response of AlGaN/GaN C-HEMT based ring gate capacitor

We report on a piezoelectric response investigation of AlGaN/GaN circular high electron mobility transistor (C-HEMT) based ring gate capacitor as a new stress sensor device to be potentially applied for dynamic high-pressure sensing. A ring gate capacitor of C-HEMT with an additional ZnO gate interfacial layer was used to measure the changes in the piezoelectric charge induced directly by the variation of piezoelectric polarization of both gate piezoelectric layers (AlGaN, ZnO) for harmonic loading at different excitation frequences. Our experimental results show that about 10 nm thick piezoelectric ZnO layer grown on ring gate/AlGaN interface of C-HEMT can yield almost a 60% increase in the piezoelectric detection sensitivity of the device due to its higher piezoelectric coefficient. A three-dimensional CoventorWare simulation is carried out to confirm the increase in the measured piezoelectric response of ZnO based ring gate capacitor of C-HEMT.     

Micromechanical switches fabricated using nickel surfacemicromachining

Micromechanical switches have been fabricated in electroplated nickel using a four-level surface micromachining process. The simplest devices are configured with three terminals, a source, a drain, and a gate and are 30 μm wide, 1 μm thick, and 65 μm long. A voltage applied between the gate and source closes the switch, connecting the source to the drain. Devices switch more than 10⁹ cycles before failure and exhibit long-lifetime hot switching currents up to 5 mA. The initial contact resistance is less than 50 mΩ. The breakdown (stand-off) voltage between the source and the drain is greater than 100 V and the off-current is less than 20 fA at 100 V     

Ultrathin GaN/AlN/GaN solution-gate field effect transistor with enhanced resolution at low source-gate voltage

The pH response of a GaN/AlN/GaN solution-gate field effect transistor (SGFET), with a GaN/AlN barrier of 7.5 nm thick, is analyzed and compared with standard GaN/AlGaN/GaN SGFETs with total barrier thicknesses of 19 and 23 nm. While all types of SGFETs show a similar surface sensitivity to H⁺ ions, a significant improvement in the transducive sensitivity of the SGFET source-drain current under pH changes is found when decreasing the barrier thickness, due to the increased transconductance of the FET structure. Resolution better than 0.005 pH can be estimated in the case of the ultrathin SGFET. Moreover, the maximum transconductance value shifts to gate-drain voltage close to 0 V, which eventually involves no need of reference electrode in less demanding applications, simplifying the final design of the device and making AlN barrier-based SGFETs highly recommended in the broad field of chemical sensors.     

Novel self‐aligned top‐gate oxide TFT for AMOLED displays

Abstract— A novel highly reliable self‐aligned top‐gate oxide‐semiconductor thin‐film transistor (TFT) formed by using the aluminum (Al) reaction method has been developed. This TFT structure has advantages such as small‐sized TFTs, lower mask count, and small parasitic capacitance. The TFT with a 4‐μm channel length exhibited a field‐effect mobility of 21.6 cm²/V‐sec, a threshold voltage of ?1.2 V, and a subthreshold swing of 0.12 V/decade. Highly reliable TFTs were obtained after 300°C annealing without increasing the sheet resistivity of the source/drain region. A 9.9‐in.‐diagonal qHD AMOLED display was demonstrated with self‐aligned top‐gate oxide‐semiconductor TFTs for a low‐cost and ultra‐high‐definition OLED display. Excellent brightness uniformity could be achieved due to small parasitic capacitance.     

Instability dependent upon bias and temperature stress in amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors

Abstract— The effects of gate‐bias stress, drain‐bias stress, and temperature on the electrical parameters of amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors have been investigated. Results demonstrate that the devices suffer from threshold‐voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature‐assisted charging and discharging phenomenon of preexisting traps at the near‐interface and the a‐IGZO channel region. The experimental results show that applying a drain‐bias stress obviously impacts the instability of a‐IGZO TFTs; however, the instability caused by drain bias is not caused by hot‐electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.     

Neuro‐space mapping modeling approach for trapping and self‐heating effects on GaAs and GaN devices

In recent years, neural networks have been successfully applied for modeling the nonlinear microwave devices as GaAs and GaN MESFETs/HEMTs. Many modeling approaches have been developed for small and large signal applications. In this contribution, a neuro‐space mapping approach is proposed for modeling the trapping and the self‐heating effects on GaAs and GaN devices. The Angelov empirical model is used as the coarse model, which can be adjusted using DC and Pulsed I/V measurements at different static bias points. The proposed approach is tested for the MGF1923 GaAs MESFET and for an AlGaN/GaN HEMT. DC and transient simulation results are compared to DC and Pulsed I/V measurements. Good results are obtained for the DC and dynamics I/V characteristics at different static bias points.     

Electrokinetic micromixing of charged and non-charged samples near nano–microchannel junction

A nano–microchannel flow mixer comprising a polydimethylsiloxane (PDMS) microchannel and a Nafion nanoporous membrane is fabricated. It is shown that when an electric field is applied across the device, an ion enrichment/ion depletion effect occurs near the nano–microchannel junction. The mixing performance of the proposed device is examined for three different samples, namely fluorescein (negatively charged), Rhodamine 6G (positively charged), and Rhodamine B (electroneutral). It is shown that a mixing effect is obtained only for the Rhodamine B solution. Thus, it is inferred that nano–microchannel devices such as that presented in this study and those presented in the literature are unsuitable for biomolecule detection applications since such molecules are generally charged.     

Differential negative resistance effect of output characteristics in deep sub-micrometer wurtzite AlGaN/GaN MODFETs

We obtained the output characteristics in wurtzite Al0.15Ga0.85N/GaN MODFETs with the full band Monte Carlo method. The gate length Lg and the channel length Los in the device are 0.2 μm and 0.4 urn, respectively. In the output characteristics we found a differential negative resistance effect. That is, as VDS is a constant, initially, VDS increases with increasing VDS. When VDS exceeds a certain critical value, IDS decreases with increasing VDS. The analysis for velocity-field characteristics in wurtzite CaN, the distributions of the electric field and the electron velocity in the two dimensional electron gas channel indicates that the differential negative resistance effect of the electron average velocity results in the differential negative resistance effect of the output characteristics. The transient transport also is related to the differential negative resistance effect of the output characteristics. This effect only can be observed in the devices with very short channel.     

Genetic algorithm‐based neural‐network modeling approach applied to AlGaN/GaN devices

An accurate equivalent circuit large‐signal model (ECLSM) for AlGaN‐GaN high electron mobility transistor (HEMT) is presented. The model is derived from a distributed small‐signal model that efficiently describes the physics of the device. A genetic neural‐network‐based model for the gate and drain currents and charges is presented along with its parameters extraction procedure. This model is embedded in the ECLSM, which is then implemented in CAD software and validated by pulsed and continuous large‐signal measurements of on‐wafer 8 × 125‐μm GaN on SiC substrate HEMT. Pulsed IV simulations show that the model can efficiently describe the bias dependency of trapping and self‐heating effects. Single‐ and two‐tone simulation results show that the model can accurately predict the output power and its harmonics and the associated intermodulation distortion (IMD) under different input‐power and bias conditions. © 2012 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2013.