基才层次故障树的地面电源诊断优化方法研究

导弹地面电源系统是一个集成度高、结构复杂的综合系统,采用传统的故障树分析方法,存在故障树复杂,分析量大等问题。针对该地面电源系统的复杂性,结合常规的故障树分析方法和层次化分析方法的优势,提出了层次故障树的分析方法,在构建故障诊断树后,将其应用到该电源系统的故障诊断策略优化中,达到了很好的效果。     

基才层次故障树的地面电源诊断优化方法研究

导弹地面电源系统是一个集成度高、结构复杂的综合系统,采用传统的故障树分析方法,存在故障树复杂,分析量大等问题。针对该地面电源系统的复杂性,结合常规的故障树分析方法和层次化分析方法的优势,提出了层次故障树的分析方法,在构建故障诊断树后,将其应用到该电源系统的故障诊断策略优化中,达到了很好的效果。     

一种基于异常值检测和群体智能优化神经网络的电价混合预测模型

为了提高短期电价预测精度,本文提出了一种将异常值检测、时间序列分析、神经网络以及群体智能算法相结合的混合算法。作为混合算法的具体实现,文中的异常值检测利用了残差比方法和正态分布方法,群体智能优化算法选取了粒子群(PSO)算法和布谷鸟(CS)算法。作为实例研究,本文将混合模型应用用于澳大利亚新南威尔士州短期电价预测中,结果表明,混合预测方法能在一定程度上提高模型的预测精度。     

基于蒙特卡罗仿真与逆向FTF的复杂系统可靠性分析

针对复杂系统可靠性评估问题,提出了一种基于FTA(故障树)仿真与FMECA(故障模式影响及危害性分析)相结合的逆向FTF综合分析方法,该方法通过故障树的蒙特卡罗仿真计算系统中的重要部件和系统薄弱环节,再利用FMECA有针对性的对重要部件进行详尽分析,提高了可靠性分析的效率,增强了评估的客观性。并以某无人机为例进行了计算和分析,结果表明:该方法对复杂系统可靠性设计具有一定的指导作用和实用价值。     

不规则贴片微带天线的MPSTD-FDTD混合算法分析

 针对不规则贴片微带天线的准确建模与快速分析,将多区域时域伪谱(MPSTD)与时域有限差分(FDTD)两种时域算法相结合,提出了MPSTD-FDTD混合算法,以此来充分发挥两种时域算法的优越性.文中首先给出了混合算法的具体实现方法,并简要推导了混合算法中子域分界面上的匹配条件.其次,分析了算法的计算精度和影响计算精度的主要因素.最后,利用该混合算法对一种倾斜矩形贴片微带天线进行了分析,数值仿真验证了算法的有效性和准确性.     

遥感、遥测、遥控

TP73 96031304微波辐射计低温定标负载的研究/吕颖,张祖荫,郭伟(华中理工大学图象识别与人工智能所)刀华中理工大学学报一1996,24(2)一72一73 基于Hardy定标方法在精度上受到的限制,提出了一种新的辐射计低温定标负载结构.并根据分层中电磁波传输的基本理论对这种结构进行分析,得到辐射亮温的计算公式,得出了绝热层对定标负载辐射的贡献必须在定标方程中加以考虑而不能忽略的结论.计算结果与实验结果符合得较好。图2表2参双金)最优解的过程。文中提出的有限光谱混合分析方法是在约束条件下求混合光谱方程的最优解,并提出子决速算法.该方法…     

基于逻辑回归改进的随机行走空谱融合分类

针对只利用光谱信息进行分类没有充分利用高光谱图像的空间信息和光谱信息的融合,文中提出了改进的随机行走算法,将高光谱的空间信息和非空间信息(光谱)充分融合。针对传统的马尔科夫随机场在物体边缘分类上的欠缺,提出了对高光谱图像先进行主成份分析获得第一主成分构造拥有最大均方特性的加权图G=(V,E)。最后将基于加权图和改进的随机行走理论结合进行高光谱图像分类。针对逐像素支持向量机在估计初始概率时没有考虑高光谱图像的空间信息,尝试提出利用逻辑回归分类器LOR与改进的随机行走的算法结合来提升分类精度。对比实验表明文中算法具有更高的分类精度。     

超大规模集成电路中基于OCV的时序收敛方法

当芯片设计进入深亚微米,片上工艺偏差(OCV)造成的时序不确定性,成为超大规模集成电路时序收敛中的关键问题,单纯使用传统时序分析方法,已不能完全达到时序收敛的要求。文中首先介绍了静态时序分析方法,阐述了深亚微米下OCV分析对时序收敛的重要性,并提出对OCV问题建模和分析的方法。最后通过一个具体的设计实例,运用基于OCV的时序分析方法达到时序收敛。     

电源技术

0530 充电与发电及其设备9908927水电站群装机容量分配的多目标模糊优化方法[刊]/李会安//西安理工大学学报.—1998,14(3).—289～293(G)9908928水轮发电机组的事故停机分析与故障诊断专家系统的研究[刊]/杨晓萍//西安理工大学学报.—1998,14(2).—201～205(B)构造了水轮发电机组的故障树,对故障树进行了定性定量分析,得出了逻辑分析与数量分析的结果,并对故障树的简化与等效进行了讨论;按照故障树模型,建立了在线故障数据采集和故障诊断的实时故障诊断专家系统,介绍了专家系统知识库的建立及知识表示方法。参4     

基于混合核函数的快速KPCA人脸识别算法

为提高人脸识别的速率和识别率,文中提出一种基于混合核函数的快速核主成分分析算法用于进行人脸识别,首先构造两种混合核函数,利用均值矢量的方法构建核矩阵,并利用文中提出的核主成分分析算法计算核矩阵的特征向量。分别在ORL和AR人脸数据库中做了相关实验,并且与传统的核主成分分析方法在识别率和算法运行时间上进行了比较,结果表明,文中所提核主成分分析方法具有较高的识别率和更短的运行时间,从而为实时地具有大数据的人脸识别系统提供技术支持。     

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates

This paper presents accurate models for the analysis of fault trees based on stochastic logic. To produce the models, probabilistic analysis of static, dynamic and temporal gates is carried out and the probability models are converted to their equivalent stochastic logic gates. A hardware template is also designed for each stochastic logic gate. In the proposed method, users provide fault rates of basic events and immediately evaluate system reliability. Experimental results show that the proposed method is more accurate than previous methods using the proposed stochastic logic gates for dynamic and temporal fault trees. The formula was validated using the Markov model for exponential failure distribution events. The proposed model is applicable for both exponential and non-exponential distributions.     

Robust tests for parity trees

Linear logic circuits are used extensively in digital computing and signal processing systems. They are constructed as regular arrays (for example as cascade or tree circuits), employing linear gates such as Exclusive OR (EOR) and Exclusive NOR (ENOR) gates. Earlier studies on fault diagnosis in linear logic circuits were based on the classical fault model of line stuck-at faults. Transistor stuck-open (SOP) and stuck-on (SON) faults in linear circuits were studied recently, but the effect of signal transients due to circuit delays and time skews in input changes were not considered in the derivation of test sequences. These latter factors are known to cause invalidation of two pattern tests for stuck-open faults. In this article we consider the problem of generating robust tests for linear logic circuits. These tests are not affected by circuit transients caused by delays. A major finding in this paper is that, if the test invalidation problem is redressed by introducing robust tests, the test length becomes a linear function of the depth of the circuit as opposed to the constant number of tests derived in previous studies, by neglecting circuit transients. A lower bound on minimum number of distinct test patterns needed for a tree of EOR gates of depthd is derived. This number depends on the specific implementation of the gate. Robust test-generation procedures are proposed for both single and multiple fault models and their optimalities are argued. Given that every gate in a parity tree is robustly testable, a test sequence that can test for all faults in the circuit, regardless of the nature of gate implementation, is calleduniversal robust test sequence for a parity tree. Finally we propose an optimal universal robust test sequence.     

PIPBQ Effect Aware SER Analysis for Combinational Logic Circuits

Technology scaling results in the propagation-induced pulse broadening and quenching (PIPBQ) effect become more noticeable. In order to effectively evaluate the soft error rate for combinational logic circuits, a soft error rate analysis approach considering the PIPBQ effect is proposed. As different original pulse propagating through logic gate cells, pulse broadening and quenching are measured by HSPICE. After that, electrical effect look-up tables (EELUTs) for logic gate cells are created to evaluate the PIPBQ effect. Sensitized paths are accurately retrieved by the proposed re-convergence aware sensitized path search algorithm. Further, by propagating pulses on these paths to simulate fault injection, the PIPBQ effect on these paths can be quantified by EELUTs. As a result, the soft error rate of circuits can be effectively computed by the proposed technique. Simulation results verify the soft error rate improvement comparing with the PIPBQ-not-aware method.     

Design and simulation of logic circuits with hybrid architectures of single-electron transistors and conventional MOS devices at room temperature

Single-electron transistors (SETs) provide current conduction characteristics comparable to CMOS technology and research shows that these devices can be used to develop logic circuits. It has been observed while building logic circuits that comprise only of SETs the voltage at the gate input had to be much higher than the power supply for the SET to have acceptable switching characteristics. This limitation in the gate and power supply voltages makes it practically inappropriate to build circuits. In this paper, we propose a hybrid architecture to overcome this limitation by combining conventional MOS devices with SETs. Three different types of hybrid circuits have been proposed and their characteristics have been studied using SPICE-based simulation tool which includes a SET-SPICE model.     

MOSFET-like CNFET based logic gate library for low-power application: a comparative study

The next generation of logic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLSI. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors (CNFETs) technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely: complementary-CMOS (C-CMOS), transmission gate (TG), complementary pass logic (CPL) and Domino logic (DL) styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average power-delay-product (PDP). The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.     

基于改进麻雀搜索算法优化BN的变压器故障诊断研究

针对变压器故障诊断准确率低和稳定性差的问题,文中提出了一种改进麻雀搜索算法优化贝叶斯网络的变压器故障诊断方法。首先,通过计算互信息建立最大支撑树并进行定向处理得到贝叶斯网络初始结构即初始种群。然后,在算法中引入一种新的合作机制和正弦余弦算法,提高算法收敛速度和全局搜索能力,并利用油中溶解气体分析,创建基于改进麻雀搜索算法优化贝叶斯网络的变压器故障诊断模型。最后,为了证明所提方法的优越性,将所提的方法与现有变压器故障诊断方法进行对比。结果表明,文中所提出的方法故障诊断率最高,可以更精准地对变压器进行故障诊断。     

基于量子元胞自动机的PLA故障分析和检测

量子元胞自动机(quantum-dot cellular automata,QCA)可编程逻辑阵列(programma-ble logic array,PLA)结构可用于实现大规模可编程逻辑电路。分析了4种故障类型发生在PLA单元的8个区域中的影响,得出了具体的影响效果。其中,直接或间接致使隐含线和与门发生逻辑错误的故障均会导致PLA中故障所在行整行失效,其他故障只会影响故障所在的PLA单元的逻辑功能和配置,而对PLA中的其他单元没有影响。此外,基于故障分析,提出了具体的PLA故障检测方法。     

Voltage-based fault path tracing by transistor operating point analysis

A novel diagnosis technology based on transistor operating point analysis is presented. This technology is the way to detect penetration current net result from fault, replace the net with impedance net, calculate voltage value of each node of the impedance net by OHM’s low, and then sequentially trace the fault logic propagation. The impedance is determined by using transistor dimension and its operating point managed by gate voltage. The proposed method makes it possible to detect not only signal propagation of each gate in order of time, but oscillation phenomenon brought by feedback fault.     

FAULT DETECTION TEST SET FOR TESTABLE REALIZATIONS OF LOGIC FUNCTIONS WITH ESOP EXPRESSIONS

The circuit testable realization and its fault detection for logic functions with ESOP （EXOR-Sum-Of-Products） expressions are studied. First of all, for the testable realization by using XOR gate cascade, a test set with 2n ＋ m ＋ 1 vectors for the detections of AND bridging faults and a test set with 2n ＋ m vectors for the detections of OR bridging faults are presented. Secondly, for the testable realization by using ）（OR gate tree, a test set with 2n ＋ m vectors for the detections of AND bridging faults and a test set with 3n ＋ m ＋ 1 vectors for the detections of OR bridging faults are presented. Finally, a single fault test set with n ＋ 5 vectors for the XOR gate tree realization is presented. Where n is the number of input variables and m is the number of product terms in a logic function.     

A Classification-Based Fault Detection and Isolation Scheme for the Ion Implanter

We propose a classification-based fault detection and isolation scheme for the ion implanter. The proposed scheme consists of two parts: 1) the classification part and 2) the fault detection and isolation part. In the classification part, we propose a hybrid classification tree (HCT) with learning capability to classify the recipe of a working wafer in the ion implanter, and a k-fold cross-validation error is treated as the accuracy of the classification result. In the fault detection and isolation part, we propose a warning signal generation criteria based on the classification accuracy to detect and fault isolation scheme based on the HCT to isolate the actual fault of an ion implanter. We have compared the proposed classifier with the existing classification software and tested the validity of the proposed fault detection and isolation scheme for real cases to obtain successful results