Wireless communication in a flip-chip package using integrated antennas on silicon substrates

An intrachip wireless interconnect using integrated antennas is demonstrated in a flip-chip ball grid array package. The wireless interconnect consists of a transmitter-receiver pair, which is fabricated in a 0.18-/spl mu/m CMOS process. A 15-GHz signal is generated and broadcasted across the integrated circuit. The signal is picked up by a receiver 4 mm away on the same integrated circuit and frequency divided by eight to produce a 1.875-GHz local clock signal. The interconnection is also demonstrated between a transmitting antenna and a packaged receiver 40 cm away from the transmitting antenna. Demonstration of intrachip wireless interconnects in a package has been considered the ultimate test for this technology.     

A 77-GHz Phased-Array Transceiver With On-Chip Antennas in Silicon: Receiver and Antennas

In this paper, we present the receiver and the on-chip antenna sections of a fully integrated 77-GHz four-element phased-array transceiver with on-chip antennas in silicon. The receiver section of the chip includes the complete down-conversion path comprising low-noise amplifier (LNA), frequency synthesizer, phase rotators, combining amplifiers, and on-chip dipole antennas. The signal combining is performed using a novel distributed active combining amplifier at an IF of 26 GHz. In the LO path, the output of the 52-GHz VCO is routed to different elements and can be phase shifted locally by the phase rotators. A silicon lens on the backside is used to reduce the loss due to the surface-wave power of the silicon substrate. Our measurements show a single-element LNA gain of 23 dB and a noise figure of 6.0dB. Each of the four receive paths has a gain of 37 dB and a noise figure of 8.0 dB. Each on-chip antenna has a gain of +2 dBi     

A 24-GHz Transmitter With On-Chip Dipole Antenna in 0.13-$mu$m CMOS

A fully integrated dual-conversion transmitter chain with an on-chip dipole antenna and an integer-N synthesizer operating in the 24-GHz Instrument, Scientific and Medical (ISM) band was fabricated in 0.13-mum CMOS. The choice of 24-GHz operation enables the integration of a 4-mm long antenna on chip. The transmitter chain can support data rate of 100 Mb/s. It provides 6-dBm output power to a 100-Omega load at 22.4 GHz with 152-mW power dissipation including that of a frequency synthesizer. At this output power level, the dual conversion architecture can mitigate the VCO pulling even when an antenna and a power amplifier are integrated on the same substrate as the VCO. The out-of-band emissions due to the modulation side lobes and image have been sufficiently suppressed. The stray emissions of local oscillator can also be reduced using circuit techniques. The signal from the transmitter has been picked up 95 meters away with a horn antenna, which suggests that wireless communications between a single chip radio and a base station 100 meters away is possible.     

A 6-Gb/s Wireless Inter-Chip Data Link Using 43-GHz Transceivers and Bond-Wire Antennas

A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10^-8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.     

A CMOS 10-gb/s SONET transceiver

This paper presents a single-chip SONET OC-192 transceiver (transmitter and receiver) fabricated in a 90-nm mixed-signal CMOS process. The transmitter consists of a 10-GHz clock multiplier unit (CMU), 16:1 multiplexer, and 10-Gb/s output buffer. The receiver consists of a 10-Gb/s limiting input amplifier, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. Both transmit and receive phase-locked loops employ a 10-GHz on-chip LC voltage-controlled oscillator (VCO). This transceiver exceeds all SONET OC-192 specifications with ample margin. Jitter generation at 10.66-Gb/s data rate is 18 mUI/sub pp/ (unit interval, peak-to-peak) and jitter tolerance is 0.6 UI/sub pp/ at 4-MHz jitter frequency. This transceiver requires 1.2V for the core logic and 1.8 V for input/output LVDS buffers. Multiple power supply domains are implemented here to mitigate crosstalk between receiver and transmitter. The overall power dissipation of this chip is 1.65 W.     

A Silicon 60-GHz Receiver and Transmitter Chipset for Broadband Communications

A 0.13-mum SiGe BiCMOS double-conversion superheterodyne receiver and transmitter chipset for data communications in the 60-GHz band is presented. The receiver chip includes an image-reject low-noise amplifier (LNA), RF-to-IF mixer, IF amplifier strip, quadrature IF-to-baseband mixers, phase-locked loop (PLL), and frequency tripler. It achieves a 6-dB noise figure, -30 dBm IIP3, and consumes 500 mW. The transmitter chip includes a power amplifier, image-reject driver, IF-to-RF upmixer, IF amplifier strip, quadrature baseband-to-IF mixers, PLL, and frequency tripler. It achieves output P_1dB of 10 to 12dBm, P_sat of 15 to 17 dBm, and consumes 800 mW. The chips have been packaged with planar antennas, and a wireless data link at 630 Mb/s over 10 m has been demonstrated     

Highly integrated 60 GHz transmitter and receiver MMICs in a GaAs pHEMT technology

Highly integrated transmitter and receiver MMICs have been designed in a commercial 0.15 /spl mu/m, 88 GHz f/sub T//183 GHz f/sub MAX/ GaAs pHEMT MMIC process and characterized on both chip and system level. These chips show the highest level of integration yet presented in the 60 GHz band and are true multipurpose front-end designs. The system operates with an LO signal in the range 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO chain, resulting in an IF center frequency of 2.5 GHz. Although the chips are inherently multipurpose designs, they are especially suitable for high-speed wireless data transmission due to their very broadband IF characteristics. The single-chip transmitter MMIC consists of a balanced resistive mixer with an integrated ultra-wideband IF balun, a three-stage power amplifier, and the X8 LO chain. The X8 is a multifunction design by itself consisting of a quadrupler, a feedback amplifier, a doubler, and a buffer amplifier. The transmitter chip delivers 3.7/spl plusmn/1.5 dBm over the RF frequency range of 54-61 GHz with a peak output power of 5.2 dBm at 57 GHz. The single-chip receiver MMIC contains a three-stage low-noise amplifier, an image reject mixer with an integrated ultra-wideband IF hybrid and the same X8 as used in the transmitter chip. The receiver chip has 7.1/spl plusmn/1.5 dB gain between 55 and 63 GHz, more than 20 dB of image rejection ratio between 59.5 and 64.5 GHz, 10.5 dB of noise figure, and -11 dBm of input-referred third-order intercept point (IIP3).     

Low-power fully integrated 10-Gb/s SONET/SDH transceiver in 0.13-/spl mu/m CMOS

Here, we present a low-power fully integrated 10-Gb/s transceiver in 0.13-/spl mu/m CMOS. This transceiver comprises full transmit and receive functions, including 1:16 multiplex and demultiplex functions, high-sensitivity limiting amplifier, on-chip 10-GHz clock synthesizer, clock-data recovery, 10-GHz data and clock drivers, and an SFI-4 compliant 16-bit LVDS interface. The transceiver exceeds all SONET/SDH (OC-192/STM-64) jitter requirements with significant margin: receiver high-frequency jitter tolerance exceeds 0.3 UI/sub pp/ and transmitter jitter generation is 30 mUI/sub pp/. All functionality and specifications (core and I/O) are achieved with power dissipation of less than 1 W.     

On-chip integrated antenna structures in CMOS for 60 GHz WPAN systems

This paper presents several on-chip antenna structures that may be fabricated with standard CMOS technology for use at millimeter wave frequencies. On-chip antennas for wireless personal area networks (WPANs) promise to reduce interconnection losses and greatly reduce wireless transceiver costs, while providing unprecedented flexibility for device manufacturers. This paper presents the current state of research in on-chip integrated antennas, highlights several pitfalls and challenges for on-chip design, modeling, and measurement, and proposes several antenna structures that derive from the microwave microstrip and amateur radio art. This paper also describes an experimental test apparatus for performing measurements on RFIC systems with on-chip antennas developed at The University of Texas at Austin.     

A 2-V CMOS cellular transceiver front-end

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-μm CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-μm CMOS technology, without tuning or trimming     

Terahertz MMICs and Antenna-in-Package Technology at 300 GHz for KIOSK Download System

Toward the realization of ultra-fast wireless communications systems, the inherent broad bandwidth of the terahertz (THz) band is attracting attention, especially for short-range instant download applications. In this paper, we present our recent progress on InP-based THz MMICs and packaging techniques based on low-temperature co-fibered ceramic (LTCC) technology. The transmitter MMICs are based on 80-nm InP-based high electron mobility transistors (HEMTs). Using the transmitter packaged in an E-plane split-block waveguide and compact lens receiver packaged in LTCC multilayered substrates, we tested wireless data transmission up to 27 Gbps with the simple amplitude key shifting (ASK) modulation scheme. We also present several THz antenna-in-packaging solutions based on substrate integrated waveguide (SIW) technology. A vertical hollow (VH) SIW was applied to a compact medium-gain SIW antenna and low-loss interconnection integrated in LTCC multi-layer substrates. The size of the LTCC antennas with 15-dBi gain is less than 0.1 cm³. For feeding the antenna, we investigated an LTCC-integrated transition and polyimide transition to LTCC VH SIWs. These transitions exhibit around 1-dB estimated loss at 300 GHz and more than 35 GHz bandwidth with 10-dB return loss. The proposed package solutions make antennas and interconnections easy to integrate in a compact LTCC package with an MMIC chip for practical applications.     

Micropower circuits for bidirectional wireless telemetry in neural recording applications

State-of-the art neural recording systems require electronics allowing for transcutaneous, bidirectional data transfer. As these circuits will be implanted near the brain, they must be small and low power. We have developed micropower integrated circuits for recovering clock and data signals over a transcutaneous power link. The data recovery circuit produces a digital data signal from an ac power waveform that has been amplitude modulated. We have also developed an FM transmitter with the lowest power dissipation reported for biosignal telemetry. The FM transmitter consists of a low-noise biopotential amplifier and a voltage controlled oscillator used to transmit amplified neural signals at a frequency near 433 MHz. All circuits were fabricated in a standard 0.5-microm CMOS VLSI process. The resulting chip is powered through a wireless inductive link. The power consumption of the clock and data recovery circuits is measured to be 129 microW; the power consumption of the transmitter is measured to be 465 microW when using an external surface mount inductor. Using a parasitic antenna less than 2 mm long, a received power level was measured to be -59.73 dBm at a distance of one meter.     

OC-192 transmitter and receiver in standard 0.18-/spl mu/m CMOS

This paper presents the first fully integrated SONET OC-192 transmitter and receiver fabricated in a standard 0.18-/spl mu/m CMOS process. The transmitter consists of an input data register, 16-b-wide first-in-first-out (FIFO) circuit, clock multiplier unit (CMU), and 16:1 multiplexer to give a 10-Gb/s serial output. The receiver integrates an input amplifier for 10-Gb/s data, clock and data recovery circuit (CDR), 1:16 demultiplexer, and drivers for low-voltage differential signal (LVDS) outputs. An on-chip LC-type voltage-controlled oscillator (VCO) is employed by both the transmitter and receiver. The chipset operates at multiple data rates (9.95-10.71 Gb/s) with functionality compatible with the multisource agreement (MSA) for 10-Gb transponders. Both chips demonstrate SONET-compliant jitter characteristics. The transmitter 10.66-GHz output clock jitter is 0.065 UI/sub pp/ (unit interval, peak-to-peak) over a 50-kHz-80-MHz bandwidth. The receiver jitter tolerance is more than 0.4 UI/sub pp/ at high frequencies (4-80 MHz). A high level of integration and low-power consumption is achieved by using a standard CMOS process. The transmitter and receiver dissipate a total power of 1.32 W at 1.8 V and are packaged in a plastic ball grid array with a footprint of 11/spl times/11 mm/sup 2/.     

Low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications

State-of-the-art endoscopy systems require electronics allowing for real-time, bidirectional data transfer. Proposed are 2.4-GHz low-power transceiver analog front-end circuits for bidirectional high data rate wireless telemetry in medical endoscopy applications. The prototype integrates a low-IF receiver analog front-end [low noise amplifier (LNA), double balanced down-converter, bandpass-filtered automatic gain controlled (AGC) loop and amplitude-shift keying (ASK) demodulator], and a direct up-conversion transmitter analog front-end [20-MHz IF phase-locked loop (PLL) with well-defined amplitude control circuit, ASK modulator, up-converter, and power amplifier] on a single chip together with an internal radio frequency oscillator and local oscillating (LO) buffers. Design tradeoffs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. The circuits have been implemented in a 0.25-microm CMOS process. The measured sensitivity of the receiver analog front-end is -70 dBm with a data rate of 256 kbps, and the measured output power of the transmitter analog front-end could achieve -23 dBm with a data rate of 1 Mbps. The integrated circuit consumes a current of 6 mA in receiver mode and 5.6 mA in transmitter mode with a power supply of 2.5 V. This paper shows the feasibility of achieving the analog performance required by the wireless endoscopy capsule system in 0.25 microm CMOS.     

A Low Power Fully CMOS Integrated RF Transceiver IC for Wireless Sensor Networks

A fully CMOS integrated RF transceiver for ubiquitous sensor networks in sub-gigahertz industrial, scientific, and medical (ISM)-band applications is implemented and measured. The integrated circuit is fabricated in 0.18-mum CMOS technology and packaged in leadless plastic chip carrier (LPCC) package. The fully monolithic transceiver consists of a receiver, a transmitter, and an RF synthesizer with on-chip voltage-controlled oscillator. The chip fully complies with the IEEE 802.15.4 wireless personal area network in sub-gigahertz mode. The cascaded noise figure of the overall receiver is 9.5 dB and the overall transmitter achieves less than 6.3% error vector magnitude for 40 kb/s mode. The chip uses 1.8-V power supply and the power consumption is 25 mW for reception mode and 29 mW for transmission mode     

Monolithic Integration of a Folded Dipole Antenna With a 24-GHz Receiver in SiGe HBT Technology

The integration of an on-chip folded dipole antenna with a monolithic 24-GHz receiver manufactured in a 0.8-mum SiGe HBT process is presented. A high-resistivity silicon substrate (1000 Omega ldr cm) is used for the implemented circuit to improve the efficiency of the integrated antenna. Crosstalk between the antenna and spiral inductors is analyzed and isolation techniques are described. The receiver, including the receive and an optional transmit antenna, requires a chip area of 4.5 mm² and provides 30-dB conversion gain at 24 GHz with a power consumption of 960 mW.     

120-GHz wireless link using photonic techniques for generation, modulation, and emission of millimeter-wave signals

We present a wireless link system that uses millimeter-wave (MMW) photonic techniques. The photonic transmitter in the wireless link consists of an optical 120-GHz MMW generator, an optical modulator, and a high-power photonic MMW emitter. A uni-traveling carrier photodiode (UTC-PD) was used as the photonic emitter in order to eliminate electronic MMW amplifiers. We evaluated the dependence of UTC-PD output power on its transit-time limited bandwidth and its CR-time constant limited bandwidth, and employed a UTC-PD with the highest output power for the photonic emitter. As for the MMW generation, we developed a 120-GHz optical MMW generator that generates a pulse train and one that generates a sinusoidal signal. The UTC-PD output power generated by a narrow pulse train was higher than that generated by sinusoidal signals under the same average optical power condition, which contributes to reducing the photocurrent of the photonic emitter. We have experimentally demonstrated that the photonic transmitter can transmit data at up to 3.0 Gb/s. The wireless link using the photonic transmitter can be applied to optical gigabit Ethernet signals.     

芯片内/间无线互连技术发展综述

为了解决超大规模集成电路布线复杂的问题,无线互连技术(WIT)应运而生。介绍了实现芯片内/间无线互连的两类技术,一类是基于片上天线的无线互连技术,另一类是基于AC耦合的无线互连技术。从实现成本、功耗,传输性能方面对这两类技术进行了分析与比较,讨论了它们的具体应用及适用范围,同时也总结了两者目前存在的问题,并指出了其未来的研究方向,对今后芯片内/间无线互连技术的应用研究具有一定的参考意义。     

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

Integrated 460 GHz photonic transmitter module

A photonic sub-millimetre (sub-mm) wave transmitter module has been developed and fabricated. The module consists of a 1.55 μm waveguide InP photodetector monolithically integrated with a planar full wave slot antenna and passive lowpass filter for DC bias supply. For the first time, optical heterodyne 460 GHz sub-mm signal generation is demonstrated It is further shown that the module can effectively replace the classical solid-state oscillator of an astronomical superconductor-insulator-superconductor heterodyne receiver The module generates sufficient sub-mm wave power to operate the receiver under optimum conditions