Optimal global interconnects for GSI

Performance of a high-speed chip is largely affected by both latency and bandwidth of global interconnects, which connect different macrocells. Therefore, one of the important goals is to design high-bandwidth and fast buses that connect a processor and its on-chip cache memory or link different processors within a multiprocessor chip. In this paper, the width of global interconnects is optimized to achieve a large "data-flux density" and a small latency simultaneously. Data-flux density is the product of interconnect bandwidth and reciprocal wire pitch, which represents the number of bits per second that can be transferred across a unit-length bisectional line. The optimal wire width, which maximizes the product of data-flux density and reciprocal latency, is independent of interconnect length and can be used for all global interconnects. It is rigorously proved that the optimal wire width is the width that results in a delay that is 33% larger than the time-of-flight (ToF). Using the optimal wire width decreases latency, energy dissipation, and repeater area considerably, compared to a sub-optimal wire width (e.g., 42% smaller latency, 30% smaller energy-per-bit, and 84% smaller repeater area compared with the W/sub opt//2 case) at the cost of a small decrease in data-flux density (e.g., 14% smaller compared with W/sub opt//2 case). A super-optimal wire width, however, causes a slight decrease in latency (e.g., 14% for 2W/sub opt/) at the cost of a large decrease in data-flux density (e.g., 35% for 2W/sub opt/).     

A comprehensive 2-D inductance modeling approach for VLSI interconnects: frequency-dependent extraction and compact circuit model synthesis

Although three-dimensional (3-D) partial inductance modeling costs have decreased with stable, sparse approximations of the inductance matrix and its inverse, 3-D models are still intractable when applied to full chip timing or crosstalk analysis. The 3-D partial inductance matrix (or its inverse) is too large to be extracted or simulated when power-grid cross-sections are made wide to capture proximity effect and wires are discretized finely to capture skin effect. Fortunately, 3-D inductance models are unnecessary in VLSI interconnect analysis. Because return currents follow interconnect wires, long interconnect wires can be accurately modeled as two-dimensional (2-D) transmission lines and frequency-dependent loop impedances extracted using 2-D methods . Furthermore, this frequency dependence can be approximated with compact circuit models for both uncoupled and coupled lines. Three-dimensional inductance models are only necessary to handle worst case effects such as simultaneous switching in the end regions. This paper begins by explaining and defending the 2-D modeling approach. It then extends the extraction algorithm to efficiently include distant return paths. Finally, a novel synthesis technique is described that approximates the frequency-dependent series impedance of VLSI interconnects with compact circuit models suitable for timing and noise analysis.     

Efficient and accurate crosstalk prediction via neural net-basedtopological decomposition of 3-D interconnect

Crosstalk-related issues have become increasingly important with deep submicron downscaling of ICs and wafer scale integration. In today's systems-on-a-chip, the delay through a wire is often greater than the delay through the gate driving it. Furthermore, because of significant parasitic effects, crosstalk between signals on wires can cause major problems. Improved management of the EMI problem is made possible via EDA tools which have the capability of accurately and efficiently modeling electromagnetic interference effects in nanoscale VLSI. However, existing tools are computationally expensive and do not have broad application. The novel methodology proposed in this paper involves topological decomposition of small portions of interconnect (referred to as wirecells) at an extreme level of detail and the creation of parameterized models of these primitive interconnect structures using modular artificial neural networks (MANNs). The technique uses a finite element method program coupled with a circuit simulator and a neural network multi-paradigm prototyping system to produce a library of standard MANN-based wirecell models. It is especially attractive because none of the existing approaches is capable of fully modeling the simultaneous effect on delay and crosstalk of several uncorrelated variables such as interconnect length, width, thickness, separation, metal and insulating medium conductivity and relative permittivity for multiple systems of conductors. The library models derived are used to predict delay noise and crosstalk resulting from interconnect structures embedded in actual analog and digital circuitry     

Compact distributed RLC interconnect models-Part II: Coupled linetransient expressions and peak crosstalk in multilevel networks

For pt. I see ibid., vol. 47, no. 11, (Nov. 2000). Novel compact expressions that describe the transient response of high-speed resistance, inductance, and capacitance (RLC) coupled interconnects are rigorously derived. These new distributed rlc models reveal that peak crosstalk voltage is over 60% larger for 3 GHz high-speed interconnects than predicted by current distributed RC models. Simplified forms of the compact models enable physical insight and accurate estimation of peak crosstalk voltage between two and three distributed RLC interconnects     

Transient current propagation along a wire penetrating a circularaperture in an infinite planar conducting screen

The shielding properties of a wire penetrating an infinite planar screen are considered. Time domain results are presented for the case of a transient current pulse propagating along the wire. These results are obtained by first computing numerical solutions for the problem in the frequency domain and then utilizing the inverse Fourier transform. Two double exponential pulses with differing characteristics are considered. Numerical results for the two pulses are compared to determine the effects of the pulse characteristics on the shielding properties of the geometry. Applications to via structures in high-speed circuits are also briefly discussed. It is observed that even for very small apertures, the effect of the screen on the low-frequency pulse is negligible. As the pulse width decreases, the effect of the screen becomes more prominent. For the high-frequency case, the pulse is significantly affected by the screen. Unlike the low-frequency pulse, the amplitude of the high-frequency pulse is dependent on the aperture size. Even for large apertures, the attenuation becomes significant as the current propagates down the wire. It is shown that as the width of the input pulse decreases, the distortion in the pulse shape becomes more pronounced. This effect is especially important in applications related to high-speed integrated circuits     

Crosstalk between microstrip transmission lines

Methods for prediction of crosstalk between microstrip transmission lines are reviewed and simplified for the weak-coupling case. Classical coupled transmission line theory is used for uniform lines, and potential and induced EMF methods are used for crosstalk between nonuniform lines. It is shown that the potential method is equivalent to classical coupled transmission line theory for the case of uniform lines. An experiment was performed for uniform coupled microstrip lines for frequencies from 50 MHz to 5 GHz, and good agreement between theory and measurement was obtained for both near- and far-end crosstalk     

Evaluation of closed-form crosstalk models of coupled transmissionlines

Closed-form crosstalk models used for the estimation of near and far end crosstalk voltages between two parallel transmission lines are evaluated. The quantitative validity ranges, in terms of transmission line length and coupling strength, of the crosstalk models are presented. It is shown that the accuracy of the commonly used closed-form crosstalk models deteriorates as the increase of the coupling strength and the line length     

Crosstalk Stability Analysis in Multilayer Graphene Nanoribbon Interconnects

In this paper a time-domain response and Nyquist stability criterion to acquire dependence of degree of crosstalk relative stability based on transmission lines modeling (TLM) is investigated for coupled multilayer graphene nanoribbon (MLGNR) interconnects. This is the first instance that such an analysis has been presented for coupled MLGNR consisting of both capacitive and mutual-inductive couplings. The near-end and far-end outputs of coupled MLGNR individually are compared in two cases, with considering both couplings and without them (single MLGNR). It is observed that the near-end output of the system together with both couplings is more stable and at its far-end output, an induced voltage is created. By increasing capacitive coupling or decreasing inductive coupling, the near-end output becomes more stable. Also, the results of changes of length and width of each ribbon show that by increasing the length and decreasing the width, the coupled MLGNR interconnects become more stable.     

A multiline model for time-efficient estimation of crosstalk

This work proposes a novel and accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. Using the realistic exponential waveform and a reduced transfer function, the proposed model presents a complete multiline noise model by representing active and passive aggressors simultaneously on the victim line. In the model, active aggressors are easily represented by current sources and passive aggressors are accurately modeled as equivalent capacitances to victim. Each current source representing an active aggressor carries the same accuracy as the 2-π representation. Equivalent capacitances for passive aggressors, on the other hand, consider resistive shielding effect and the realistic exponential aggressor waveform. This approach allows one to obtain a general noise model that considers the effect of many active and passive aggressors and general formulas derived can easily be applied to real cases. Noise peak and width expressions are derived and results are in good agreement with HSPICE results. Results show that average error for noise peak is 4.3% and for the width is 6.9% while allowing for very fast analysis.     

Spatio-temporal coding to improve speed and noise tolerance of on-chip interconnect

This paper introduces a new coding scheme that simultaneously tackles different design issues of interconnections such as noise, crosstalk and power consumption. The scheme is based on temporal skewing between data words on even and odd lines of an interconnection link, and its hardware implementation is simple and area-efficient. The proposed scheme permits to double the bandwidth of the interconnect while improving its noise tolerance. This is achieved through the simultaneous use of two error detecting techniques: temporal redundancy and parity. Improved noise tolerance property provided by our design enables to decrease the power supply voltage and hence to reduce power consumption of the interconnect.     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

Methods of summing crosstalk from mixed sources. I. Theoreticalanalysis

Digital subscriber lines (DSLs) are fundamentally limited by crosstalk. The case where all crosstalk is from the same type of DSL has been studied over the years and accurate models have been standardized. However, crosstalk from multiple different types of DSLs is a relatively new area of study and models of summing mixed crosstalk have only recently been postulated. As more and more types of DSLs are deployed by multiple service providers, it is imperative to gain confidence in the method of modeling worst-case mixed crosstalk and to understand its limitations in order to enable efficient spectrum management of the loop plant. All known crosstalk summation methods are described here in detail and their properties are compared. This paper also presents a new methodology for deriving sound crosstalk summation methods. This new methodology consists of deriving lower bounds to the worst-case method, which is intrinsically too pessimistic. In particular, it has been ascertained that the Minkowski inequality and, to a lesser extent, the Holder inequality, yield new crosstalk summation methods that exhibit appealing properties. It is also shown here that the standardized full service access network (FSAN) method is a particular case of the more general Minkowski-bound method     

Simultaneous Shield and Buffer Insertion for Crosstalk Noise Reduction in Global Routing

As VLSI technologies scale down, interconnect performance is greatly affected by crosstalk noise due to the decreasing wire separation and increased wire aspect ratio, and crosstalk has become a major bottleneck for design closure. The effectiveness of traditional buffering and spacing techniques for noise reduction is constrained by the limited available resources on chip. In this paper, we present a method for incorporating crosstalk reduction criteria into global routing under a broad power supply network paradigm. This method utilizes power/ground wires as shields between signal wires to reduce capacitive coupling, while considering the constraints imposed by limited routing and buffering resources. An iterative procedure is employed to route signal wires, assign supply shields, and insert buffers so that both buffer/routing capacity and signal integrity goals are met. In each iteration, shield assignment and buffer insertion are considered simultaneously via a dynamic programming-like approach. Our noise calculations are based on Devgan's metric, and our work demonstrates, for the first time, that this metric shows good fidelity on average. An effective noise margin inflation technique is also proposed to compensate for the pessimism of Devgan's metric. Experimental results on testcases with up to about 10000 nets point towards an asymptotic runtime that increases linearly with the number of nets. Our algorithm achieves noise reduction improvements of up to 53% and 28%, respectively, compared to methods considering only buffer insertion or only shield insertion after buffer planning.     

Accurate estimation of the error probability in the presence of in-band crosstalk noise in WDM networks

In-band crosstalk noise can pose important limitations in wavelength-division-multiplexing (WDM) optical networks. This paper describes a model that takes into account the statistical behavior of in-band crosstalk noise accurately and that can be used to estimate the error probability (EP) in a WDM receiver. It is based on the formulation of the moment-generating function of the decision variable in terms of a double integral, which allows the inclusion of the crosstalk-crosstalk noise, which was previously neglected in the literature. The optical amplifier noise and the electrical receiver noise are also incorporated, and the model is used to assess the implications of the crosstalk-crosstalk contribution. With the aid of some examples, it is shown that the crosstalk-crosstalk noise can influence the value of the EP, change the optimum receiver threshold, and introduce some power penalty.     

The problem of summing crosstalk from mixed sources

Digital subscriber lines (DSL) are fundamentally limited by crosstalk. The case where all crosstalk is from the same type of DSL has been studied over the years and accurate models have been standardized. However, crosstalk from multiple different types of DSLs is a relatively new area of study and models of summing mixed crosstalk have only recently been postulated. The goal of this paper is twofold: firstly, to point out the lack of this subject in the current literature; secondly, to propose a new method of summing crosstalk due to mixed sources. This new method consists of deriving a lower bound to the worst-case method, which is intrinsically too pessimistic. Moreover, it is shown here for the first time that the full service access network (FSAN) method is a particular case of the proposed method     

Edge effect aware low-power crosstalk avoidance technique for 3D integration

Metal wires and through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs due to their high capacitive crosstalk which can be reduced using coding techniques. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV bundles. Additionally, these 3D CACs do not reduce the metal wire crosstalk and dramatically increase the power consumption of 2D and 3D interconnects. This work presents a 3D CAC which overcomes previous limitations. The method is based on an intelligent fixed mapping of the bits of existing 2D CACs onto rectangular or hexagonal TSV arrangements. Simulation results, obtained by circuit simulations in combination with an electromagnetic field solver, show that existing 3D CACs only reduce the TSV crosstalk by a maximum of 9.4%, provide no optimization of the metal wire crosstalk and induce an increase in the interconnect power consumption by about 50%. In contrast, the presented technique requires less hardware and reduces the maximum crosstalk of modern TSV and metal wire buses by 37.8% and 47.6%, respectively, while leaving their power consumption almost unaffected. Alternatively, our technique can reduce the TSV and metal wire crosstalk peaks by 20.3% and 47.7%, respectively, while additionally providing a reduction in the TSV and metal wire power consumption by 5.3% and 21.9%, respectively.     

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations     

Calculation of the characteristics of two-wire lines in multiconductor cables

A rigorous method is proposed for calculating the parameters of two-wire lines (twisted pairs) surrounded by a single metal shield and the mutual coupling between these lines. It is shown that coupling between the lines in multiconductor cables results in electromagnetic interference (crosstalk) in communications channels and that inphase currents in the lines are caused by the asymmetry of excitation and loads. The stray voltages induced across the impedances placed at the beginning and the end of an adjacent line are determined at a given power in the main line. The effect produced by the loads placed between the wires and the shield is considered. The proposed method allows generalization of the obtained results to the case of lossy multiconductor cables.     

V型人工电源网络寄生效应MATLAB仿真研究

运用MATLAB仿真软件分析了分立元件各寄生参数对分压系数、隔离度、串扰及阻抗的影响。通过分析接地和金属板的两种基本串扰形式,建立了人工电源网络（AMN）相应的等效电路模型,并用MATLAB仿真软件分析了两种模型下的寄生参数对AMN隔离度、阻抗的影响。结果表明：寄生参数及其耦合关系对AMN测量有较大影响。     

Performance study of high-speed asymmetric digital subscriber linestechnology

Computer simulation results are presented for the loop range coverage of an asymmetric digital subscriber lines (ADSL) system that uses the quadrature amplitude modulation (QAM) signaling scheme, ADSL performance is evaluated in the presence of background additive white Gaussian noise (AWGN), and crosstalk noise from existing services in the local telephone loop plant. It is shown that coverage of the extreme carrier serving area (CSA) is possible at transmission rates that are well above the existing T1 rate