一位QCA数值比较器的可靠性研究

针对量子元胞自动机电路中存在的元胞移位、元胞未对准、元胞遗漏、元胞旋转等固有缺陷,采用概率转移矩阵方法建立了一位QCA数值比较器的可靠性模型,并对其可靠性进行了深入分析。对于不同的输入,分别比较了各组成元件在同样的故障概率水平下对整体可靠性(正确输出的概率)的不同影响。仿真结果表明,在所有的输入情况下传输线始终是影响其可靠性的主要因素,从而确定了传输线在该数值比较器中的重要性,进而为大规模QCA数值比较器的设计以及可靠性的提高提供了依据。     

基于概率模型的QCA触发器可靠性研究

通过将时序逻辑电路中的反馈回路打开,在原有电路结构的基础上增加一路输入,采用概率转移矩阵方法建立了基于QCA的RS触发器、D触发器、JK触发器的可靠性模型,深入研究了各组成元件对其可靠性影响的差异,从而为其可靠性的提高提供了依据,这对于高缺陷率的QCA电路的可靠性设计具有重要的指导意义。     

基于量子细胞自动机的数值比较器设计

量子细胞自动机(QCA)可以构建逻辑门和QCA线。该文基于QCA设计了1位,4位和8位数值比较器,并用QCADesigner软件进行模拟。结果表明,所设计的电路具有正确的逻辑功能。通过对电路所需细胞数、面积和时延三方面性能分析,表明所设计的电路时延并不随输入位数呈线性增加,因而所设计的电路具有良好的时延性。     

两点量子元胞自动机逻辑电路设计与仿真

择多逻辑门和反相器是量子元胞自动机(QCA)逻辑电路的基本组件。设计了两点量子元胞自动机(两点QCA)的传输线、择多逻辑门和反相器等基本逻辑器件。通过仅在信号沿竖直方向传递需要取反时用到水平放置元胞的设计,使电路布局更加紧凑。利用这些基本逻辑器件完成了一位数值比较器电路的设计。基于两点QCA系统的半经典模型,利用遗传模拟退火法对电路功能进行了仿真。仿真结果显示,两点QCA同样能够有效实现传统四点QCA的功能,而其所需的电子数和量子点数均减少了32.1%,电路集成度提高了49.4%。     

基于贝叶斯模型的QCA扇出结构转换特性

基于半径为2的贝叶斯模型,量化分析了量子元胞自动机(QCA)扇出结构的转换特性。分析表明,采用半径为1的贝叶斯模型进行QCA转换特性分析将导致传输线正确概率的误差增大到40%,而半径为2的贝叶斯模型平衡了运算量和计算精度,适用于QCA的可靠性分析。仿真表明,扇出结构的正确概率随元胞尺寸和元胞间距的增大而逐渐降低,也随着输入条件和输出端的不同而改变,输入为‘1’时,扇出的拐角输出端的正确概率高于85%,而输入为‘0’时,拐角输出端的正确概率低于20%。这是由于QCA是一种基于量子机理进行工作的器件,不同的输入或不同的元胞尺寸和元胞间距都将造成元胞扭结能的改变,进而影响元胞的翻转概率。研究所得结论可为今后QCA的电路实现与设计和可靠性分析提供参考。     

多台阶衍射光学元件的工艺优化

通过对多台阶衍射光学元件(MDOE)刻蚀工艺中的误差分析,提出了一个反映整体刻蚀误差的参数--误差偏度.重点研究了误差偏度的变化对多台阶衍射光学元件光束整形效果的影响,发现在误差偏度曲线中存在一个能使刻蚀误差影响减弱的平坦区间.提出了在刻蚀工艺上以控制刻蚀深度来改善多台阶衍射光学元件器件实际照明效果的一种方法.实验结果表明,经过工艺优化后的MDOE的光场参数峰值(PV)下降了近30%.     

聚合物整体灌装电路板热应力分析

电路板的聚合物整体灌装是一种提高电子器件在极端工况下可靠性的方法。针对该方法所面临的热应力失效问题,采用有限元数值方法研究了含15个元器件的整体灌装电路板在环境温度改变和器件产热两种热载荷下的热应力分布,并通过参数化模拟分析了不同几何和材料参数对元器件及其接合层中热应力分布的影响。结果表明整体灌装加剧了IC器件及其接合层的热应力,该模拟工作为提高整体灌装方案的热应力可靠性提供参考。     

基于PolSK调制格式的FWM型全光比较器

文章提出了一种利用偏振移位键控(PolSK)信号光,基于半导体光放大器(SOA)中的四波混频(FWM)效应的超快全光比较器方案.该方案由于采用了功率恒定的PolSK信号光,可以消除SOA中的码型效应.通过数值模拟,研究了两输入信号光功率、SOA注入电流以及有源区长度对超快全光比较器输出特性的影响.     

一种自适应迟滞性比较器的设计

设计了一种由滤波器和迟滞比较器构成的传输频率信号电路。设计使用滤波器将输入信号改变适当的相位作为迟滞比较器标准端的信号,而原信号输入比较器的另一端。那么由于迟滞比较器标准端的电压同时随输入信号改变。电路对不同的信号有一定的适应能力。即对不同的输入信号,不需要另外确定标准端的电压。简化了电路,提高了可靠性。同时滤波器的加入使电路同时获得频率选择的能力。仿真证明了电路的可行性。     

一种通用的可逆比较器级联方法

可逆数值比较器是可逆计算机中诸多运算器中的重要组成部分。为了提升可逆比较器的通用性,进一步优化可逆比较器电路。分析了比较器的输入与输出的逻辑关系,提出并设计了一位可逆比较器(OBC)和一位可逆完全比较器(OBCC)。在此基础上将这两种器件进行级联,可以快速生成通用可逆比较器的级联电路.与相关文献对比,该级联方法有效的减少了常量输入和垃圾输出的同时,具有较低的量子代价,易于完成多位二进制数值在可逆电路中的比较。     

Single-bit digital comparator circuit design using quantum-dot cellular automata nanotechnology

The large amount of secondary effects in complementary metal–oxide–semiconductor technology limits its application in the ultra-nanoscale region. Circuit designers explore a new technology for the ultra-nanoscale region, which is the quantum-dot cellular automata (QCA). Low-energy dissipation, high speed, and area efficiency are the key features of the QCA technology. This research proposes a novel, low-complexity, QCA-based one-bit digital comparator circuit for the ultra-nanoscale region. The performance of the proposed comparator circuit is presented in detail in this paper and compared with that of existing designs. The proposed QCA structure for the comparator circuit only consists of 19 QCA cells with two clock phases. QCA Designer-E and QCA Pro tools are applied to estimate the total energy dissipation. The proposed comparator saves 24.00% QCA cells, 25.00% cell area, 37.50% layout cost, and 78.11% energy dissipation compared with the best reported similar design.     

Design and Optimization of Full Comparator Based on Quantum‐Dot Cellular Automata

Quantum‐dot cellular automata (QCA) is one of the few alternative computing platforms that has the potential to be a promising technology because of higher speed, smaller size, and lower power consumption in comparison with CMOS technology. This letter proposes an optimized full comparator for implementation in QCA. The proposed design is compared with previous works in terms of complexity, area, and delay. In comparison with the best previous full comparator, our design has 64% and 85% improvement in cell count and area, respectively. Also, it is implemented with only one clock cycle. The obtained results show that our full comparator is more efficient in terms of cell count, complexity, area, and delay compared to the previous designs. Therefore, this structure can be simply used in designing QCA‐based circuits.     

改进型QCA共面交叉电路的可靠性分析

针对量子元胞自动机(QCA)电路中电路单元复杂化能提高电路可靠性的假设,采用概率转移矩阵对一种改进后的QCA共面交叉电路单元及原始电路单元的可靠性进行对比分析,以检验复杂化设计能否提高电路可靠性,并利用四选一数据选择器进行深入研究以验证分析结果。仿真结果表明,该改进方案将共面交叉电路单元应用于单独运行及组合电路中分别使电路的可靠性降低了19.6%和0.84%。改进后的电路单元不但没有提高可靠性,反而由于电路结构的复杂化降低了其可靠性。     

Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design

The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges. The most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This issue is commonly referred to as the “layout = timing” problem. To circumvent the problem, a novel self-timed circuit design technique referred to as the Locally Synchronous, globally asynchronous design for QCA has been recently proposed. The proposed technique can significantly reduce the layout–timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design is be possible. Also, the proposed technique is more scalable in designing large-scale systems. Since a less number of cells is used, the overall area is smaller and the manufacturability is better. In this paper, numerous multi-bit adder designs are considered to demonstrate the layout efficiency and robustness of the proposed globally asynchronous QCA design technique.     

Single-Bit Comparator in Quantum-Dot Cellular Automata (QCA) Technology Using Novel QCA-XNOR Gates

To fill the continuous needs for faster processing elements with less power consumption causes large pressure on the complementary metal oxide semiconductor (CMOS) technology developers. The scaling scenario is not an option nowadays and other technologies need to be investigated. The quantum-dot cellular automata (QCA) technology is one of the important emerging nanotechnologies that have attracted much researchers’ attention in recent years. This technology has many interesting features, such as high speed, low power consumption, and small size. These features make it an appropriate alternative to the CMOS technique. This paper suggests three novel structures of XNOR gates in the QCA technology. The presented structures do not follow the conventional approaches to the logic gates design but depend on the inherent capabilities of the new technology. The proposed structures are used as the main building blocks for a single-bit comparator. The resulted circuits are simulated for the verification purpose and then compared with existing counterparts in the literature. The comparison results are encouraging to append the proposed structures to the library of QCA gates.     

Efficient design of parity preserving logic in quantum-dot cellular automata targeting enhanced scalability in testing

Design of parity preserving logic based on emerging nanotechnology is very limited due to present technological limitation in tackling its high error rate. In this work, Quantum-dot cellular automata (QCA), a potential alternative to CMOS, is investigated for designing easily testable logic circuit. A novel self-testable logic structure referred to as the testable-QCA (t-QCA), using parity preserving logic, is proposed. Design flexibility of t-QCA then evaluated through synthesis of standard functions. The programmability feature of t-QCA is utilized to implement an ALU, realizing six important functions. Although the parity preservation property of t-QCA enables concurrent detection of permanent as well as the transient faults, an augmented test logic circuit (TC) using QCA primitives has been introduced to cover the cell defects in nanotechnology. Experimental results establish the efficiency of the proposed design that outperforms the existing technologies in terms of design cost and test overhead. The achievement of 100% stuck-at fault coverage and the 100% fault coverage for single missing/additional cell defects in QCA layout of the t-QCA gate, address the reliability issues of QCA nano-circuit design.     

Using nano-scale QCA technology for designing fault-tolerant 2:1 multiplexer

Recently, Quantum-dot Cellular Automata (QCA) has appeared as a noteworthy substitution to CMOS technology. It contains ultra-high-velocity, efficient energy, low area for design circuits, one potential computational fabric for Nano computing systems, and integration density. On the other hand, fault-tolerant circuits promise reliability circuits by computation redundancy cells. This work targets to form two designs of fault-tolerant 2:1 multiplexer in the QCA framework. This proposed QCA multiplexer designs use cell redundancy on the wire, NOT gates, and majority gates. The coplanar structures for the proposed 2:1 QCA fault-tolerant multiplexers are provided and operated based on cell interactions. Four types of faults, cell misalignment, cell missing, cell displacement, and extra cell, are essential in analyzing the fault attributes. The proposed fault-tolerant multiplexers can attain 100% fault-tolerance while extra cell deficiencies or single missing exist in the layout of the QCA. The simulation outcomes reached by the software, QCA Designer 2.0.3, approve that the suggested multiplexers work correctly and can be utilized in QCA technology as a high-performance schematization. The outcomes show that the proposed construct outperforms any prior schematization.

     

Layout design of manufacturable quantum-dot cellular automata

Quantum-dot cellular automaton (QCA) is an emergent technology that is not hindered by quantum effects that limit the scaling of CMOS technology, but instead employs them to perform computation. However, this brings its own impediments, such as the influence of the thermodynamic effects. Beside that, QCA has to be coupled with CMOS circuitry of different size features to enable clocking. We discussed all these facts and devised a floorplan which would facilitate manufacturability. Based on it we developed the process of QCA layout design and defined the design rules that must be considered in order to ensure correct operation. These instructions enable the automatization of designing a QCA circuit layout.