Harmonic fold back reduction at the N‐path filters

In this paper, a method is proposed to reduce harmonic fold back (HFB) problem of N‐path filters, without increasing the input reference clock (f_CLK ) frequency. The HFB at the N‐path filter is analyzed, and simple expressions are extracted to model this problem. Using the results of the analysis, an M‐of‐N‐path filter has been proposed that behaves like an M × N‐path filter in terms of HFB problem; however, the f_CLK frequency of this structure is the same as an N‐path filter. To demonstrate the feasibility of the proposed idea, a 3‐of‐4‐path filter is designed, and its characteristics are compared with 4‐path and 12‐path filters by simulation. Impacts of different non‐idealities like clock‐phase error, mismatch, and parasitic capacitance are investigated. The transistor‐level implementation of this filter is performed in 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology. The simulation results show that the filter has the pass‐band gain of 17 dB, tuning range of 0.2–1.2 GHz, −3 dB bandwidth of 25 MHz, quality factor of 8–48, 18 dB out‐of‐band rejection, 16 dB rejection of the third harmonic of switching frequency (f_s ), and the noise figure of 4.35 dB (using ideal G_m cells) and 6.95 dB (for practical G_m cells). The strongest harmonic folding to the filter pass‐band occurs around 11f_s with the attenuation of 23.8 dB. Each G_m cell draws about 12.4 mA from 1.8 V supply, and the out‐of‐band IIP3 and P _{1 dB,CP} are 17 and 4 dBm, respectively. Copyright © 2016 John Wiley & Sons, Ltd.     

A simulation study of high‐order CMOS hyperbolic‐sine filters

This paper advances the field of externally linear–internally nonlinear (ELIN) filters by introducing a synthesis method that enables the design of high‐order class‐AB sinh filters by means of complementary metal–oxide semiconductor (CMOS) weak‐inversion sinh integrators comprising only one type of devices in their translinear loops. The proposed transistor‐level synthesis approach is demonstrated through the examples of (1) a biquadratic and (2) a fifth‐order filter, and their simulated performance is studied. The biquadratic filter achieves a dynamic range of 94 dB and has a tunable quality factor Q up to the value of 8, whereas its natural frequency can be tuned for four orders of magnitude. Its static power consumption amounts to 6.2 μW for Q = 1 and f_o = 2 kHz. The fifth‐order Chebyshev sinh CMOS filter with a cut‐off frequency of 100 Hz, a pass band ripple of 1 dB, and a power consumption of ~300 nW is compared head‐to‐head with its pseudo‐differential class‐AB CMOS log domain counterpart. The sinh filter achieves similar or better signal‐to‐noise ratio (SNR) and signal‐to‐noise‐plus‐distortion ratio (SNDR) performances with half the capacitor area but at the expense of higher power consumption from the same power supply level. All three presented filter topologies are novel. Cadence design framework simulations have been performed using the commercially available 0.35 µm AMS (austriamicrosystems) process parameters. Copyright © 2013 John Wiley & Sons, Ltd.     

Explicit design formulas for current‐mode leap‐frog OTA‐C filters and 300 MHz CMOS seventh‐order linear phase filter

The leap‐frog (LF) configuration is an important structure in analogue filter design. Voltage‐mode LF OTA‐C filters have recently been studied in the literature; however, general explicit formulas do not exist for current‐mode LF OTA‐C filters and there is also need for current‐mode LF‐based OTA‐C structures for realization of arbitrary transmission zeros. Three current‐mode OTA‐C structures are presented, including the basic LF structure and LF filters with an input distributor or an output summer. They can realize all‐pole characteristics and functions with arbitrary transmission zeros. Explicit design formulas are derived directly from these structures for the synthesis of, respectively, all‐pole and arbitrary zero filter characteristics of up to the sixth order. The filter structures are regular and the design formulas are straightforward to use. As an illustrative example, a 300 MHz seventh‐order linear phase low‐pass filter with zeros is presented. The filter is implemented using a fully differential linear operational transconductance amplifier (OTA) based on a source degeneration topology. Simulations in a standard TSMC 0.18µm CMOS process with 2.5 V power supply have shown that the cutoff frequency of the filter ranges from 260 to 320 MHz, group delay ripple is about 4.5% over the whole tuning range, noise of the filter is 420nA/√Hz, dynamic range is 66 dB and power consumption is 200 mW. Copyright © 2008 John Wiley & Sons, Ltd.     

A reconfigurable high ultimate rejection inductorless band‐pass filter by the use of N‐path passive mixers

In this paper, a band‐pass filter with a tunable bandwidth and the center frequency is introduced, which employs N‐path and N × M‐path passive mixer structures, for multiband multistandard wireless receivers. The center frequency of the proposed filter is tunable from 0.1 to 1 GHz, while its bandwidth is also adjustable from 6% to 34% of the center frequency at 100 MHz. The passband ripple is reduced by applying a Miller compensation technique, resulting in a worst‐case ripple of only 1.6 dB over the entire tuning range. An additional eight‐path filter is also utilized at the input of the circuit, which highly improves the out‐of‐band rejection of the filter as well as its out‐of‐band linearity. The noise figure and the input return loss are, respectively, better than 5 and 10 dB, and depending on the desired center frequency, the total power consumption of the proposed filter varies from 41 to 70 mW.     

A power‐area‐efficient, 3‐band, 2‐RX MIMO,TD‐LTE receiver with direct‐coupled ADC

In this work, a power‐area‐efficient, 3‐band, 2‐RX MIMO, and TD‐LTE (backward compatible with the HSPA+, HSUPA, HSDPA, and TD‐SCDMA) CMOS receiver is presented and implemented in 0.13‐μm CMOS technology. The continuous‐time delta‐sigma A/D converters (CT ?Σ ADCs) are directly coupled to the outputs of the transimpedance amplifiers, eliminating the need of analog anti‐aliasing filters between RX front‐end and ADCs in conventional structures. The strong adjacent channel interference without low‐pass filter attenuation is handled by proper gain control. A low‐power small‐area solution for excess loop delay compensation is implemented in the CT ?Σ ADC. At 20 MHz bandwidth, the CT ?Σ ADC achieves 66 dB dynamic range and 3.5 dB RX chip noise figure is measured. A maximum of 2.4 dB signal‐to‐noise ratio degradation is measured in all the adjacent channel selectivity (ACS) and blocking tests, demonstrating the effectiveness of the strategy against the low‐pass filter removal from the conventional architecture. The receiver dissipates a maximum of 171 mW at 2‐RX MIMO mode. To our best knowledge, it is the first research paper on the design of fully integrated commercial TD‐LTE receiver. Copyright © 2014 John Wiley & Sons, Ltd.     

Voltage mode and current mode Tow Thomas bi‐quadratic filters using inverting CCII

A voltage mode Tow Thomas bi‐quadratic filter using the inverting second‐generation current conveyor (ICCII) is given. The filter has high input impedance, employs two grounded capacitors, and has independent control on Q, independent control on the band‐pass and low‐pass response gain. Three alternative current mode filters are generated from the voltage mode circuit. The three circuits have zero input impedance, employ grounded capacitors and have independent control on Q. Two of the circuits have also all resistors grounded and the other uses only ICCII?and has only one floating resistor. Copyright © 2007 John Wiley & Sons, Ltd.     

Analytical synthesis of voltage‐mode even/odd‐nth‐order differential difference current conveyor and fully differential current conveyor II‐grounded resistor and capacitor universal filter structures

A complete definition of an odd/even‐nth‐order notch or band‐reject filter transfer function is presented. Based on the differences between the input voltage and (i) an nth‐order high‐pass; (ii) a traditional nth‐order notch; and (iii) an nth‐order all‐pass filtering transfer function, a systematic method has been proposed to derive a universal filter structure that can realize voltage‐mode odd/even‐nth‐order low‐pass, band‐pass, high‐pass, all‐pass and traditional notch filters. The intrinsic capability of voltage‐mode addition and subtraction of the two active elements, differential difference current conveyors and fully differential current conveyors, is used to advantage in the aforementioned synthesis procedure. Based upon the definition of an nth‐order notch or band‐reject filter transfer function proposed in this paper, the aforementioned universal one has been further extended to the newly defined nth‐order band rejection filter. The voltage and current tracking errors of the two active elements are compensated by varying the resistances of the proposed filter. Filtering feasibility, stability, component sensitivities, linear and dynamic ranges, power consumption, and noise are simulated using H‐Spice with 0.35 µm process. Compared to some of the recently reported universal biquads, the new one is shown to enjoy the lowest component sensitivities and the best output accuracy for all‐pass signals. Moreover, Monte Carlo and two‐tone tests for intermodulation linearity simulations are also investigated. Copyright © 2014 John Wiley & Sons, Ltd.     

Implementation of an in‐field CMOS frequency division multiplexer for 9.4 T magnetic resonance applications

This paper introduces the implementation of an application‐specific complementary metal oxide semiconductor frequency division multiplexer as a novel solution to interface magnetic resonance (MR) phased arrays of micro‐detectors to an image‐processing unit, thus reducing the complexity and space issues associated with MR detector arrays. The frequency multiplexer, in a compact 3 × 4 mm silicon die, is designed to operate at 400 MHz, which is the Larmor frequency of ¹H protons in a 9.4‐T MR imaging system. The system implements eight channels, where each channel consists of a low‐noise amplifier, a frequency mixer, and a band‐pass filter. The maximum gain of an individual channel after the band‐pass filter stage is 38 dB. The suppression of the local oscillator ranges from 40 to ?51 dB, and the maximum coupling between channels is ?39 dB. The input dynamic range of an individual channel is 8 mV. Each channel consumes 54 mA from a 3.3‐V source. The chip operates without errors within a high 9.4‐T magnetic field. Copyright © 2014 John Wiley & Sons, Ltd.     

A single‐bit continuous‐time delta‐sigma modulator using clock‐jitter and inter‐symbol‐interference suppression technique

This paper presents a technique for mitigating two well‐known DAC non‐idealities in continuous‐time delta‐sigma modulators (CTDSMs), particularly in wide‐band and low over‐sampling‐ratio (OSR) cases. This technique employs a special digital‐to‐analog convertor (DAC) waveform, called modified return‐to‐zero (MRZ), to reduce the time uncertainty effect because of the jittered clock at the sampling time instances and eliminate the effect of inter‐symbol‐interference (ISI) which degrades the modulator performance, especially when non‐return‐to‐zero (NRZ) DAC waveform is chosen in the modulator design. A third‐order single‐bit CTDSM is designed based on the proposed technique and step‐by‐step design procedure at circuit and system levels, considering clock jitter and ISI, is explained. Circuit simulations in 180‐nm CMOS technology show that in the presence of circuit non‐idealities which generate jitter and asymmetrical rise and fall times in the DAC current pulse, signal‐to‐noise‐distortion‐ratio (SNDR) of the proposed modulator is higher than the conventional modulator with NRZ waveform by about 10 dB. In these simulations, clock jitter standard deviation is 0.3% of the sampling period (T_S) and the difference between fall/rise times in the DAC current pulse is 4%T_S. Simulated at 600‐MHz sampling frequency (f_S) with an oversampling ratio (OSR) of 24, SNDR figure of merit (FOM_SNDR) of the proposed modulator in 180‐nm CMOS is 300 fj/conversion. Copyright © 2016 John Wiley & Sons, Ltd.     

Balanced Gm‐C filters with improved linearity and power efficiency

A novel G_m‐C filter design technique is presented. It is based on floating‐gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G_m‐C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all‐pole G_m‐C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low‐power second‐order Butterworth G_m‐C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5‐µm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. Copyright © 2014 John Wiley & Sons, Ltd.     

A low‐power,area‐efficient multichannel receiver for micro MRI

A new integrated, low‐noise, low‐power, and area‐efficient multichannel receiver for magnetic resonance imaging (MRI) is described. The proposed receiver presents an alternative technique to overcome the use of multiple receiver front‐ends in parallel MRI. The receiver consists of three main stages: low‐noise pre‐amplifier, quadrature down‐converter, and a band pass filter (BPF). These components are used to receive the nuclear magnetic resonance signals from a 3 × 3 array of micro coils. These signals are combined using frequency domain multiplexing (FDM) method in the pre‐amplifier and BPF stages, then amplified and filtered to remove any out‐of‐band noise before providing it to an analog‐to‐digital converter at the low intermediate frequency stage. The receiver is designed using a 90 nm CMOS technology to operate at the main B₀ magnetic field of 9.4 T, which corresponds to 400 MHz. The receiver has an input referred noise voltage of 1.1 nV/√Hz, a total voltage gain of 87 dB, a power consumption of 69 mA from a 1 V supply voltage, and an area of 305 µm × 530 µm including the reference current and bias voltage circuits. Copyright © 2013 John Wiley & Sons, Ltd.     

Structure generation and performance comparison of elliptic Gm‐C filters

Starting from a set of matrices describing a general G_m‐C filter topology, a procedure is developed for generating structures of lowpass filters. As the matrices and the filter topologies have a one‐to‐one correspondence, an algebraic method is used to identify filter topologies with desired properties, here, transfer functions with finite jω‐axis transmission zeros, specifically elliptic filters. Sensitivity expressions for these structures are derived and a performance comparison based on a set of chosen criteria is made. For a specified elliptic transfer function, filters with only grounded capacitors and those containing also floating capacitors emerge as alternative realizations, as are filters with a single input and those with distributed inputs. For third‐order functions, a detailed comparison is performed of leapfrog (LF) and inverse follow‐the‐leader‐feedback (IFLF), the most popular special cases, and of topologies that have also floating capacitors (LF_f, IFLF_f), as well as of a novel configuration that uses also distributed inputs (DI_f) and leads to a reduced element count. Design guidelines and restrictions are given, which follow from the derived results with focus on the circuits' sensitivity performance and other properties important for IC implementation. Copyright © 2004 John Wiley & Sons, Ltd.     

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Emerging wide‐band communications and spectrum‐sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far‐field beam width. Realizing existing phased‐array technology on a digital scale is computationally intensive. Moreover, digitizing wide‐band signals at Nyquist rate requires complex high‐speed analog‐to‐digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low‐complexity alternative proposed in this paper is the use of radio‐frequency (RF) channelizers for spectrum division followed by sub‐sampling of the RF sub‐bands, which results in extensive reduction of the necessary ADC operative frequency. The RF‐channelized array signals are directionally filtered using 2‐D digital filterbanks. This mixed‐domain RF/digital aperture array allows sub‐sampling, without utilizing multi‐rate 2‐D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14–19 dB of rejection of wide‐band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single‐phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65‐nm Xilinx field‐programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area‐time complexity, and dynamic power consumption for a 45‐nm CMOS circuit operating at B _DC = 1.1 V, are presented. Copyright © 2016 John Wiley & Sons, Ltd.     

Programmable feedforward linearized CMOS OTA for fully differential continuous‐time filter design

In this paper, a feedforward linearization method for programmable CMOS operational transconductance amplifier (OTA) is described. The proposed circuit technique is developed using simple source‐coupled differential pair transconductors, a feedback‐loop amplifier for self‐adjusting transcoductance (g_m) and a linear reference resistor (R). As a result, an efficient linearization of a transfer characteristic of the OTA is obtained. SPICE simulations show that for 0.35µm AMS CMOS process with a single +3V power supply, total harmonic distortion at 1 V_pp and temperature range from ?30 to +90°C is less than ?49.3 dB in comparison with ?35.8 dB without linearization. Moreover, the input voltage range of linear operation is increased. Power consumption of the linearized OTA circuit is 0.86 mW. Finally, the OTA is used to design a third‐order elliptic low‐pass filter in high‐frequency range. The cut‐off frequency of the operational transconductance amplifier‐capacitor (OTA‐C) filter is tunable in the range of 322.6 kHz–10 MHz using the feedforward linearized OTAs with the digitally programmable current mirrors. Copyright © 2009 John Wiley & Sons, Ltd.     

A front‐end receiver with a dual cross‐coupling technique for MICS applications

This paper presents a front‐end receiver with a dual cross‐couple technique for Medical Implant Communication Services M applications, using a standard complementary metal‐oxide semiconductor process. A lower‐power design is achieved using a resistive feedback, g_m‐boosting technique along with a current reuse topology in the receiver's transconductance stage. In addition, a dual cross‐coupling configuration applied at the input stage increases overall gain performance and reduces power consumption. The measured power dissipation of the low‐noise amplifier is only 0.51 mW. The conversion gain of the receiver is 19.74 dB, while the radio frequency and local oscillator frequencies are respectively 403.5 and 393.5 MHz, and the LO power is 0 dBm. The chip exhibits excellent isolation below −70 dB from LO to intermediate frequency and LO to radio frequency. Copyright © 2016 John Wiley & Sons, Ltd.     

Analytical synthesis and comparison of voltage‐mode Nth‐order OTA‐C universal filter structures

Complementary single‐ended‐input operational transconductance amplifier (OTA)‐based filter structures are introduced in this paper. Through two analytical synthesis methods and two transformations, one of which is to convert a differential‐input OTA to two complementary single‐ended‐input OTAs, and the other to convert a single‐ended‐input OTA and grounded capacitor‐based one to a fully differential OTA‐based one, four distinct kinds of voltage‐mode nth‐order OTA‐C universal filter structures are proposed. TSMC H‐Spice simulations with 0.35µm process validate that the new complementary single‐ended‐input OTA‐based one holds the superiority in output precision, dynamic and linear ranges than other kinds of filter structures. Moreover, the new voltage‐mode band‐pass, band‐reject and all‐pass (except the fully differential one) biquad structures, all enjoy very low sensitivities. Both direct sixth‐order universal filter structures and their equivalent three biquad stage ones are also simulated and validated that the former is not absolutely larger in sensitivity than the latter. Finally, a very sharp increment of the transconductance of an OTA is discovered as the operating frequency is very high and leads to a modified frequency‐dependent transconductance. Copyright © 2010 John Wiley & Sons, Ltd.     

IC‐constrained optimization of continuous‐time Gm–C filters

This paper presents an automated synthesis procedure for integrated continuous‐time fully‐differential G_m?C filters. Such procedure builds up on a general extended state‐space system representation which provides simple matrix algebra mechanisms to evaluate the noise and distortion performances of filters, as well as, the effect of amplitude and impedance scaling operations. The proposed technique not only addresses the dynamic range optimization under power dissipation constraints, but also accounts for other relevant integrated circuit related features, such as transconductor decomposition in unitary instances, spread of capacitances and estimated area occupation, among other characteristics. The proposed approach, implemented in the MATLAB^® framework, can be also used as an exploratory tool to compare different circuit implementations for a given set of filter specifications. Copyright © 2010 John Wiley & Sons, Ltd.     

Low‐power,low‐area preamplifier for ultra high‐speed multi‐channel optical communication system

A novel circuit technique was applied to the design of a preamplifier for ultra high‐speed short‐distance parallel optical communication system in standard 180‐nm CMOS technology. This circuit is featured by low power, low area as well as high gain bandwidth product, and suited for applications in low‐cost process. The restraint on voltage headroom as bottleneck in traditionally adopted regulated cascode configuration has been fundamentally analyzed and lifted by feed‐forward common gate stage to achieve high gain bandwidth product under limited f_T and strict power restriction. Complex poles were carefully assigned to further attain bandwidth extension without sacrifice on power, noise, and chip area. No additional peaking techniques and subsequent gain‐boosting stages are adopted, which makes the design simple and favorable in low‐cost high‐density multi‐channel optical communication system. The preamplifier provides a trans‐impedance gain of up to 52 dBΩ and a 3‐dB bandwidth of 8.4 GHz. Operating under a 1.8‐V supply, the power dissipation is 8 mW, and the chip area is only 0.075×0.08 mm. The measured average input‐referred noise–current spectral density is . Copyright © 2011 John Wiley & Sons, Ltd.     

Design of a 1‐GSample/s 9‐b double sampling track‐and‐hold amplifier in BiCMOS technology

This paper gives a detail presentation of a fully pseudo‐differential open‐loop BiCMOS track‐and‐hold amplifier (THA) for 9‐b operation up to 1 GSample/s. The proposed THA not only uses a double sampling technique to increase the achievable sampling frequency by a factor of two, but also employs a linearization technique to reduce the gain dependence of the THA input stage upon the input level. Moreover, timing mismatch between the clock signals of the two interleaved paths is minimized by means of a timing mismatch insensitive clock generator controlled by a common master sampling clock. The post‐layout simulation results using TSMC 75 GHz f_T, 0.35‐µm SiGe BiCMOS technology show that the proposed architecture achieve a signal to noise and distortion ratio of 53.92 dB, equivalent to the effective number of bits of 8.66‐b for 58.11 MHz input frequency at 1 GSample/s. The power dissipation of the whole THA is 161.1 mW. Copyright © 2012 John Wiley & Sons, Ltd.