0.5‐V bulk‐driven differential amplifier

A new 0.5‐V fully differential amplifier is proposed in this article. The structure incorporates a differential bulk‐driven voltage follower with conventional gate‐driven amplification stages. The bulk‐driven voltage follower presents differential gain equal to unity while suppressing the input common‐mode voltage. The amplifier operates at a supply voltage of less than 0.5 V, performing input transconductance almost equal to a gate transconductance and relatively high voltage gain without the need for gain boosting. The circuit was designed and simulated using a standard 0.18‐µm CMOS n‐well process. The low‐frequency gain of the amplifier was 56 dB, the unity gain bandwidth was approximately 3.2 MHz, the spot noise was 100 nV/√Hz at 100 kHz and the current consumption was 90 μΑ. Copyright © 2012 John Wiley & Sons, Ltd.     

Analysis and implementation of a high‐efficiency zero‐voltage‐zero‐current‐switching DC–DC converter

A high‐efficiency zero‐voltage‐zero‐current‐switching DC–DC converter with ripple‐free input current is presented. In the presented converter, the ripple‐free boost cell provides ripple‐free input current and zero‐voltage switching of power switches. The resonant flyback cell provides zero‐voltage switching of power switches and zero‐current switching of the output diode. Also, it has a simple output stage. The proposed converter achieves high efficiency because of the reduction of the switching losses of the power switches and the output diode. Detailed analysis and design of the proposed converter are carried out. A prototype of the proposed converter is developed and its experimental results are presented for validation. Copyright © 2011 John Wiley & Sons, Ltd.     

Low‐voltage bulk‐driven input stage with improved transconductance

A low‐voltage input stage constructed from bulk‐driven PMOS transistors is proposed in this paper. It is based on a partial positive feedback and offers significant improvement of both input transconductance and noise performance compared with those achieved by the corresponding already published bulk‐driven structures. The proposed input stage offers also extended input common‐mode range under low supply voltage in relevant to a gate‐driven differential pair. A differential amplifier based on the proposed input stage is also designed, which includes an auxiliary amplifier for the output common‐mode voltage stabilization and a latch‐up protection circuitry. Both input stage and amplifier circuits were implemented with 1 V supply voltage using standard 0.35µm CMOS process, and their performance evaluation gave very promising results. Copyright © 2010 John Wiley & Sons, Ltd.     

A single‐stage LED streetlight driver with PFC and digital PWM dimming capability

This paper proposes a single‐stage light‐emitting diode (LED) driver that offers power‐factor correction and digital pulse–width modulation (PWM) dimming capability for streetlight applications. The presented LED streetlight driver integrates an alternating current–direct current (AC–DC) converter with coupled inductors and a half‐bridge‐type LLC DC–DC resonant converter into a single‐stage circuit topology. The sub‐circuit of the AC–DC converter with coupled inductors is designed to be operated in discontinuous‐conduction mode for achieving input‐current shaping. Zero‐voltage switching of two active power switches and zero‐current switching of two output‐rectifier diodes in the presented LED driver decrease the switching losses; thus, the circuit efficiency is increased. A prototype driver for powering a 144‐W‐rated LED streetlight module with input utility‐line voltages ranging from 100 to 120 V is implemented and tested. The proposed streetlight driver features cost‐effectiveness, high circuit efficiency, high power factor, low levels of input‐current harmonics, and a digital PWM dimming capability ranging from 20% to 100% output rated LED power, which is fulfilled by a micro‐controller. Satisfying experimental results, including dimming tests, verify the feasibility of the proposed LED streetlight driver. Copyright © 2016 John Wiley & Sons, Ltd.     

Hybrid DC–DC converter with high efficiency,wide ZVS range,and less output inductance

In this paper, a new soft switching direct current (DC)–DC converter with low circulating current, wide zero voltage switching range, and reduced output inductor is presented for electric vehicle or plug‐in hybrid electric vehicle battery charger application. The proposed high‐frequency link DC–DC converter includes two resonant circuits and one full‐bridge phase‐shift pulse‐width modulation circuit with shared power switches in leading and lagging legs. Series resonant converters are operated at fixed switching frequency to extend the zero voltage switching range of power switches. Passive snubber circuit using one clamp capacitor and two rectifier diodes at the secondary side is adopted to reduce the primary current of full‐bridge converter to zero during the freewheeling interval. Hence, the circulating current on the primary side is eliminated in the proposed converter. In the same time, the voltage across the output inductor is also decreased so that the output inductance can be reduced compared with the output inductance in conventional full‐bridge converter. Finally, experiments are presented for a 1.33‐kW prototype circuit converting 380 V input to an output voltage of 300–420 V/3.5 A for battery charger applications. Copyright © 2015 John Wiley & Sons, Ltd.     

Analysis and design of a two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers

A new two‐transformer active‐clamping forward converter with parallel‐connected current doubler rectifiers (CDRs) is proposed in this paper. The presented DC–DC converter is mainly composed of two active‐clamping forward converters with secondary CDRs. Only two switches are required and each one is the auxiliary switch for the other. The circuit complexity and cost are thus reduced. The leakage inductance of the transformer or an additional resonant inductance is employed to achieve zero‐voltage‐switching (ZVS) during the dead times. Two CDRs at the secondary side are connected in parallel to reduce the current stresses of the secondary windings and the ripple current at the output side. Accordingly, the smaller output chokes and capacitors decrease the converter volume and increase the power density. Detailed analysis and design of the presented two‐transformer active‐clamping forward converter are described. Experimental results are recorded for a prototype converter with a DC input voltage of 130??180V, an output voltage of 5 V and an output current of 40 A, operating at a switching frequency of 100 kHz. Copyright © 2010 John Wiley & Sons, Ltd.     

Power‐efficient analog design based on the class AB super source follower

A class AB version of the conventional super source follower (SSF) is described. The circuit greatly increases slew rate (SR) and current efficiency, maintaining the low distortion and low output resistance of the SSF. Class AB operation is achieved without extra power dissipation or supply requirements, and without bandwidth or noise degradation. The circuit can advantageously replace the SSF in a wide variety of analog systems, opening a new research line in analog design. To illustrate the widespread application of this cell, a class AB differential unity‐gain buffer, a class AB differential current mirror and two class AB differential transconductors are designed, fabricated in a 0.5µm CMOS technology and tested. Measurement results using a dual supply of ±1.65V show that the proposed class AB version of the SSF improves SR by a factor 21.5 and increases bandwidth by 10%, keeping noise level, input range, power consumption, and supply requirements unaltered. The fabricated class AB current mirror features a THD at 100 kHz of ? 62dB for signal currents 20 times larger than the bias current. The fabricated transconductors feature an IM3 at 1 MHz of ? 56.6dB for output currents more than 13 times larger than the bias currents. Copyright © 2011 John Wiley & Sons, Ltd.     

Design and analysis of power‐CMOS‐gate‐based switched‐capacitor DC–DC converter with step‐down and step‐up modes

A unified multi‐stage power‐CMOS‐transmission‐gate‐based quasi‐switched‐capacitor (QSC) DC–DC converter is proposed to integrate both step‐down and step‐up modes all in one circuit configuration for low‐power applications. In this paper, by using power‐CMOS‐transmission‐gate as a bi‐directional switch, the various topologies for step‐down and step‐up modes can be integrated in the same circuit configuration, and the configuration does not require any inductive elements, so the IC fabrication is promising for realization. In addition, both large‐signal state‐space equation and small‐signal transfer function are derived by state‐space averaging technique, and expressed all in one unified formulation for both modes. Based on the unified model, it is all presented for control design and theoretical analysis, including steady‐state output and power, power efficiency, maximum voltage conversion ratio, maximum power efficiency, maximum output power, output voltage ripple percentage, capacitance selection, closed‐loop control and stability, etc. Finally, a multi‐stage QSC DC–DC converter with step‐down and step‐up modes is made in circuit layout by PSPICE tool, and some topics are discussed, including (1) voltage conversion, output ripple percentage, and power efficiency, (2) output robustness against source noises and (3) regulation capability of converter with loading variation. The simulated results are illustrated to show the efficacy of the unified configuration proposed. Copyright © 2003 John Wiley & Sons, Ltd.     

A novel three‐phase converter using a three‐phase series chopper

This paper proposes a novel three‐phase converter using a three‐phase series chopper. The proposed circuit is composed of three switching devices, three‐phase diode bridge, input reactors, and LC low‐pass filter. In the conventional circuit, which combines three‐phase diode bridge and boost voltage chopper, to obtain sinusoidal input current the output voltage must be two or three times larger than the maximum input line voltage. However, in the proposed circuit, the input current can be controlled to be sinusoidal also when the output voltage is the same as the maximum input line voltage. This can be achieved because in the proposed circuit the discharging current of the reactors does not flow through the voltage source. The control method of the proposed circuit is as simple as that of the conventional circuit since all three switching devices are simultaneously turned on and off. This paper discusses the theoretical analysis and the design of the proposed circuit. In addition, simulation and experimental results are reported. The proposed circuit has obtained a 93% efficiency, and 99.7% at 1.3kW load as the input power factor. © 2000 Scripta Technica, Electr Eng Jpn, 132(4): 79–88, 2000     

An interleaved high step‐up DC‐DC converter with double boost paths

This paper proposed a novel high step‐up converter with double boost paths. The circuit uses two switches and one double‐path voltage multiplier cell to own the double boost and interleaved effects simultaneously. The voltage gain ratio of the proposed DC‐DC converter can be three times the ratio of the conventional boost converter such that the voltage stress of the switch can be lower. The high step‐up performance is in accordance with only one double‐path voltage multiplier cell. Therefore, the number of diodes and capacitors in the proposed converter can be reduced. Furthermore, the interleaved property of the proposed circuit can reduce the losses in the rectifier diode and capacitor. The prototype circuit with 24‐V input voltage, 250‐V output voltage, and 150‐W output power is experimentally realized to verify the validity and effectiveness of the proposed converter. Copyright © 2014 John Wiley & Sons, Ltd.     

A ZVS‐ZCS phase shift full bridge DC‐DC converter with secondary‐side control for battery charging applications

The output power requirement of battery charging circuits can vary in a wide range, hence making the use of conventional phase shift full bridge DC‐DC converters infeasible because of poor light load efficiency. In this paper, a new ZVS‐ZCS phase shift full bridge topology with secondary‐side active control has been presented for battery charging applications. The proposed circuit uses 2 extra switches in series with the secondary‐side rectifier diodes, operating with phase shift PWM. With the assistance of transformer's magnetizing inductance, the proposed converter maintains zero voltage switching (ZVS) of the primary‐side switches over the entire load range. The secondary‐side switches regulate the output voltage/current and perform zero current switching (ZCS) independent of the amount of load current. The proposed converter exhibits a significantly better light load efficiency as compared with the conventional phase shift full bridge DC‐DC converter. The performance of the proposed converter has been analyzed on a 1‐kW hardware prototype, and experimental results have been included.     

Low‐voltage high‐performance current mirrors: Application to linear voltage‐to‐current converter

Current mirror is one of the basic building blocks of analog VLSI systems. For high‐performance analog circuit applications, the accuracy and bandwidth are the most important parameters to determine the performance of the current mirror. This paper presents an efficient implementation of a CMOS current mirror suitable for low‐voltage applications. This circuit combines a shunt input feedback, a regulated cascade output and a differential amplifier to achieve low input resistance, high accuracy and high output resistance. A comparison of several architectures of this scheme based on different architectures of the amplifier is presented. The comparison includes: input impedance, output impedance, accuracy, frequency response and settling time response. These circuits are validated with simulation in 0.18µm CMOS TSMC of MOSIS. In this paper, a linear voltage to current converter, based on the adapted current mirror, is proposed. Its static and dynamic behaviour is presented and validated with the same technology. Copyright © 2009 John Wiley & Sons, Ltd.     

A new efficient SC integrator scheme for high‐speed low‐power applications

A new solution to implement efficient switched‐capacitor (SC) integrators is presented. In the proposed scheme, voltage buffers are opportunely introduced in order to prevent direct connection between the output and the capacitive feedback network of the circuit that characterizes classical SC integrator topologies during the charge transfer phase. Design guidelines to optimize the settling performances of the proposed circuit are also given. To demonstrate the possible advantages of the new solution, the proposed integrator is designed in a commercial 0.35?µm CMOS technology. It is shown that compared with classical SC integrator topologies, the proposed configuration allows a significant improvement of the integrator speed to be achieved for a given power budget. Copyright © 2010 John Wiley & Sons, Ltd.     

Design of a dual‐input SC DC–DC converter realizing negative outputs

Aimed at a back‐lighting application, a dual‐input switched‐capacitor (SC) DC–DC converter with battery charge process is proposed in this paper. The proposed converter can realize −1/N× (N = 2,3,…) step‐down conversion as well as (N + 1)/N× step‐up conversion. By converting clean energy such as solar energy, the proposed dual‐input converter not only drives light‐emitting diodes (LEDs) but also recharges the battery, although conventional single‐input converter only consumes battery energy. In the proposed converter, the −1/N× stepped‐down voltage is generated to drive the LED's cathode when the input voltage is insufficient to drive a 1× transfer mode. Furthermore, unlike conventional converters, the battery is charged by the (N + 1)/N× stepped‐up voltage when the LED back light is in standby mode. Hence, the proposed converter can realize long battery run time. The validity of circuit design is confirmed by theoretical analyses, simulations, and experiments. The derived theoretical formulas will be helpful to estimate circuit characteristics, because the theoretical results correspond well with the simulation program with integrated circuit emphasis (SPICE) simulation results. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.     

A mixed‐mode KHN‐biquad using DVCC and grounded passive elements suitable for direct cascading

In this paper a mixed‐mode (input and output signals can be current or voltage) Kerwin–Huelsman–Newcomb (KHN) biquad with low/high input impedance and high/low output impedance depending on the type of the corresponding signal (current/voltage) is presented. The circuit is constructed using three differential voltage current conveyors (DVCCs), two grounded capacitors and three grounded resistors. The circuit simultaneously provides bandpass (BP), highpass (HP) and lowpass (LP) responses when the output is current and notch, BP and LP responses when the output is voltage. The notch and allpass responses can be obtained by connecting appropriate output currents directly without using additional active elements. Because of the low input and high output impedance of the circuit for current signals and the high input and low output impedance for voltage signals, it can be used in cascade for realizing higher‐order filters. SPICE simulation results are given to verify the theoretical analysis. Copyright © 2008 John Wiley & Sons, Ltd.     

0.5‐V bulk‐driven OTA and its applications

A new 0.5‐V bulk‐driven operational transconductance amplifier (OTA), designed in 50 nm CMOS technology, is presented in the paper. The circuit is characterized by improved linearity and dynamic range obtained for MOS devices operating in moderate inversion region. Some basic applications of the OTA such as a voltage integrator and a second‐order low‐pass filter have also been described. The filter is compared to other low‐voltage filters presented in the literature. Copyright © 2013 John Wiley & Sons, Ltd.     

A soft‐switching high step‐up DC‐DC converter with a single magnetic component

A soft‐switching high step‐up DC‐DC converter with a single magnetic component is presented in this paper. The proposed converter can provide high voltage gain with a relatively low turn ratio of a transformer. Voltage doubler structure is selected for the output stage. Due to this structure, the voltage gain can be increased, and the voltage stresses of output diodes are clamped as the output voltage. Moreover, the output diode currents are controlled by a leakage inductance of a transformer, and the reverse‐recovery loss of the output diodes is significantly reduced. Two power switches in the proposed converter can operate with soft‐switching due to the reflected secondary current. The voltages across the power switches are confined to the clamping capacitor voltage. Steady‐state analysis, simulation, and experimental results for the proposed converter are presented to validate the feasibility and the performance of the proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.     

A three‐phase constant‐current source using an immittance converter

The term immittance converter refers to an impedance–admittance converter. The immittance converter has an input impedance that is proportional to the admittance of the load connected across output terminals. In this converter, the output current is proportional to the input voltage and the input current is proportional to the output voltage. Consequently, it converts a constant‐voltage source into a constant‐current source and a constant‐current source into a constant‐voltage source. It is well known that the quarter wavelength transmission line shows immittance conversion characteristics. However, it has a very long line length for the switching frequency, and is not suitable for power electronics applications. We thus proposed immittance converters that consist of lumped elements L, C and show improved immittance conversion characteristics at a resonant frequency. A three‐phase constant‐current source is proposed in this paper. It is possible to realize this by a simple circuit using an immittance converter. In this paper, circuit operation, characteristic equations, and results of simulation are described. © 2005 Wiley Periodicals, Inc. Electr Eng Jpn, 151(4): 47–54, 2005; Published online in Wiley InterScience ( www.interscience.wiley.com ). DOI 10.1002/eej.20078     

Implementation of parallel zero‐voltage switching converter with series‐connected transformers

This paper presents a parallel zero‐voltage switching (ZVS) DC–DC converter with series‐connected transformers. In order to increase output power, two transformers connected in series are used in the proposed converter. Two buck‐type converters connected in parallel have the same switching devices. The primary windings of series‐connected transformers can achieve the balanced secondary winding currents. The current doubler rectifiers with ripple current cancellation are connected in parallel at the output side to reduce the current stress of the secondary winding. Thus, the current ripple on the output capacitor is reduced, and the size of the output choke and output capacitor are reduced. Only two switches are used in the proposed circuit instead of four switches in the conventional parallel ZVS converter to achieve ZVS and output current sharing. Therefore, the proposed converter has less power switches. The ZVS turn‐on is implemented during the commutation stage of two complementary switches such that the switching losses and thermal stresses on the semiconductors are reduced. Experimental results for a 528‐W (48 V/11 A) prototype are presented to prove the theoretical analysis and circuit performance. Copyright © 2011 John Wiley & Sons, Ltd.     

Ultra‐low voltage fractional‐order circuits using current mirrors

Fractional‐order blocks, including differentiators, lossy and lossless integrators as well as filters of order 1 + a (0 < a < 1), are presented in this paper. The proposed topologies offer the benefit of ultra low‐voltage operation; in addition, reduced circuit complexity is achieved compared to the corresponding companding schemes, which have been already introduced in the literature. The ultra‐low voltage operation is performed through the employment of metal oxide semiconductor transistors biased in the subthreshold region. The reduction of circuit complexity is achieved through the utilization of current mirrors as active elements for realizing the required building blocks. The performance of the proposed fractional‐order circuits has been evaluated through the Analog Design Environment of the Cadence software and the design kit provided by the Taiwan Semiconductor Manufacturing Company (TSMC) 180 nm complementary metal oxide semiconductor process. Copyright © 2015 John Wiley & Sons, Ltd.