声表面波器件用的表面安装封装管壳

主要阐述某种声表面波(SAW)器件用的表面安装型封装管壳的结构设计过程，以及适应大批量生产的工艺改进及创新。     

声表面波器件的封装技术及其发展

目前各种声表面波器件的工作频率涵盖30MHz到3000MHz的频率范围,其封装形式主要有塑料封装、金属封装(如F11、TO-39)和sMD封装。在本文中,作者对声表面波器件的这三种主要封装形式对声表面波器件电传输性的影响作了系统的实验研究与分析,并论述了声表面波器件在封装方面的现状及其发展趋势。     

SAW滤波器WLP封装中腔体抗模压塌陷研究

通过对声表面波滤波器晶圆级封装结构的探讨,针对在模组封装时器件塌陷成因进行了有限元仿真模型研究,模拟了不同模压量对器件中腔体最大的塌陷量位置。经过实验验证,提出了一种新的金属加强结构,在3 MPa较高模压量时塌陷量几乎为0,解决了声表面波滤波器晶圆级封装芯片灌封压力导致的塌陷问题,降低了器件及模组失效风险,是一种声表面波滤波器晶圆级封装的新技术。     

基于LTCC技术的表贴式封装SAWF

提出一种基于低温共烧结陶瓷(LTCC)技术的封装形式,将声表面波滤波器(SAWF)做成表面贴装器件(SMD).该封装结构可实现SAWF基片表面上方2个换能器间的隔离,提高SAWF的阻带抑制,其器件适合于高密度组装,进而可演变成SAWF集成在电路模块的LTCC多层电路板上,即直接将SAWF的裸基片掩埋在LTCC多层电路板内,实现器件—电路—体化.     

声表面波器件小型化技术发展概述

以EPCOS生产的声表面波(SAW)芯片级封装和晶圆级封装为例,介绍了声表面波器件小型化发展的趋势.着重介绍了声表器件芯片级封装技术发展的各个阶段器件的结构特点.详述采用倒装、贴膜和晶圆键合技术将声表面波器件的尺寸减至最小及后续声表面波器件组件化封装的趋势.     

BGA的回流焊温度曲线的设定

在电子发展的今天,BGA封装器件的应用越来越广,虽然用传统的SMT进行BGA贴装时,工艺过程不需要改变,但由于BGA的封装与正常的表面安装器件（SMD）不同,因此,BGA在实际应用中也有一些特殊性。     

钉头法倒装焊技术在声表面波器件生产中的应用

简单介绍了集成电路采用的封装形式,对钉头法倒装焊技术在声表面波器件中的应用和发展趋势进行了简单分析。详细介绍了倒装焊技术在声表面波器件生产中的应用方法,对比了线焊技术和倒装焊技术的差异,介绍了倒装焊技术的优点。简单介绍了倒装焊技术的整体流程,对生产过程中的每道关键工序做了详细的描述,并对产品后期的失效形式做了简要分析。     

双面贴装电路板上BGA焊点的潜在失效机理

采用双面贴装回流焊工艺在FR4基板表面贴装Sn3.0Ag0.5Cu(SnAgCn)无铅焊点BGA器件,通过对热应力加速实验中失效的SnAgCu无铅BGA焊点的显微结构分析和力学性能检测,研究双面贴装BGA器件的电路板出现互连焊点单面失效问题的原因,单面互连焊点失效主要是由于回流焊热处理工艺引起的.多次热处理过程中,NiSnP层中形成的大量空洞是导致焊点沿(Cu,Ni)6Sn5金属间化合物层和Ni(P)镀层产生断裂失效的主要因素.改变回流焊工艺是抑制双面贴装BGA器件的印制电路板出现互连焊点单面失效问题的关键.     

声表面波后工序环节对器件可靠性影响的研究

报道了声表面波（SAW）后工艺环节对基片粘接剂的固化程度、不同制作条件、不同封帽环境制作的滤波器，通过在高温、负温以及高温加速老化后的器件性能变化，来研究SAW器件的可靠性。结果表明：器件的插入损耗随老化时间逐渐增加；器件插入损耗的稳定性明显依赖于封装的湿度和器件表面的状态；器件的气密性随老化时间，器件的老化会更明显。结论是：器件必须要在清洁（净化）的环境中制作，清洁的器件表面第一重要；干燥的封装是器件性能稳定的重要条件；器件、组件老化到一定程度后，将不会有较大的性能变坏现象出现。这些研究成果，对防止或控制高性能器件失效、提高SAW器件可靠性将具有指导意义。     

SAW滤波器自动测试系统设计

针对声表面波(SAW)滤波器测试参数较多,仪器设置较复杂,且封装尺寸不断缩小,传统人工测试效率低,可靠性也不能满足要求等问题。该文利用国内定制的自动测试机,基于LabVIEW软件实现表面贴装器件(SMD)封装的SAW滤波器的自动测试系统。结果表明,该测试系统可实现SMD的自动上料、测试和记录数据,并自动分离不合格品,测试速度约1 000只/h,满足研发及小批量生产的需求。     

System-in-a-package integration of SAW RF Rx filter stacked on a transceiver chip

Demands for mobile phones with smaller form factor and lower cost have driven enhanced integration of electronics components. However, surface acoustic wave (SAW) filters must be fabricated on piezoelectric substrates, and so they are difficult to monolithically integrate on semiconductor chips. This paper reports on a compact wafer-scale packaged SAW filter stacked over a transceiver chip in a quad flat-pack no-lead (QFN) package. An integrated passive device (IPD) provided redistribution and matching between the SAW filter output and the transceiver input. Both extended global system for mobile communications (EGSM) and DCS filters were evaluated. Results demonstrated that conventional packaging techniques could be used to successfully assemble stacked SAW on transceiver modules without damage. SAW compact models based on the coupling of modes model were developed to facilitate system design. Electromagnetic simulations of coupling between SAW filters and inductors integrated on the transceiver suggested that design care is needed to avoid interactions, especially if an IPD is not used as a spacer. With appropriate design, stacked SAW filter on transceiver offers viable module integration.     

半导体器件和集成电路封装的发展趋势

随着表面安装技术(SMT)的迅速发展,电子元器件正在朝着片式化、编带化方面发展。本文仅就表面安装器件(SMD)及IC封装的目前状况以及涉及到的封装的新工艺、新材料的未来发展作了详细报导。尤其对高可靠、高密度多层陶瓷封装技术以及新型陶瓷材料作了详细评述,并对今后我所封装方面的研制、开发工作提出了建议和设想。     

一种新型声表面波器件封装技术

声表面波器件表贴封装一直存在着技术难点,因成品率低,难以实现批量生产。通过多次实验,使用新型声表面波器件封装技术制定工艺流程,最终采用减少温度梯度,通过在环氧树脂中加入无机添加剂来降低内应力的方法,有效解决了难点问题,为批量生产打下了基础。     

芯片叠层封装工艺技术研究

随着大量电子产品朝着小型化、高密度化、高可靠性、低功耗方向发展,将多种芯片封装于同一腔体内的芯片叠层封装工艺技术将得到更为广泛的应用,其封装产品的特点就是更小、更轻盈、更可靠、低功耗。芯片叠层封装是把多个芯片在垂直方向上堆叠起来,利用传统的引线封装结构,然后再进行封装。芯片叠层封装是一种三维封装技术,叠层封装不但提高了封装密度,降低了封装成本,同时也提高了器件的运行速度,且可以实现器件的多功能化。随着叠层封装工艺技术的进步及成本的降低,多芯片封装的产品将更为广泛地应用于各个领域,覆盖尖端科技产品和应用广大的消费类产品。     

Modular, device-scale, direct-chip-attach packaging formicrosystems

A pressing challenge to the commercial implementation of prototype microsystems is the reduction of package size and cost. To decrease package size, a process was developed for the fabrication of high-aspect-ratio, through-wafer interconnect structures. These interconnects permit device-scale packaging of microsystems and are compatible with modern surface mount technology such as flip chip assembly. To minimize package cost, a modular wafer-level silicon packaging architecture was devised. Low temperature bonding methods were used to join package components, permitting integration of driving circuitry on the microsystem die. The reconfigurable architecture allows standard package components to serve a wide variety of applications     

先进的叠层式3D封装技术及其应用前景

采用叠层3D封装技术将使芯片所包含晶体管数目成倍的增加,它不但具有体积小、性能高、功耗低等优点,而且拥有无可比拟的封装效率.对其叠层3D封装的发展趋势、技术特点、技术优势、散热问题以及应用前景等几个方面进行了探讨.     

Packaging multiple active and passive elements in a hybrid optical platform

The commercial market for telecom components has had an increasing demand for laser transmitter packages with higher functionality and smaller form factor. These higher levels of integration require an optical bench platform that can incorporate multiple active and passive elements and withstand stringent reliability requirements. Furthermore, the laser package must be compatible with high-volume manufacturing. We have developed an optical platform for building hybrid (multiple active elements) optoelectronic devices in a stable, hermetically sealed package. Two novel approaches to optical packaging have been developed: a localized laser soldering process and a flexure-based lens mount with large dynamic range. We present the optical bench and component design and the results of engineering reliability testing of the assembled package.     

MEMS加速计的SOIC封装技术研究

文中通过研究MEMS（微机电系统）加速计在SOIC封装（小外形集成电路封装）下的特性,针对MEMS芯片断裂故障的原因分析了影响PPM（百万分比的缺陷率）性能的主要封装工艺步骤。其中感应单元固晶胶的硬度是引起芯片断裂的主要参数,通过反向工程确定了可以同时满足感应单元固有频率和封装可靠性要求的固晶材料。在试验中采用固晶胶E后,MEMS加速计的SOIC封装呈现出更加强韧的特性。此研究对于改善MEMS加速计的PPM性能有一定参考价值。     

Analysis of Multilayered Microelectronic Packaging Under Thermal Gradient Loading

An accurate estimation of interfacial and axial stresses in multilayered structures is important in the design process of microelectronic packaging because these stresses drive the failure modes in the package. During manufacturing, microelectronic packaging devices usually suffer from severe thermal gradients. Design engineers often simplify the thermal gradient case as an isothermal loading case by averaging the temperature of the top and bottom of the microelectronic packaging device. Such simplification usually underestimates the stress level in the devices. With the analytical model presented in this paper, the stresses in multilayered microelectronic packaging devices subjected to thermal gradient loading can easily be predicted. It is shown that ignoring the thermal gradient in the package leads to underestimation of stresses