Corner turn of SAR data based on multi-FPGAs parallel system

A segmented storage strategy is provided for corner turn of Synthetic Aperture Radar (SAR) data based on multiple Field-Programable Gate Arrays (multi-FPGAs) parallel system. The optimal segmented length is related to the type of the Double-Data-Rate (DDR) memory. Address mapping between pixel location and memory location is expressed in pseudo-code, and the address mapping between bus address and memory address is also deduced in universal expression. A hardware module is given to implement DDR2 SDRAM controller. Practical debugging and experiment have proved that the segmented storage method balances the access rate between row and column in memory cells and accelerates the corner turn of two dimensional image data. Compared with previous related works, our implementation could get higher Throughput/Area and provide much more optimal performance.     

Dual-port RAMs simplify processor communications

Conventional memory blocks have a single address input and a single, usually bidirectional, data output. Dual-port memories have two address inputs and two data ports. These memories have been designed to facilitate the exchange of data between CPUs within a multiprocessor system. Each microprocessor can access the multiport memory and therefore read the data of another processor or leave data for another processor. There are two problems in the design of multiport memory systems. The first, and more trivial, concerns the way in which each processor supplies an address to the memory and how it accesses the memory data bus. This is not a particularly complex problem and the designer biggest worry is how to design the interface with the least number of multiplexers and buffers. Whenever a processor wishes to access the multiport memory, it takes control of the address and data bus and then accesses the memory. A more fundamental design problem is posed when two or more processors try to access the memory nearly simultaneously. Memory contention is solved by the use of an arbitration circuit that arbitrates between the contending processors, grants access to only one processor and forces the others to wait. Fortunately, it is no longer necessary for all designers to construct their own dual-port memories from discrete components, since several manufacturers now put the memory, address and data multiplexers plus arbitration circuits on chip. IDT's application note shows how its dual-port memory operates and how it is used in multiprocessor systems.     

Integrated task scheduling and data assignment for SDRAMs in dynamic applications

Runtime management of shared resources is crucial for efficient implementation of multimedia applications. Particularly, the energy consumption of SDRAMs is very sensitive to data assignment. This article presents an SDRAM data assignment technique for dynamic multithreaded multimedia and number of deadline violations applications, which, combined with task scheduling, minimizes the energy cost.     

基于2D Cache结构的H.264运动补偿访存带宽优化方法

H.264/AVC的运动补偿处理环节需要消耗大量的内存访问带宽,这成为制约其性能的关键因素.分析表明,如此巨大的带宽消耗具体来自5个方面:像素数据的重复读取、地址对齐、突发访问、SDRAM页切换和内存竞争冲突.提出一种基于2D Cache结构的运动补偿带宽优化方法,充分利用像素的重用以减少数据的重复读取.同时通过结合数据在SDRAM中映射方式的优化,将众多短而随机的访问整合为地址对齐的突发访问,并减少了访问过程中页切换的次数.此外还提出了访存的组突发访问模式,以解决SDRAM竞争冲突所引入的开销.实验结果表明采用上述优化设计后,运动补偿的访存带宽降低了82.9～87.6%,同现存优化效率较高的方法相比,带宽进一步减少了64%～87%.在达到相同带宽减少幅度的前提下,所提出的新方法比传统Cache结构电路面积减少91%.该方法目前已在一款多媒体SoC芯片设计中实际应用.     

计算密集型体系集成DDR SDRAM控制器设计

文章介绍了计算密集型体系解决存储器访问瓶颈的研究趋势。针对计算密集型体系的高数据访存需求，提出并在FPGA上实现了一种集成的DDRSDRAM控制器，其关键部分为固化初始化系列和专有的定制系统总线。仿真结果和分析表明，该控制器解决了计算密集型体系的数据访问瓶颈。     

基于FPGA的PCI接口DMA传输的设计与实现

PCI总线是高速同步总线,支持单字段传输和突发传输,突发传输中,写一次地址,传输多个数据段。DMA技术是一种由DMA控制器控制的存储器与外部设备或存储器之间大数据量传输的方法,具有传输速度高,CPU额外开销小的优点。介绍了一种使用FPGA在32位PCI接口内实现DMA块模式传输的设计方法,硬件部分基于Xilinx Virtex—II Pro^TM芯片,通过一个OPB—PCI总线桥实现了Power PC与主机问的FCI接口通信,不仅实现了PCI的突发式传输,发挥了PCI总线的高性能,而且将CPU从繁杂的I／O事务中解放出来,解决了原有通信系统中采用中断方式传输的瓶颈,使得PCI接口卡与主机间传输效率得到明显改善。     

FTC piles onto standardization Rambus' skullduggery

The Rambus standardization skullduggery saga continues. SDRAM technology licensor Rambus sued chipmaker Infineon for patent infringement because Infineon refused to take a license under Rambus' patents. (SDRAMs are synchronous dynamic random-access memory chips. Instead of running asynchronously (like ordinary DRAMs), SDRAMs are refreshed by a synchronous system clock. By 1999, SDRAM had largely replaced asynchronous DRAM.) Infineon then countersued for common-law fraud based on Rambus' alleged abuse of the standard-setting process. After a trial in which the judge assessed $7 million in damages against Rambus, the company appealed to the Federal Circuit appeals court. After its recent hearing of the opposing arguments, the Federal Circuit will probably take at least six months to hand down an opinion. In June 2002, the Federal Trade Commission weighed in by suing Rambus for engaging in unfair competition, in violation of section 5 of the FTC Act     

基于FPGA的一种存储器字节访问方法

计算机系统普遍采用较宽的存储器总线结构以提高吞吐率,这导致了以字节为基本单位读写数据的不便。通过对主流SDRAM存储器的访问机制的分析,为SDRAM存储控制器设计了一种数据自动对齐方案,该方案能够根据输入的字节地址和数据自动产生所需的存储器控制信号,并将数据对齐到正确的字节位置。详细阐述了生成地址、字节控制信号以及进行字节对齐的原理与方法,并在FPGA芯片上实现。与基于Cache以及基于两次存储器读写操作的方案相比较,新方案占用硬件资源更少,存储器带宽利用率更高。     

Location-Aware Tools for Improving Public Transit Usability

Real-time arrival information, immediately available on mobile devices, can significantly enhance the usability of public transit systems. The OneBusAway system provides just such information to more than 7,000 Seattle-area bus riders per day. The authors describe a new location-aware native iPhone application for OneBusAway that provides bus stop and arrival information tailored to the user's location. Results from survey and user-study evaluations demonstrate quicker access to data using the location-aware tool. In addition, data for OneBusAway users as a whole show strikingly positive changes in rider satisfaction, the number of transit trips per week, reduced wait time at bus stops, and increased walking. The positive results also hold for the location-aware version users, suggesting the possibility of even further gains.     

四画面目标搜索的设计与实现

在电视制导中,快速搜索并锁定被打击目标是关键技术之一。基于单片FPGA完成了一种利用多视场对目标进行搜索的设计。本设计对实时性要求极高,控制指令的解析采用浮点运算,并且数据的存储只采用了一片SDRAM地址交织完成,系统中灵活运用NiosII软核处理器和高速Avalon总线达到了以上要求。     

PROFIBUS通信性能测试与参数设置分析

PROFIBUS现场总线协议的实时性是评价其性能的关键因素,因此,如何研究和计算实时性能参数显得尤为重要. 针对这一问题,在对PROFIBUS总线存取协议深入分析的基础上,设计了基于PROFIBUS-DP通信性能测试平台. 通过测试平台分析和计算了包信息率、传输效率、网络平均利用率、网络吞吐量、传输延迟和令牌循环时间等实时性能参数,并给出了总线循环时间与主站个数及报文数量之间的关系之间的关系,从而定性定量分析了PROFIBUS-DP现场总线的实时性能.     

基于CPCI总线多DSP系统的高速主机接口设计

CPCI总线是一种成熟全面的计算机总线,通过它主机可以方便地为DSP加载程序,进行调试和监控工作;另外还能在主机和DSP系统间完成高速数据传输工作。本文结合一个已经成功应用的设计,阐述了基于双状态机+Cache结构的主机接口设计,并给出了逻辑框图。利用PLX公司的PCI9656接口芯片,FPGA提供了高达90MB/s的主机访问DSP和SDRAM的速度。     

基于PCI-E总线的高速数据传输卡的设计与实现

介绍了用于改善合成孔径雷达数据回放模块性能的高速数据传输卡的设计与实现;传输卡通过PCI Express总线与主机进行数据交互,配置两组DDR2SDRAM进行乒乓操作实现大容量高速缓存,在输入、输出数据传输率不匹配的情况下保证数据传输稳定、可靠;选用PLX公司的接口芯片PEX8311实现PCI Express总线接口功能,FPGA逻辑实现DDR2SDRAM控制器;测试结果表明,传输板数据传输率不低于100MB/s,工作状态稳定,达到了预期指标,具有一定的实用性和良好的应用前景。     

基于FPGA的卷积神经网络加速器动态余数处理映射模型

将卷积计算转化为矩阵乘法是FPGA上一种高效实现,而现有的转化方法无法根据卷积参数的不同动态调整,限制了卷积计算的并行度.提出一种新的动态余数处理映射模型.该映射模型包含有3个子模型:特征值映射模型,权值映射模型,和输出映射模型.特征值映射模型将特征值转化为特征值矩阵,权值映射模型将权值转化为权值矩阵,特征值矩阵和权值矩阵通过乘累加计算阵列得到卷积计算结果,由输出映射模型将卷积计算结果存储到内存中.在卷积计算过程中,卷积的输出通道数通常不是乘累加计算阵列行数的整数倍,3个子映射模型会根据产生的余数动态调整映射方法,提高乘累加计算阵列的利用率.通过实验表明,采用动态余数处理映射模型能够将余数并行度的倍数至多提高到卷积核大小,使整个加速器达到了更高的实际吞吐量和能量效率.     

基于NiosII软核的嵌入式通用数据回放器

通用数据回放器通常用于检验实时信号处理器的接收和实时处理能力,或者设备的故障检测。本文针对嵌入式通用数据回放器,重点讨论了基于FPGA的嵌入式PCI总线数据回放卡的设计,由于板卡采用了FPGA和NiosII软核技术,降低了硬件设计难度,减少板卡功耗,提高了适应性、通用性和可扩展性,同时,采用乒乓SDRAM大容量存储技术,提高了数据回放器的实时性等性能指标。     

基于NiosII软核的嵌入式通用数据回放器

通用数据回放器通常用于检验实时信号处理器的接收和实时处理能力,或者设备的故障检测。本文针对嵌入式通用数据回放器,重点讨论了基于FPGA的嵌入式PCI总线数据回放卡的设计,由于板卡采用了FPGA和NiosII软核技术,降低了硬件设计难度,减少板卡功耗,提高了适应性、通用性和可扩展性,同时,采用乒乓SDRAM大容量存储技术,提高了数据回放器的实时性等性能指标。     

Performance Modeling and Evaluation of a Two-Dimensional Disk Array System

This paper presents a performance model of a two-dimensional disk array (TIDA) system, which is composed of several major subsystems including disk cache, intelligent disk array controller, SCSI-like I/O bus, and two-dimensional array of disk devices. Accessing conflict in these subsystems and fork/join synchronization of physical disk requests are considered in the model. The representation for the complex behavior, including the interactions among subsystems, of a whole disk array system distinguishes the model from others that model only individual subsystems. To assist evaluating the architectural alternatives of TIDA, we employ a subsystem access time modeling methodology, in which we model for each subsystem the mean subsystem access time per request (SATPR). Fed with a given set of representative workload parameters, the performance model is used to conduct performance evaluation and the SATPRs of the subsystems are utilized to identify the bottleneck subsystem for performance improvement. The results show that (1) the values of some key design parameters, such as data block size and I/O bus bandwidth that yield the best system throughput are dependent not only on the subsystem performance but also on the interaction among subsystems; (2) an I/O bus bandwidth of 5 Mbytes/s per disk device is large enough for data transfers from/to disk devices equipped with a cache of 1 Mbytes; and (3) the activity of fork/join synchronization of physical disk requests may cause performance degradation, which can be improved by using large I/O bus bandwidth and/or placing a cache in each disk device.     

基于CAN总线的智能网桥设计

根据CAN总线扩展标识符的特点和网桥地址需求,利用扩展标识符构建数据转发地址表,针对网段的合理分配问题,提出网段优先和节点优先的网段节点位分配算法,并进行位利用率的评估。分析二维数组转发地址表的学习算法,针对网桥环网提出单向生成转发路线的网桥端口生成树算法。在不同负载下对网桥的利用率和延迟进行实验,结果证明该CAN双端口网桥设计方法可以实现CAN网桥的功能。     

高档个人计算机的系统空间映射和周期转换

在一个典型的具有３级总线结构的ＰＣ机里，一方面各级总线上的主设备都可面对自己的地址空间启动各自总线上的访问周期，另一方面系统中各类地址空间实体分布在各级总线上，使得各级总线设备的访问地址与各处实际空间的映射关系千头万绪。该文把物理上分布于各处的地址空间组织成一个整体，并视之为一个独立于各级总线主设备地址空间之外的、又为各级主设备所共有的空间（系统空间），然后在此基础上着重分析了两级总线桥如何共同把     

潜铺型卫星认知通信中上行链路功率控制

针对卫星通信中存在有效信道远小于注册频率的情况,提出了以潜铺型认知无线电为技术依靠的卫星上行链路功率控制算法。该算法以次要用户所获吞吐量与付出代价之差为效用函数,通过次要用户作为参与者建立的博弈模型进行纳什均衡求解,得到最优功率分配策略。该策略可满足次要用户自身需求,亦不影响主要用户系统正常通信,能有效提高频带使用率。在性能方面,指出了次要用户系统容量和预留信噪比的关系。仿真结果表明,在主要用户系统容许范围内次要用户数量越多则其系统吞吐量和系统收益越大,最后讨论了算法的实现复杂度。