天津激光全息干版Ⅰ、Ⅱ型特性的研究

至今能提供全息记录的材料至少有七种。作为这些记录介质之一的银盐感光材料,虽然还存在某些不足之处,但它和其他一些全息记录介质比较起来,具有感光度高的优点,因而它仍然是适用的全息记录材料。 本文研究了天津全息版Ⅰ型、Ⅱ型的光谱感光灵敏度,H—D曲线及振幅透射率特性曲线,感光材料的调制传递特性,并概述了这两种全息版对于白光再现体积全息照片的适应性。     

带双投影物镜和全息屏幕的投影型全息显微镜

本文提出了一种可用于集成电路装配和质量控制的、带有双投影物镜和全息光学元件散射全息屏幕的投影型全息显微镜(PHM)系统。介绍了该系统的光学原理、全息散射屏幕的记录方案、系统色差的改善和投影显微系统的特性。     

声场全息重构方法与实验研究

声场全息重构是通过近场声全息重构声源的声辐射特性的一种声场反演方法,是近年来的研究热点问题.基于近场声全息声场重构模型,研究声场全息重构方法;再运用LabVIEW虚拟仪器软件平台,开展了传声器阵列各通道标定校准、数据采集、全息面复声压的获取和声场可视化等声场全息重构实验研究.实验结果表明,声场全息重构实验具有较高的定位精度,同时也验证了声场全息重构方法的有效性和实用性.     

全息干板的时间响应特性

全息干板的感光过程涉及到银原子和光电子的动力学过程,这些动力学特性决定了全息干板对不同曝光时间尺度具有不同的感光效率。介绍了用随机过程方法建立的全息干板时间响应理论模型,用该模型分析了SlavichVRP-M型全息干板的时间响应特性并进行了数值模拟。设计了三套不同的曝光实验装置用于时间响应特性的研究,给出了8个时间点的实验数据,在曝光量不变的情况下,曝光时间范围为0.5 ns~10 s。实验结果与理论结果比较吻合,表明全息干板在曝光过程中存在低照度和高照度互易律失效。最后简要分析了互易律失效对全息照相的影响。     

彩色全息显示方法与系统概述

彩色全息显示是全息视频显示技术发展的重要目标。概述了基于空间光调制器实现彩色全息显示的方法与系统构建问题。首先,介绍了彩色全息显示中三个单色全息像叠加生成彩色全息再现像的基本原理。分析了全息图生成的方法,比较了光全息图、数字全息图、计算机生成全息图的不同。其次,讨论了彩色全息显示系统构建时空间光调制器的选择以及多波长照明下的相位调制特性问题。在实际系统中,红、绿、蓝三色激光或者发光二极管都可以用作系统照明光源。然后,描述了基于时分复用、空间复用、空间划分、空间叠加方法构建的彩色全息显示系统架构,指出彩色全息重构结果受到空间光调制器像素结构和色差等问题的影响。最后,展望了彩色全息显示技术的发展方向。     

全息微光刻中全息掩模衍射特性的理论研究

通过耦合波理论分析,使用矩阵转换方法,对全息光刻中全息掩模衍射效率进行数值模拟计算,得出了影响全息掩模衍射特性的因素主要是显影前后记录材料平均介电常数的改变、介质的膨胀与收缩以及非共轭再现等,为实验研究提供了理论依据.     

基于全息聚合物液晶光栅的动态增益均衡器的设计与模拟

介绍了聚合物分散液晶(PDLC)材料及体全息光栅的特性,提出了基于全息聚合物液晶(H-PDLC)电控光栅多极串联式动态增益均衡器的设计。根据光栅的衍射特性计算公式,对全息聚合物液晶光栅在中心波长为1550 nm的波长选择特性进行模拟,并且进一步利用遗传算法模拟实现全息聚合物液晶动态光强增益均衡器的功能。计算模拟表明,选择合适的全息聚合物液晶光栅参量,能够使光栅在1550 nm为中心波长的衍射谱线半宽度达到10 nm。同时,采用基于全息聚合物液晶的动态光强增益均衡器,能够使掺饵光纤放大器在1530~1560 nm内,其自发辐射谱的不平坦度从3.3 dB降到0.1 dBp-p(峰-峰值)。     

全色铬酸盐明胶全息记录新材料

通过在明胶层中引入新型多色光敏剂及光化学增感助剂,成功研制出了三基色感光度达30 mJ/cm2、衍射效率大于85%和分辨率大于5 000 lines/mm的全色铬酸盐明胶全息记录新材料.对其配方构成、光谱响应曲线、三基色感光灵敏度、反射体全息光栅的光谱选择性、透射体全息光栅的角度及波长选择性等特性进行了报道,对其在真彩色全息显示、角度复用波长复用全息存储等的初步应用结果作了简要的介绍.     

计算全息光栅的技术研究与设计

论述了计算全息光栅用于光谱仪器分光系统的分光原理和特性,以圆筒型计算全息光栅为例,给出了圆筒型计算全息光栅的位相函数方程、条纹位置方程及参数结构方程式,并且用MATLAB软件将其制作出来,最后对提高光栅分辨率问题进行了分析。     

汽车全息平显系统

本文利用非均匀反射体全息理论讨论了我们制作 的重铬酸明胶反射全息衍射特性和折率率调制分布;     

X-ray metrology for high-k atomic layer deposited HfxZr1−xO2 films

Hafnium-based dielectrics are the most promising material for SiO₂ replacement in future nodes of CMOS technology. While devices that utilize HfO₂ gate dielectrics suffer from lower carrier mobility and degraded reliability, our group has recently reported improved device characteristics with a modified Hf_xZr_1−xO₂ [R.I. Hegde, D.H. Triyoso, P.J. Tobin, S. Kalpat, M.E. Ramon, H.-H. Tseng, J.K. Schaeffer, E. Luckowski, W.J. Taylor, C.C. Capasso, D.C. Gilmer, M. Moosa, A. Haggag, M. Raymond, D. Roan, J. Nguyen, L.B. La, E. Hebert, R. Cotton, X.-D. Wang, S. Zollner, R. Gregory, D. Werho, R.S. Rai, L. Fonseca, M. Stoker, C. Tracy, B.W. Chan, Y.H. Chiu, B.E. White, Jr., in: Technical Digest - International Electron Devices Meet, vol. 39, 2005, D.H. Triyoso, R.I. Hegde, J.K. Schaeffer, D. Roan, P.J. Tobin, S.B. Samavedam, B.E. White, Jr., R. Gregory, X.-D. Wang, Appl. Phys. Lett. 88 (2006) 222901]. These results have lead to evaluation of X-ray reflectivity (XRR) for monitoring high-k film thickness and control of Zr addition to HfO₂ using measured film density. In addition, a combination of XRR and spectroscopic ellipsometry (SE) is shown to be a fast and non-intrusive method to monitor thickness of interfacial layer between high-k and the Si substrate.     

Analog Circuit Synthesis Using Linear and Nonlinear Current Amplifiers

Various design techniques are presented for obtaining current-mode filters suitable for operation at high frequencies. For this purpose CMOS and or bipolar current amplifiers are used as active building blocks. The derived circuits simulate LC passive prototype filters. Second order resonators can also be obtained by following the same techniques. The presented circuits are modular in structure, thus, their electronic and layout design is very easy. Low-voltage, low-power design is also feasible. Simulation examples for all-pole filters and filters with transmission zeros are given. George Souliotis received the B.Sc. degree in physics from the University of Ioannina, Ioannina, Greece, in 1993 and the M.Sc. and Ph.D. degrees in electronics from the University of Patras, Patras, Greece, in 1998 and 2003, respectively. From 2000 to 2002, he was with Giga Hellas, an Intel company, designing high-speed electronic circuits for transceivers for optical networks. He is co-inventor of a patent that was developed through that work. He is currently a Post-Doctoral Researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece. His research interests include analog and mixed signal integrated circuits for high-speed communication applications, current mode circuits, continuous time active filters and CMOS-BiCMOS VLSI design. Nikos Fragoulis was born in Megara Attikis, Greece, in 1972. He received the B.S. degree in physics and the M.Sc. degree in electronics and Ph.D. in electronics from the Electronics Laboratory, Department of Physics, University of Patras, Patras, Greece, in 1995, 1998 and 2005 respectively. He is currently a post-doctoral researcher with the Electronics Laboratory, Department of Physics, University of Patras, Patras Greece. His research interests include, continuous time filtering, and analog integrated circuits for broadband telecommunication applications. Ioannis Haritantis received the Ph.D. in Electronics, in 1976, from the Physics Department, University of Patras, Patras, Greece, in collaboration with the Electrical Engineering Department, Imperial College, London, UK. For many years he has conducted scientific research on the development and design of circuits, discrete component and/or integrated, which are suitable for analog signal processing. His other fields of interest include, network theory, design and testing of integrated circuits, integrated active devices for telecommunications and medical instrumentation, smart sensors, and e-learning. During the past few years his focus is on the design of low-power, low-voltage, tunable, integrated active filters of high dynamic range that could operate at high frequencies. Professor Haritantis in now the director of the Electronics Laboratory, Division of Electronics and Computers, Department of Physics, University of Patras, Patras, Greece. He is also in the editorial board of the journal “Analog Integrated Circuits and Signal Processing”, Kluwer Academic Publishers.     

Hybrid Morphology Processing Unit Architecture for Moving Object Segmentation Systems

Video segmentation is a key operation in MPEG-4 content-based coding systems. For real-time applications, hardware implementation of video segmentation is inevitable. In this paper, we propose a hybrid morphology processing unit architecture for real-time moving object segmentation systems, where a prior effective moving object segmentation algorithm is implemented. The algorithm is first mapped to pixel-based operations and morphological operations, which makes the hardware implementation feasible. Then the high computation load, which is more than 4.2 GOPS, can be overcome with a dedicated morphology engine and a programmable morphology PE array. In addition, the hardware cost, memory size, and memory bandwidth can be reduced with the partial-result-reuse concept. This chip is designed with TSMC 0.35 μm 1P4M technology, and can achieve the processing speed of 30 QCIF frames or 7,680 morphological operations per second at 26 MHz. Simulation shows that the proposed hardware architecture is efficient in both hardware complexity and memory organization. It can be integrated into any content-based video processing and encoding systems. Shao-Yi Chien was born in Taipei, Taiwan, R.O.C., in 1977. He received the B.S. and Ph.D. degrees from the Department of Electrical Engineering, National Taiwan University (NTU), Taipei, in 1999 and 2003, respectively. During 2003 to 2004, he was a research staff in Quanta Research Institute, Tao Yuan Shien, Taiwan. In 2004, he joined the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, as an Assistant Professor. His research interests include video segmentation algorithm, intelligent video coding technology, image processing, computer graphics, and associated VLSI architectures. Bing-Yu Hsieh was born in Taichung, Taiwan, in 1979. He received the B.S.E.E and M.S.E.E degrees from National Taiwan University (NTU), Taipei, in 2001 and 2003, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2003, where he develops integrated circuits related to multimedia systems and optical storage devices. His research interests include object tracking, video coding, baseband signal processing, and VLSI design. Yu-Wen Huang was born in Kaohsiung, Taiwan, in 1978. He received the B.S. degree in electrical engineering and Ph. D. degree in the Graduate Institute of Electronics Engineering from National Taiwan University (NTU), Taipei, in 2000 and 2004, respectively. He joined MediaTek, Inc., Hsinchu, Taiwan, in 2004, where he develops integrated circuits related to video coding systems. His research interests include video segmentation, moving object detection and tracking, intelligent video coding technology, motion estimation, face detection and recognition, H.264/AVC video coding, and associated VLSI architectures. Shyh-Yih Ma received the B.S.E.E, M.S.E.E, and Ph.D. degrees from National Taiwan University in 1992, 1994, and 2001, respectively. He joined Vivotek, Inc., Taipei County, in 2000, where he developed multimedia communication systems on DSPs. His research interests include video processing algorithm design, algorithm optimization for DSP architecture, and embedded system design. Liang-Gee Chen was born in Yun-Lin, Taiwan, in 1956. He received the BS, MS, and Ph.D degrees in Electrical Engineering from National Cheng Kung University, in 1979, 1981, and 1986, respectively. He was an Instructor (1981–1986), and an Associate Professor (1986–1988) in the the Department of Electrical Engineering, National Cheng Kung University. In the military service during 1987 and 1988, he was an Associate Professor in the Institute of Resource Management, Defense Management College. From 1988, he joined the Department of Electrical Engineering, National Taiwan University. During 1993 to 1994 he was Visiting Consultant of DSP Research Department, AT&T Bell Lab, Murray Hill. At 1997, he was the visiting scholar of the Department of Electrical Engineering, University, of Washington, Seattle. Currently, he is Professor of National Taiwan University. From 2004, he is also the Executive Vice President and the General Director of Electronics Research and Service Organization (ERSO) in the Industrial Technology Research Institute (ITRI). His current research interests are DSP architecture design, video processor design, and video coding system. Dr. Chen is a Fellow of IEEE. He is also a member of the honor society Phi Tan Phi. He was the general chairman of the 7th VLSI Design CAD Symposium. He is also the general chairman of the 1999 IEEE Workshop on Signal Processing Systems: Design and Implementation. He serves as Associate Editor of IEEE Trans. on Circuits and Systems for Video Technology from June 1996 until now and the Associate Editor of IEEE Trans. on VLSI Systems from January 1999 until now. He was the Associate Editor of the Journal of Circuits, Systems, and Signal Processing from 1999 until now. He served as the Guest Editor of The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, November 2001. He is also the Associate Editor of the IEEE Trans. on Circuits and Systems II: Analog and Digital Signal Processing. From 2002, he is also the Associate Editor of Proceedings of the IEEE. Dr. Chen received the Best Paper Award from ROC Computer Society in 1990 and 1994. From 1991 to 1999, he received Long-Term (Acer) Paper Awards annually. In 1992, he received the Best Paper Award of the 1992 Asia-Pacific Conference on Circuits and Systems in VLSI design track. In 1993, he received the Annual Paper Award of Chinese Engineer Society. In 1996, he received the Out-standing Research Award from NSC, and the Dragon Excellence Award for Acer. He is elected as the IEEE Circuits and Systems Distinguished Lecturer from 2001–2002.     

基于ASP.NET的网络选课系统的设计与实现

本设计为基于Dotnet技术开发的网络选课系统,引入学分制和竞分制的概念。提供学生、教师、管理员三个角色登陆系统。实现了学生选课、退课、竞买选课、查看成绩,查看选课结果,查看个人信息、课程信息、教室信息;教师查看教学计划,录入成绩;管理员维护学生、教师、课程、教室信息,设置系统状态等功能。在课程上进行了较细的分类,主要分为专业选修课、专业必修课、公共选修课、公共必修课。该系统具有操作简便,功能强大,可扩展性好等特点。为学生,教师,管理员提供简单快捷的选课工作环境。     

DREAM : Density Aware Overlay Multicast Forwarding in Mobile Ad Hoc Networks

Instead of multicast functionality on a network entity, the overlay multicast schemes support multicast service with help of underlying unicast routing protocol. However, due to a node's free migration and communication based on broadcasting capability, effectiveness of overlay multicast scheme is not guaranteed in Mobile Ad Hoc Networks (MANET). Specially, nodes' density within some areas changes frequently so heterogeneous forwarding scheme based on density is strongly desired in order to reduce a number of collisions as well as enhance resource utilization. To achieve this, in this paper, we introduce a new forwarding scheme, called as DREAM (Density aware overlay Multicast forwarding). A key feature of DREAM is to introduce a scoped flooding where the nodes densely locates, on the other hand, data forwarding based on unicast routing protocol is maintained in sparse environment. Distinct advantages are evaluated by simulation. Ki-Il Kim received the M.S. and Ph.D. degrees in computer science from the Chungnam National University, Daejeon, Korea, in 2002 and 2005, respectively. He is currently with Department of Information Science, Gyeongsang National University as a faculty member. His research interests include routing for MANET, QoS in wireless network, multicast, and sensor networks. Sang-Ha Kim received the B.S. degree in chemistry from Seoul National University, Seoul, Korea, in 1980. He received the M.S. and Ph.D. degrees in quantum scattering and computer science from the University of Houston, Houston, TX, in 1984 and 1989, respectively. From 1990 to 1991, he was with the Supercomputing Center, SERI, Korean Institute of Science and Technology (KIST) as Senior Researcher. He joined Chungnam National University, Daejeon,Korea, in 1992, where he is a Professor. His current research interests include wireless networks, ad hoc networks, QoS, optical networks, and network analysis.     

Handling routability in floorplan design with twin binary trees

As technology moves into the deep-submicron era, the complexities of VLSI circuits grow rapidly. Interconnect optimization has become an important concern. Most routability-driven floorplanners [H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. Sherwani, Integrated floorplanning and interconnect planning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 1999, pp. 354–357; S. Krishnamoorthy, J. Lou, H.S. Sheng, Estimating routing congestion using probabilistic analysis, in: Proceedings of International Symposium on Physical Design, 2001, pp. 112–117; M. Wang, M. Sarrafzadeh, Modeling and minimization of routing congestion, in: IEEE Asia and South Pacific Design Automation Conference, 2000, pp. 185–190] use grid-based approach that divides a floorplan into grids as in global routing to estimate congestion by the expected number of nets passing through each grid. This approach is direct and accurate, but not efficient enough when dealing with complex circuits containing many nets. In this paper, an efficient and innovative interconnect-driven floorplanner using twin binary trees (TBT) representation [B. Yao, H. Chen, C.K. Cheng, R. Graham, Revisiting floorplan representations, in: Proceedings of International Symposium on Physical Design, 2001, pp. 138–143; E.F.Y. Young, C.C.N. Chu, Z.C. Shen, Twin binary sequences: a non-redundant representation for general non-slicing floorplan, in: Proceedings of International Symposium on Physical Design, 2002, pp. 196–201] is proposed. The estimations are based on the wire densities (number of wires passing through per unit length) on the half-perimeter boundaries of different regions in a floorplan. These regions are defined naturally by the TBT representation. Buffer planning is also considered by deciding if buffers can be inserted successfully for each net. In order to increase the efficiency of our floorplanner, a fast algorithm for the least common ancestor (LCA) problem in Bender and Farach-Colton [The LCA problem revisited, in: Latin American Theoretical INformatics, 2000, pp. 88–94] is used to compute wire density, and a table look-up approach is used to obtain the buffer insertion information. Experimental results show that our floorplanner can reduce the number of unroutable wires. The performance is comparable with other interconnect-driven floorplanners that perform global routing-like operations directly to estimate routability, but our estimation method is much faster and is scalable for large complex circuits.     

New Four-Quadrant CMOS Current-Mode and Voltage-Mode Multipliers

In this paper, a four-quadrant current-mode multiplier based on a new squarer cell is proposed. The multiplier has a simple core, wide input current range with low power consumption, and it can easily be converted to a voltage-mode by using a balanced output transconductor (BOTA) [1]. The proposed four-quadrant current-mode and voltage-mode multipliers were confirmed by using PSPICE simulation and found to have good linearity with wide input dynamic range. For the proposed current-mode multiplier, the static power consumption is 0.671 mW, the maximum power consumption is 0.72 mW, the input current range is ± 60 μ A, the bandwidth is 31 MHz, the input referred noise current is 46 pA/√Hz, and the maximum linearity error is 3.9%. For the proposed voltage-mode multiplier, the static power consumption is 1.6 mW, the maximum power consumption is 1.85 mW, the input voltage range is ± 1V from ± 1.5V supply, the bandwidth is 25.34 MHz, the input referred noise voltage is 0.85 μV/√Hz, and the maximum linearity error is 4.1%. Mohammed A. Hashiesh was born in Elkharga, New Valley, Egypt, in 1979. He received the B.Sc. degree with honors from the Electrical Engineering Department, Cairo University, Fayoum-Campus, Egypt in 2001, and he received the M.Sc. degree in 2004 from the Electronics and Communication Engineering Department, Cairo University, Egypt. He is currently a Teacher Assistant at the Electrical Engineering Department, Cairo University, Fayoum-Campus. His research interests include analog CMOS integrated circuit design and signal processing, and digitally programmable CMOS analog building blocks. Soliman A. Mahmoud was born in Cairo, Egypt, in 1971. He received the B.Sc. degree with honors, the M.Sc. degree and the Ph.D. degree from the Electronics and Communications Department, Cairo University—Egypt in 1994, 1996 and 1999 respectively. He is currently an Assistant Professor at the Electrical Engineering Department, Cairo University, Fayoum-Campus. He has published more than 50 papers. His research and teaching interests are in circuit theory, fully integrated analog filters, high frequency transconductance amplifiers, low voltage analog CMOS circuit design, current-mode analog signal processing and mixed analog/digital programmable analog blocks. Ahmed M. Soliman was born in Cairo Egypt, on November 22, 1943. He received the B.Sc. degree with honors from Cairo University, Cairo, Egypt, in 1964, the M.S. and Ph.D. degrees from the University of Pittsburgh, Pittsburgh, PA., U.S.A., in 1967 and 1970, respectively, all in Electrical Engineering. He is currently Professor Electronics and Communications Engineering Department, Cairo University, Egypt. From September 1997–September 2003, Dr Soliman served as Professor and Chairman Electronics and Communications Engineering Department, Cairo University, Egypt. From 1985–1987, Dr. Soliman served as Professor and Chairman of the Electrical Engineering Department, United Arab Emirates University, and from 1987–1991 he was the Associate Dean of Engineering at the same University. He has held visiting academic appointments at San Francisco State University, Florida Atlantic University and the American University in Cairo. He was a visiting scholar at Bochum University, Germany (Summer 1985) and with the Technical University of Wien, Austria (Summer 1987). In 1977, Dr. Soliman was decorated with the First Class Science Medal, from the President of Egypt, for his services to the field of Engineering and Engineering Education. Dr Soliman is a member of the Editorial Board of Analog Integrated Circuits and Signal Processing. Presently Dr. Soliman is Associate Editor of the IEEE Transactions on Circuits and Systems I (Analog Circuits and Filters).     

Design of Current-Mode Square-Root Domain Band-Pass Filter with Reduced Voltage

A design technique for current-mode square-root domain band-pass filter fabricated in a 0.25 μ m CMOS process is presented. The basic building block consists of current-mode current mirrors, square-root circuits and capacitors, and in which the overall supply voltage is reduced by adopting low-voltage level-shift current mirror. Both of the simulation and measured results, which are in good agreement, indicate that the prototype of the band-pass provides tunable center frequency of 4–10 MHz with bias-current-tunable, −26.7 dB total harmonic distortion (THD), and approximately 1.598 mW power dissipation with a 1.5 V supply voltage. Advantages of the proposed filter include high frequency operation, tuneability, low supply voltage operation, low power consumption, and low third order intermodulation distortion. Gwo-Jeng Yu was born in Kaohsiung, Taiwan, R.O.C., in 1954. He received the B.S. and M.S. degrees in the Department Electronic Engineering in 1972 and 1976, respectively, from National Chiao Tung University, HsinChu, Taiwan, R.O.C., and he is currently working toward the Ph.D. degree in the Department of Electrical Engineering of National Cheng Kung University, Tainan, Taiwan, R.O.C. Since 1978, he has been on the Faculty of Institute of Cheng Shiu Technology, Kaohsiung, Taiwan, R.O.C., where he is currently a Associate Professor in the Department of Electronic Engineering. During 1979–1990, he was the Chairman of the Electronic Engineering Department and the Chairman of the Microelectronics and Information Technology Center during 1996–2000. His current researches include current-mode circuits design, analog IC design and VLSI circuit design. Chun-Yueh Huang was born in Taichung, Taiwan, Republic of China, on March 24, 1967. He received the B.S. degree in industrial education from the National Chang Hwa Normal University, Chang Hwa, Taiwan in 1991, M.S. and Ph.D. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1993 and 1997, respectively. Since 1999 he has been with the Kan Shan University of Technology, where he is currently Associate Professor and Chairman of the Department of Electronic Engineering. His current researches include current-mode circuits design, VLSI design, analog IC design, and analog IP design. Jenn-Jiun Chen received the B.S. and M.S. degrees both in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 2001 and 2003, respectively. His research interests are design and modeling of current mode circuit, low power analog circuit design, current mode filters, and instrumental amplifier in micro sensor applications. He received Chip Design Award from the Chip Implementation Center, National Applied Research Laboratories, in 2002. Bin-Da Liu received the B.S., M.S., and Ph.D. degrees all in electrical engineering from the National Cheng Kung University, Tainan, Taiwan, in 1973, 1975, and 1983, respectively. Since 1977 he has been on the faculty of the National Cheng Kung University, where he is currently Distinguished Professor in the Department of Electrical Engineering and Director of the SoC Research Center. During 1983–1984, he was a Visiting Assistant Professor in the Department of Computer Science, University of Illinois at Urbana-Champaign. During 1988–1992, he was the Director of Electrical Laboratories, National Cheng Kung University. He was the Associate Chair of the Electrical Engineering Department during 1996–1999 and the Chair during 1999–2002. Since 1995 he has been a consultant of the Chip Implementation Center, National Applied Research Laboratories. He has published more than 190 technical papers. He also contributed chapters in the book Neural Networks and Systolic Array Design (D. Zhang Ed. Singapore: World Scientific Publisher, 2002) and the book Accuracy Improvements in Linguistic Fuzzy Modeling (J. Casillas, O. Cordn, F. Herrera, and L. Magdalena Eds. Heidelberg, Germany: Springer-Verlag, 2003). He is currently a CAS Associate Editor of the IEEE Circuits & Devices Magazine and an Associate Editor of the IEEE Transactions on Circuits and Systems-I. His current research interests include low power circuit design, SoC system integration and verification, and VLSI implementation for fuzzy-neural networks and audio/video signal processors.     

Thyristor Input-Protection Device Suitable for CMOS RF IC’s

Based on simulation results and accompanying analysis, we suggest a thyristor-type ESD protection device structure suitable for implementation in standard CMOS processes to reduce the parasitic capacitances added to the input nodes, which is very important in CMOS RF ICs. We compare DC breakdown characteristics of the suggested device to those of a conventional NMOS protection device to show the benefits of using the suggested device for ESD protection. The characteristic improvements are demonstrated and the corresponding mechanisms are explained based on simulations. Structure dependencies are also examined to define the optimal structure. AC simulation results are introduced to estimate the magnitude of reduction in the added parasitic capacitance when using the suggested device for ESD protection. The analysis shows a possibility of reducing the added parasitic capacitance down to about 1/45 of that resulting with a conventional NMOS protection transistor, while maintaining robustness against ESD.Jin-Young Choi was born in Seoul, Korea in 1956. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the M.S. and Ph.D. degrees in electrical engineering from the University of Florida, USA, in 1986 and 1991, respectively. In 1991, he joined Samsung Electronics Memory Division, Korea, where he was engaged in high-speed SRAM development. In 1992, he moved to the Hongik University, Jochiwon, Korea, where he is now an associate professor. His recent research interests include the high-frequency modeling of CMOS devices, CMOS RF circuit design, and analysis & design for ESD protection.Woo Suk Yang was born in Seoul, Korea in 1957. He received the B.S. degree in electrical engineering from the Seoul National University, Korea, in 1979, and the Ph.D. degree in electrical and computer engineering from the North Calorina State University, USA, in 1990. His doctorial research was in the area of signal processing. In 1990, he joined LG Electronics Co. Korea. In 1991, he moved to the Hongik University, Jochiwon, Korea, where he is now a professor. His recent research interests include the high-frequency modeling and various topics in signal processing area.Dongmin Kim was born in Korea in 1956. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea, in 1979 and 1984, respectively and the Ph.D. degree in ECE from the University of Michigan, USA, in 1996. Now, he is an assistant professor of the Hongik University, Jochiwon, Korea. His recent research interests include circuit design and analysis.Youngju Kim was born in Seoul, Korea in 1957. He received the B.S. and M.S. degrees in electrical engineering from the Seoul National University, Korea in 1980 and 1985, respectively and the Ph.D. degree in electrical engineering from the Polytechnic University of New York, USA, in 1995, respectively. In 1996, he joined the Hongik University, Jochiwon, Korea, where he is now an assistance professor. His recent research interests include the RF circuit design and LIN wireless systems.     

Patch Loading Circular Aperture Slot Antennas for Broadband WLAN Applications

This paper proposes a new and simple design for a broadband planar antenna with bi- and uni-directional radiation for WLAN applications. The broadband operation is realized by loading a patch into a circular aperture slot, which is fed by a micostrip line on the other side of the slot. The frequency characteristics and the radiation performance of the antenna were studied theoretically and experimentally. The obtained results show that the proposed antenna can offer effective bandwidth for the two cases in bi- and uni-directional radiation. For the former, more than 75% impedance bandwidth can be obtained whereas for the latter, better than 20 dB front–back radiation ratio can be achieved.Tayeb A. Denidni (M98-SM04) received the B.Sc. degree in electronic engineering from the University of Setif, Setif, Algeria, in 1986, and the M.Sc. and Ph.D. degrees in electrical engineering from Laval University, Qubec City, QC, Canada, in 1990 and 1994, respectively. From 1994 to 1996, he was an Assistant Professor with the engineering department, Universit du Qubec in Rimouski (UQAR), Rimouski, QC, Canada. From 1996 to 2000, he was also an Associate Professor at UQAR, where he founded the Telecommunications laboratory. Since August 2000, he has been with the Personal Communications Staff, Institut National de la Recherche Scientifique (INRS-EMT), Universit du Qubec, Montreal, QC, Canada. His current research interests include planar microstrip antennas, dielectric resonator antennas, adaptive antenna arrays, microwave and RF design for wireless applications, phased arrays, microwave filters, RF instrumentation and measurements, microwave and development for wireless communications systems. Dr. Denidni is a Member for the Order of Engineers of the Province of Qubec, Canada. He is also a Member of URSI (Commission C). He has authored more than 60 papers in refereed journals and conferences.Qinjiang Rao received the Ph.D. degree from Peking University, Beijing, China, in July 1999. Now he is a postdoctoral fellow at INRS-EMT, University of Quebec, Montreal, Canada. Before this term, he even worked as a postdoctoral fellow at Kyoto University, Kyoto, Japan, and University of Calgary, Calgary, Canada, respectively. His research fields focus on antennas, high-frequency electromagnetic simulators, radio wave propagation and scattering. In 1999, he was the recipient of a Post-doctoral Fellowship awarded by the JSPS (Japan Society for the Promotion of Science.)