A sub 1 V high PSRR CMOS bandgap voltage reference

A Bandgap circuit capable of generating a reference voltage of less than 1 V with high PSRR and low temperature sensitivity is proposed. High PSRR achieved by means of an improved current mode regulator which isolates the bandgap voltage from the variations and the noise of the power supply. A vigorous analytical approach is presented to provide a universal design guideline. The analysis unveils the sensitivity of the circuit characteristic to device parameters. The proposed circuit is fabricated in a CMOS technology and operates down to a supply voltage of 1.2 V. The circuit yields 20 ppm/°C of temperature coefficient in typical case and 50 ppm/°C of temperature coefficient in worst case over temperature range −40 to 140°C, 60 ppm/V of supply voltage dependence and 60 dB PSRR at 1 MHz without trimming or extra circuits for the curvature compensation. The entire circuit occupies 0.027 mm² of die area and consumes from a 1.2 V supply voltage at room temperature. Twenty chips are tested to show the robustness of the topology and the measurement results are compared with Monte Carlo simulation and analysis.     

An ultra-low-power CMOS voltage reference generator based on body bias technique

A CMOS voltage reference, based on body bias technique, has been proposed and simulated using SMIC 0.18 μm CMOS technology in this paper. The proposed circuit can achieve a temperature coefficient of 19.4 ppm/°C in a temperature range from −20 °C to 80 °C, and a line sensitivity of 0.024 mV/V in a supply voltage range from 0.85 V to 2.5 V, without the use of resistors and any other special devices such as thick gate oxides MOSFETs with higher threshold voltage. The supply current at the maximum supply voltage and at 27 °C is 214 nA. The power supply rejection ratio without any filtering capacitor at 10 Hz and 10 kHz are −88.2 dB and −36 dB, respectively.     

A novel current reference based on subthreshold MOSFETs with high PSRR

A novel current reference based on subthreshold MOSFETs with high power supply rejection ratio (PSRR) is presented. The proposed circuit takes full advantages of the I-V transconductance characteristics of MOSFET operating in the subthreshold region and the enhancement pre-regulator with the high gain negative feedback loop for the current reference core circuit. The proposed circuit, designed with the SMIC 0.18 μm standard CMOS logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient of 2.5×10⁻⁴ μA/°C in the temperature range of −40 to 150 °C at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about −126 dB at dc frequency and remains −92 dB at the frequency higher 1 MHz. The proposed circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.     

Generating sub-1V reference voltages from a resistorless CMOS bandgap reference circuit by using a piecewise curvature temperature compensation technique

A piecewise curvature compensated CMOS voltage reference that is able to generate a sub-1V reference voltage is presented. The presented voltage reference circuit is operated at a minimum operating voltage of 1.5 V (theoretically 1.408 V) and generates a stable 0.658 V reference voltage with a temperature coefficient of 9.617 ppm/°C over the temperature range of −10 °C to 130 °C. When implemented in a 0.18 μm CMOS technology, the presented design occupies a compact silicon area of 0.022 mm². Spectre SPICE simulation showed that the presented design achieves a line regulation of 0.89%, a power supply rejection ratio of −42.3 dB, a power consumption of 0.449 mW at 1.8 V power supply and a high immunity to process variation.     

A high-efficiency DC-DC buck converter for sub-2×VDD power supply

This paper presents a DC-DC step-down converter, which can accommodate the range of power supply voltage from VDD to sub-2×VDD. By utilizing stacked power MOSFETs, a voltage level converter, a detector and a controller, the proposed design is realized by a typical 1P6M CMOS process without using any high voltage process to resolve gate-oxide reliability and leakage current problems. The core area of the proposed design is less than 0.184 mm², while the power supply range is up to 5 V. Since the internal reference voltage is 1.0 V, it can increase the output regulation range. The proposed design attains very high conversion efficiency to prolong the life time of battery-based power supply. Therefore, it can be integrated in a SOC (system-on-chip) to provide multiple supply voltage sources.     

An ultra-low power integer-N frequency synthesizer for MICS transceivers

The ultra-low power frequency synthesizer for the transceivers used in the application of Medical Implantable Communication Services (MICS) is presented. The MICS band is from 402 to 405 MHz. Each channel spacing is 300 kHz. Integer-N architecture is used to implement the frequency synthesizer. The post layout simulations show that the total power consumption of the system is less than at 1.2 V power supply. The gains of the charge pump and voltage controlled oscillator (VCO) are and 50 MHz/V, respectively. The standard 300 kHz external clock is used as the reference. The design is carried out in the IBM 90 nm 9LPRF CMOS technology.     

A CMOS piecewise curvature-compensated voltage reference

This paper presents a novel approach to the design of a high-precision CMOS voltage reference. The proposed circuit utilizes MOS transistors instead of bipolar transistors to generate positive and negative temperature coefficient (TC) currents summed up to a resistive load to generate low TC reference voltage. A piecewise curvature-compensation technique is also used to reduce the TC of the reference voltage within a wider temperature range. The output reference voltage can be adjusted in a wide range according to different system requirements by setting different parameters such as resistors and transistor aspect ratios. The proposed circuit is designed for TSMC 0.6 μm standard CMOS process. Spectre-based simulations demonstrate that the TC of the reference voltage is 4.3 ppm/°C with compensation compared with 107 ppm/°C without compensation in the temperature ranges from −15 to 95 °C using a 1.5 V supply voltage.     

A CMOS threshold voltage reference source for very-low-voltage applications

This paper describes a CMOS voltage reference that makes use of weak inversion CMOS transistors and linear resistors, without the need for bipolar transistors. Its operation is analogous to the bandgap reference voltage, but the reference voltage is based on the threshold voltage of an nMOS transistor. The circuit implemented using 0.35 μm n-well CMOS TSMC process generates a reference of 741 mV under just 390 nW for a power supply of only 950 mV. The circuit presented a variation of 39 ppm/°C (after individual resistor trimming) for the −20 to +80 °C temperature range, and produced a line regulation of 25 mV/V for a power supply of up to 3 V.     

Design and implementation of a 0.8 V input, 84% duty cycle, variable frequency step-up converter

A 0.8 V input, 84% duty cycle, variable frequency CMOS DC-DC step-up converter with integrated power switches has been presented in this paper. The converter has the properties of both the current mode and hysteric control mode operations. The inductor charging time of the topology is designed to be inversely proportional to the input voltage and as a result the inductor current disturbance dies out immediately. Hence, no external components and extra I/O pins are required for the compensation of the current loop. The step-up converter has been fabricated with a standard pseudo BiCMOS process. Special MOS device of threshold voltage 0.5 V and start-up circuitries enable the converter to start from a voltage as low as 0.8 V. The real time data show that the converter can boost 0.8 V to as high as 5 V, which makes it suitable for low voltage applications. The efficiency of the chip has been found over 75 % for the entire load range from 10 to 100 mA.     

Current-mode full-duplex (CMFD) signaling for high-speed chip-to-chip interconnect

In this work we propose a new current-mode full-duplex (CMFD) signaling scheme for high-speed chip-to-chip data communication. In this scheme, all the internal nodes of the link are maintained at low-impedance, facilitating high-speed data communication. A new hybrid circuit topology required for separating the inbound signal from the outbound signal is presented. The proposed current-mode hybrid is realized by a source-coupled main driver, a scaled down replica stage and a common-gate (CG) transimpedance amplifier (TIA). Detailed design, analysis, noise and jitter characterization of the proposed hybrid is presented. The hybrid is realized in 1.8 V, digital CMOS technology. Using this hybrid circuit topology, CMFD signaling over a chip-to-chip interconnect is demonstrated. The post-layout performance shows 8 Gb/s data transfer rate over a FR4 PCB trace of length 7.5 in. for a target bit-error rate (BER) of 10⁻¹². The FR4 PCB trace is modeled by measured 4-port S-parameters in the frequency range from 100 MHz to 20 GHz. The input-referred noise current of the receiver and output-noise voltage of transmitter are and 5.34 mV, respectively. The standalone power consumption of the hybrid is 14.64 mW.     

Low-voltage nanopower clock generator for RFID applications

The design of an on-chip RC-based oscillator, implemented in a standard BiCMOS process, without any external component, is presented. The proposed oscillator provides a clock signal at a frequency of 50 kHz with a temperature coefficient smaller than 0.3%/^°C over a temperature range from 0 to , without any external trimming. The proposed oscillator operates with a supply voltage of 0.8 V and has a power consumption of at room temperature. The chip area is .     

High-speed CMOS unity-gain current amplifier

A high-performance CMOS unity-gain current amplifier is proposed. The solution adopts two feedback loops to reduce the input resistance and a nested-Miller technique to provide frequency compensation. A design example using a 0.8 μm process and a 2 V supply is given and SPICE simulations show a bandwidth of 75 MHz, no slew-rate limitations and a settling time better than 50 ns, irrespective of the current amplitude. Input and output resistances are better than 0.1 Ω and 15 MΩ, respectively. The input-referred white noise spectral density is .     

A high precision low dropout regulator with nested feedback loops

A high precision low dropout regulator (LDO) with nested feedback loops is proposed in this paper. By nesting a zero-tracking compensation loop inside of the negative feedback loop comprising an error amplifier, the independence of off-chip capacitor and effective series resistance (ESR) is ensured for different load currents and operating voltages. This circuit is designed and fabricated using a standard CMOS process. The die area is a . The measurement results show that the total error of the output voltage caused by line and load variations is less than ±3% in low quiescent current (Iddq) or low voltage scenarios. Besides, the smallest dropout of the LDO, 0.11 V, while the output current is 165 mA, the output load is and 20 in parallel.     

A low-power 2 GHz data conversion using delta modulation for portable application

This paper describes a new bandpass delta modulator dedicated to low-power and portable applications. The proposed modulator can convert a wide range of frequency, 500 MHz to 2.6 GHz, into an IF as low as 20 MHz by using under-sampling. Design issues in excess loop delay, linearity, and high frequency operation are discussed and some circuit solutions are proposed for a continuous-time modulator. Simulation and experimental results obtained using CMOS IBM technology are presented and discussed. Total power consumption is 37.2 mW when the voltage supply is 1.2 V.     

High-precision curvature-compensated CMOS band-gap voltage and current references

Precise CMOS band-gap voltage and current references which uses the difference of MOS source-gate voltages to perform efficient curvature compensation are proposed and analyzed. Applying the developed design strategies, band-gap voltage references (BVR) with a temperature drift below 10 ppm/°C and a power-supply drift below 10 ppm/V can be realized. For band-gap current references, both drifts can be under 15 ppm. Experimental BVR chip shows an average drift of 5.5 ppm/°C from -60°C to 150°C and 25 V/V for supply voltages from 5 to 15 V at 25°C. Due to the use of the novel curvature-compensation technique, the circuit structure of the proposed references is simple and both chip area and power consumption are small.This research was supported by the National Science Council, ROC under contract NSC79-0404-E009-30.