4H-SiC隐埋沟道MOSFET迁移率的研究

研究了几种因素对4H-SiC隐埋沟道MOSFET沟道迁移率的影响.提出了一个简单的模型用来定量分析串联电阻对迁移率的影响.串联电阻不仅会使迁移率降低,还会使峰值场效应迁移率所对应的栅压减小.峰值场效应迁移率和串联电阻的关系可用一个二次多项式来准确描述.详细分析了均匀分布和不均匀分布的界面态对场效应迁移率的影响.对于指数分布的界面态,低栅压下界面态的影响基本上可以忽略不计,随着栅压的增加,界面态的影响越来越显著.     

Influence of source-drain series resistance on MOSFET field-effect mobility

A simple but general model for explaining the series resistance dependence of transconductance and field-effect mobility is developed in the letter. This model, which enables a quantitative analysis of series resistance effects on the maximum mobility and the corresponding gate voltage, has been successfully tested on short-channel MOSFETs with various channel lengths and external series resistances.     

Extraction of the series resistance and the effective mobility in enhancement MOSFETs from weak to strong inversion using a single transistor

This work presents a new approach for the simultaneous determination of the effective channel mobility and the parasitic series resistance as a function of gate voltage in enhancement MOSFETs. The proposed method is applicable for short channel devices as well as long channel ones. It also takes into consideration the effect of interface traps and the dependence of the effective channel length on gate bias. The method is based on the measurement of the dynamic transconductance, gate-channel capacitance and the ohmic region drain current all on a single MOS transistors. The obtained results suggest a peak for the effective mobility versus gate voltage near threshold. The parasitic series resistance for short channel devices shows only slight dependence on the gate bias in the whole strong inversion region. On the contrary, for long channel devices, the series resistance significantly decreases with increasing gate voltage at the onset of strong inversion and then tends to level off as the device is pushed deeper in strong inversion.     

Gate voltage and geometry dependence of the series resistance and of the carrier mobility in FinFET devices

In this work, we investigate the gate voltage and the geometry dependence of the series resistance and the carrier mobility in n-type and p-type FinFETs. A significant gate voltage dependence of the series resistance is observed, which is ascribed to the conduction modulation of the LDD region under the gate. The fin width dependence of the series resistance is investigated and two simple methods of normalization are compared. Mobility data in narrow (W_fin = 30 nm) and wide fin (W_fin = 3μm) have been compared. N-FinFETs show a higher mobility compared to the p-FinFET in both cases, but for narrow fins the difference is reduced since the mobility on the sidewalls improves for holes but degrades for electrons. We show that without taking into account the gate voltage dependence of the series resistance the mobility is significantly underestimated.     

High field-effect mobility in n-channel Si face 4H-SiC MOSFETs with gate oxide grown on aluminum ion-implanted material

We report investigations of Si face 4H-SiC MOSFETs with aluminum (Al) ion-implanted gate channels. High-quality SiO/sub 2/-SiC interfaces are obtained both when the gate oxide is grown on p-type epitaxial material and when grown on ion-implanted regions. A peak field-effect mobility of 170 cm/sup 2//V/spl middot/s is extracted from transistors with epitaxially grown channel region of doping 5/spl times/10/sup 15/ cm/sup -3/. Transistors with implanted gate channels with an Al concentration of 1/spl times/10/sup 17/ cm/sup -3/ exhibit peak field-effect mobility of 100 cm/sup 2//V/spl middot/s, while the mobility is 51 cm/sup 2//V/spl middot/s for an Al concentration of 5/spl times/10/sup 17/ cm/sup -3/. The mobility reduction with increasing acceptor density follows the same functional relationship as in n-channel Si MOSFETs.     

A physical model on electron mobility in InGaAs nMOSFETs with stacked gate dielectric

An inversion-channel electron mobility model for InGaAs n-channel metal–oxide-semiconductor field-effect transistors (nMOSFETs) with stacked gate dielectric is established by considering scattering mechanisms of bulk scattering, Coulomb scattering of interface charges, interface-roughness scattering, especially remote Coulomb scattering and remote interface-roughness scattering. The simulation results are in good agreement with the experimental data. The effects of device parameters on degradation of electron mobility, e.g. interface roughness, dielectric constant and thickness of high-k layer/interlayer, and the doping concentration in the channel, are discussed. It is revealed that a tradeoff among the device parameters has to be performed to get high electron mobility with keeping good other electrical properties of devices.     

Electrical characterization of polymer-based FETs fabricated by spin-coating poly(3-alkylthiophene)s

The current-voltage (I-V) characteristics of two different polymer thin-film transistors (TFTs), based on spin-coating of poly(3-hexylthiophene)-P3HT and poly(3-hexadecylthiophene)-P3HDT, are studied. A model is developed to interpret the results and to explain the differences between these two polymers. Various parameters of the semiconducting polymers, including bulk mobility, field-effect mobility, trap density, and unintentional dopant concentration are estimated. The model takes into account the domination of the bulk current over the channel current in the subthreshold regime as well as the effects of the depletion layer as parasitic resistances in series with the channel resistance. Furthermore, the effects of the films thickness on the electrical characteristics of these TFTs are discussed. Compared to the P3HT, the P3HDT-based TFT has a lower subthreshold slope, higher on current ratio, and higher field-effect mobility.     

Source/Drain Series-Resistance Effects in Amorphous Gallium–Indium Zinc-Oxide Thin Film Transistors

In this letter, we investigated the effects of source/drain series resistance on amorphous gallium-indium-doped zinc-oxide (a-GIZO) thin film transistors (TFTs). A linear least square fit of a plot of the reciprocal of channel resistance versus gate voltage yields a threshold voltage of 3.5 V and a field-effect mobility of about 13.5 cm²/Vldrs. Furthermore, in a-GIZO TFTs, most of the current flows in the distance range of 0-0.5 mum from the channel edge and shorter than that in a-Si:H TFTs. Moreover, unlike a-Si:H TFTs, a-GIZO TFTs did not show an intersection point, because they did not contain a highly doped ohmic (n+) layer below the source/drain electrodes.     

Charge-sheet model for silicon carbide inversion layers

The charge-sheet model for metal-oxide-semiconductor (MOS) inversion layers is extended to silicon carbide. The generalized model is based on an analytical solution of the Poisson equation for the case of incomplete ionization of dopant impurities and incorporating Fermi-Dirac statistics. The results are compared with the conventional charge-sheet model which assumes complete impurity ionization and nondegenerate statistics. It is found that, at room temperature and for gate voltages in weak and moderate inversion, the present model predicts higher inversion-layer charge density at a given gate voltage. However, the relationship between the inversion charge and the surface Fermi potential is essentially independent of the degree of impurity ionization. In strong inversion or at temperatures above ~600 K, the differences between the two models are small. A formula is given for the threshold voltage as a function of the impurity ionization energy. The effects of several different interface state energy distributions on inversion charge are investigated. It is found that a slowly-varying interface-state density has an effect on threshold voltage of a MOSFET similar to that of a fixed oxide charge, while an interface-state density that increases at least exponentially with energy has the effect of lowering the field-effect mobility and transconductance     

Effects of semiconductor/dielectric interfacial properties on the electrical performance of top-gate organic transistors

We investigated the effects of varying the properties of the interface between a semiconductor P3HT layer and a dielectric Cytop™ layer on the performances of the resulting transistor devices by comparing the mobilities of devices prepared with bottom gate/bottom contact or top gate/bottom contact architectures. The reduced channel roughness that arose from the thermal annealing step dramatically enhanced the field-effect mobility, yielding the highest mobility yet obtained for a top-gate transistor: 0.12 cm²/V s. High-performance OFETs may be fabricated by controlling the channel roughness and the properties of the interface between the semiconductor and the gate dielectric.     

Improving FET Switch Linearity

RF field-effect transistors, especially pseudomorphic high-electron mobility transistors (pHEMTs), are commonly used as switches in communication applications. These small high-speed devices are vital for routing and conveying signals in such uses. The important characteristics of pHEMTs, besides their small size, are their high-frequency capability, insertion loss, isolation, power handling, switching speed, and linearity. A topology using a pair of simple but modified series and shunt elements was designed to improve upon the linearity of an RF switch. Each element of the switch was composed of a single, unbiased, but relatively long pHEMT, which was designed for the test. By shifting the position of the gate asymmetrically toward the source terminal in these transistors, it was found that the linearity was improved without cost to other performance parameters     

High mobility,low voltage polymer transistor

We introduce a polymer transistor that operates with low supply voltage and yet has a field-effect mobility higher than the mobilities reported for low voltage polymer transistors. A simple plasma oxidation of the gate metal to form a thin (3.74 nm) top metal oxide layer in the gate metal is involved in the fabrication that acts as the gate dielectric. With ultrathin gate dielectrics, the variation in the dielectric thickness and the surface roughness scattering can severely limit the mobility attainable. The plasma oxidation under certain conditions produces a very smooth oxide surface, leading to the high mobility.     

Arbitrary Density of States in an Organic Thin-Film Field-Effect Transistor Model and Application to Pentacene Devices

We present a modular numerical model for organic thin-film field-effect transistors (OTFTs) that allows for an arbitrary density of states to be independently defined for the semiconductor bulk and the semiconductor surface next to the gate insulator. We can derive the surface charge density dependence on the interface field as well as the space-charge-limited current characteristics. Together with a model of the contacts, we arrive at a physical model that is applied to a series of OTFTs in staggered inverted (top contact) geometry with various gate insulator treatments     

2-µm Gate-length enhancement mode InGaAs/InP:Fe-JFET's with high transconductance

Investigations of enhancement mode InGaAs junction field-effect transistors (JFET's) grown on InP:Fe-substrate by liquid-phase epitaxy (LPE) are reported. The JFET's with 2-µm gate length and 190- µm gate width show a threshold voltage of 0.4 V, a low drain current of < 10 µA at 0-V gate-source voltage and a maximum transconductance of 105 mS/mm. The measured transconductances of enhancement mode InGaAs/InP:Fe JFET's with different gate lengths but with the same gate width and threshold voltage decrease proportional to the inverse gate length as expected from a constant drift mobility FET model.     

High-performance RSD poly-Si TFTs with a new ONO gate dielectric

This paper developed a novel polycrystalline silicon (poly-Si) thin-film transistor (TFT) structure with the following special features: 1) a new oxide-nitride-oxynitride (ONO) multilayer gate dielectric to reduce leakage current, improved breakdown characteristics, and enhanced reliability; and 2) raised source/drain (RSD) structure to reduce series resistance. These features were used to fabricate high-performance RSD-TFTs with ONO gate dielectric. The ONO gate dielectric on poly-Si films shows a very high breakdown field of 9.4 MV/cm, a longer time dependent dielectric breakdown, larger Q/sub BD/, and a lower charge-trapping rate than single-layer plasma-enhanced chemical vapor deposition tetraethooxysilane oxide or nitride. The fabricated RSD-TFTs with ONO gate dielectric exhibited excellent transfer characteristics, high field-effect mobility of 320 cm/sup 2//V/spl middot/s, and an on/off current ratio exceeding 10/sup 8/.     

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

有机场效应晶体管最新实验研究进展

介绍了近两年新报道的有机半导体材料,列举了其场效应性能参数;综述了有机场效应晶体管(OFET)在器件结构上的改进,重点阐述了基于常见有机功能层材料富勒烯及其衍生物、并五苯、聚3-己基噻吩的OFET对栅介质层及有机功能层与电极的界面的改进,讨论了器件结构改进对OFET阈值电压、开关比、载流子迁移率的影响;介绍了衬底温度、退火处理对OF-ET性能的影响。最后,针对有机场效应晶体管研究现状,指出未来研究中应注重开发高迁移率、高薄膜稳定性的有机功能材料和高介电常数、高成膜质量的有机栅介质材料,继续优化器件结构,改进制备工艺以提高器件性能。     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

Determination of mobility in modulation-doped FET's using magnetoresistance effect

A simple measurement technique based on the magnetoresistance effect is developed to obtain the differential and average mobilities of modulation-doped field-effect transistors (MODFET's) with respect to gate bias voltage. The effect of parasitic series resistances can be neglected by using a low magnetic field. The measurement is not affected by parasitic gate capacitance and therefore constitutes an effective tool for characterizing fully processed ultra-short gate-length MODFET's.     

Air stable C60 based n-type organic field effect transistor using a perfluoropolymer insulator

Air stable n-type organic field effect transistors (OFETs) based on C₆₀ are realized using a perfluoropolymer as the gate dielectric layer. The devices showed the field-effect mobility of 0.049 cm²/V s in ambient air. Replacing the gate dielectric material by SiO₂ resulted in no transistor action in ambient air. Perfluorinated gate dielectric layer reduces interface traps significantly for the n-type semiconductor even in air.