Board level reliability of PBGA using flex substrate

Assurance of board level reliability is necessary and required for adopting any new packages into products. This paper presents board level reliability test results of a flex substrate BGA under thermal and bend cyclic tests. It is well known that solder joint reliability is affected by many factors, such as the size of chip, joint stand-off height, pad design, test board surface finish, substrate gold plating thickness and the utilization of underfill material, etc. However, most of the works have been conducted are BGA on rigid substrates. In this work, thermal cyclic test is performed to re-examine these factors using package housed on a flex substrate. Bending test with two deflections is also performed to investigate solder joint fatigue life and failure modes under mechanically repetitive loading.Two-parameter Weibull model is used to analyze joint fatigue life. Failure analysis is conducted and discussed for each case. Under temperature cycling test, chip size, polyimide thickness and underfill material utilization were found to have significant impacts on joint fatigue life, especially the effect of applying underfill material to the joint. Epoxy thickness was found to have little effect on the joint fatigue life for this case.The effects of test board surface finish and substrate gold plating thickness on the joint fatigue life were found coupled. The term “substrate” here refers to the chip carrier, while the “board” here refers to motherboard, which is the board to assemble test vehicles on. The gold thickness here all refers to the electrolytic gold plating on the substrate. Using organic solderability preservative boards, substrate gold plating thickness affects joint fatigue life slightly, but with Au–Ni test boards, the effect is tremendous. The difference is due to different intermetallic compounds (IMC) formed. In other words, different IMC systems are formed due to different combination of test board surface finish and substrate gold plating thickness. As a result, different IMC induces different failure modes. The joint fatigue life under cyclic bend test with different deflections is also probed and shown. The corresponding failure modes are also discussed.     

CQFP器件板级温循可靠性的设计与仿真

温度循环是考核封装产品板级可靠性的重要试验之一。陶瓷四边引脚扁平封装(CQFP)适用于表面贴装,由于陶瓷材料与PCB热膨胀系数的差异,温循过程中引线互联部分产生周期性的应力应变,当陶瓷壳体面积较大时,焊点易出现疲劳失效现象。CQFP引线成形方式分顶部成形和底部成形两类。针对CQFP引线底部成形产品在板级温循中出现的焊接层开裂现象,采用有限元方法对焊接层的疲劳寿命进行了预测分析。采用二次成形方法对引线进行再次成形以缓解和释放热失配产生的应力。仿真和试验结果显示,引线二次成形有利于提高焊接层的温循疲劳寿命。与引线底部成形相比,当引线采用顶部成形时,焊接层的温循疲劳寿命显著提高。     

Board level investigation of BGA solder joint deformation strength

In this paper we present a method to determine the stress in BGA solder joints on complex, real assembled circuit boards.To be able to investigate the mechanical effects of post-reflow assembly within the solder joints of BGA components, it is necessary to undertake a mechanical investigation at board level by taking into consideration the effect of the adjacent components and the interconnection layer layouts.In our project, we have developed a method of how to investigate the board level deformation strength of BGA joints. The elastic properties of a real assembled circuit board and of a circuit bare board are measured; an FEM model is then created, both of the bare board and of the assembled printed circuit board taking into account the layout of the interconnection layers. The advantage of this PCB FEM model is that the deformation of a PCB of any size and for any load can be calculated quickly using any ordinary computer. In our project, we also have created another detailed FEM model for the BGA solder joints.Using the constructed FEM models, we are able to determine the stress in BGA solder joints on a real electronic product for a typical type of load (i.e. bending of PCB) thereby verifying our method. Since the simulated results correspond well to previous literature written on this topic, we consider that our method is appropriate for calculating stress in the solder joints of multi-lead components on complex, fully assembled circuit boards.     

Board level solder joint reliability modeling and testing of TFBGA packages for telecommunication applications

For thin-profile fine-pitch BGA (TFBGA) packages, board level solder joint reliability during the thermal cycling test is a critical issue. In this paper, both global and local parametric 3D FEA fatigue models are established for TFBGA on board with considerations of detailed pad design, realistic shape of solder joint, and nonlinear material properties. They have the capability to predict the fatigue life of solder joint during the thermal cycling test within ±13% error. The fatigue model applied is based on a modified Darveaux’s approach with nonlinear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during the thermal cycling test. For the test vehicles studied, the maximum SED is observed at the top corner of outermost diagonal solder ball. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house BGA thermal cycling test data. Subsequently, design analysis is performed to study the effects of 14 key package dimensions, material properties, and thermal cycling test condition. In general, smaller die size, higher solder ball standoff, smaller maximum solder ball diameter, bigger solder mask opening, thinner board, higher mold compound CTE, smaller thermal cycling temperature range, and depopulated array type of ball layout pattern contribute to longer fatigue life.     

Warpage-induced lithographic limitations of FR-4 and the need for novel board materials for future microvia and global interconnect needs

The effect of warpage on lithographic capabilities of organic circuit boards with multilayered thin film buildup was investigated. Two to six epoxy layers were built on various candidate boards to characterize the warpage and correlate it with analytical models. Underlying mechanisms were investigated and novel parameters defined to correlate warpage with photodefinition of ultrafine lines and vias on the board. Based on the experiments, warpage specifications for the multifunctional multilayered requirements in a proposed system-on-package (SOP) structure were defined. Experimentally validated FEM models were used to estimate the warpage during the multilayered buildup. Results show that FR-4 is not suitable for future high-density packaging needs and underscore the need for stiffer ceramic-based circuit board materials as replacement for FR-4     

电路板焊点在工程环境条件下寿命分析

在电子设备寿命周期中．要经历各种环境载荷。我们需要综合号虑载荷对电子设备可靠性和寿命的影响。在该文中．以一块电路板为案例。建立整板模型．然后设定边界、分别加载温度和随机振动载荷。并利用有限元分析工具ANSYS计算,得出应力应变云值。最后基于Coffin—Manson疲劳寿命模型和线性叠加模型,分析和预测热循环和随机振动条件下．器件焊点疲劳寿命,为整板器件可靠性设计提供参考,     

The effects of underfill on the reliability of flip chip solder joints

Thermal fatigue damage of flip chip solder joints is a serious reliability concern, although it usually remains tolerable with the flip chip connections (of smaller chips) to ceramic boards as practiced by IBM for over a quarter century. However, the recent trend in microelectronics packaging towards bonding large chips or ceramic modules to organic boards means a larger differential thermal expansion mismatch between the board and the chip or ceramic module. To reduce the thermal stresses and strains at solder joints, a polymer underfill is customarily added to fill the cavity between the chip or module and the organic board. This procedure has typically at least resulted in an increase of the thermal fatigue life by a factor of 10, as compared to the non-underfilled case. In this contribution, we first discuss the effects of the underfill to reduce solder joint stresses and strains, as well as underfill effects on fatigue crack propagation based on a finite element analysis. Secondly, we probe the question of the importance of the effects of underfill defects, particularly that of its delamination from the chip side, on the effectiveness of the underfill to increase thermal fatigue life. Finally, we review recent experimental evidence from thermal cycling of actual flip chip modules which appears to support the predictions of our model.     

Board level reliability of a stacked CSP subjected to cyclic bending

Second (board) level reliability of a stacked chip scale package (SCSP) under cyclic bending is conducted to evaluate the structural integrity of solder interconnects. The test vehicle (on-board SCSP) is simply supported at both ends and subjected to repetitive deflection in the middle (three-point bend). Cyclic deformation histories such as sinusoidal, triangular, and square waveforms are examined. Tremendous joint damage is observed as square-wave loading history was applied. Approximately 80% fatigue life degradation is found by bending several thermally aged samples having Ni/Au surface finish on Cu pads of package substrates and printed circuit boards. The observed failure mode is a brittle type fracture of intermetallic compound system, which is also known as effects of solder embrittlement.Measured fatigue life is characterized by two-parameter Weibull model with cumulative damage plot for each test condition. In addition to the comparisons of characteristic fatigue life for various package configuration and cyclic bending conditions, failure analysis is also employed to identify failure sites and mechanisms such as crack initiation and continuous growth to the complete fracture of solder joints.     

Experimental and statistical analyses of surface-mount technologyPLCC solder-joint reliability

The mechanical integrity of surface-mount technology (SMT) plastic leaded chip carrier (PLCC) solder joints has been studied by a four-point mechanical flexure fatigue test. The effects of printed circuit board (PCB) pad surface composition and testing temperature on solder-joint reliability are emphasized. Three sets of PCBs have been tested, one with Cu-Ni-Sn pad surface metallurgy, one with Cu-Ni-Au, and one with SMOBC/SSC (solder mask over bare copper selective solder coating). The solder composition was the 63 wt.%Sn/37 wt.%Pb eutectic. A two-parameter Weibull distribution was used for the lifetime model for these three products. The uniformity, quality, reliability, and a comparison of these products are discussed. The joints formed on Cu-Ni-Au and SMOBC boards were appreciably more reliable than those formed on the Cu-Ni-Sn board     

Solder joint reliability of indium-alloy interconnection

Recent high-density very large scale integrated (VLSI) interconnections in multichip modules require high-reliability solder interconnection to enable us to achieve small interconnect size andlarge number of input/output terminals, and to minimize soft errors in VLSIs induced by α-particle emission from solder. Lead-free solders such as indium (In)-alloy solders are a possible alternative to conventional lead-tin (Pb-Sn) solders. To realize reliable interconnections using In-alloy solders, fatigue behavior, finite element method (FEM) simulations, and dissolution and reaction between solder and metallization were studied with flip-chip interconnection models. We measured the fatigue life of solder joints and the mechanical properties of solders, and compared the results with a computer simulation based on the FEM. Indium-alloy solders have better mechanical properties for solder joints, and their flip-chip interconnection models showed a longer fatigue life than that of Pb-Sn solder in thermal shock tests between liquid nitrogen and room temperatures. The fatigue characteristics obtained by experiment agree with that given by FEM analysis. Dissolution tests show that Pt film is resistant to dissolution into In solder, indicating that Pt is an adequate barrier layer material for In solder. This test also shows that Au dissolution into the In-Sn solder raises its melting point; however, Ag addition to In-Sn solder prevents melting point rise. Experimental results show that In-alloy solders are suitable for fabricating reliable interconnections.     

Solder joint fatigue life of fine pitch BGAs – impact of design and material choices

The impact of design and material choices on solder joint fatigue life for fine pitch BGA packages is characterized. Package variables included die size, package size, ball count, pitch, mold compound, and substrate material. Test board variables included thickness, pad configuration, and pad size. Three thermal cycle conditions were used.Fatigue life increased by up to 6× as die size was reduced. For a given die size, fatigue life was up to 2× longer for larger packages with more solder balls. Mold compounds with higher filler content reduced fatigue life by up to 2× due to a higher stiffness and lower thermal expansion coefficient. Upilex S tape with punched holes gave 1.15× life improvement over Kapton E tape with etched holes. Once optimized, tape-based packages have equal board level reliability to laminate-based packages.Solder joint fatigue life was 1.2× longer for 0.9 mm thick test boards compared to 1.6 mm thick boards due to a lower assembly stiffness. The optimum PCB pad design depends on failure location. For CSP applications, NSMD test board pads give up to 3.1× life improvement over SMD pads. For a completely fan-out design, there was a 1.6× acceleration factor between −40125°C, 15 min ramps, 15 min dwells and 0100°C, 10 min ramps, 5 min dwells.     

Thermo-mechanical finite element analysis in a multichip build up substrate based package design

This paper presents a thermo-mechanical analysis of a multichip module (MCM) package design, with emphasis on the package warpage, thermally induced stress and the second level solder joint reliability. The MCM package contains four flip chips which are mounted on a build up substrate. First, the effect of the positioning of four silicon dice within the MCM package on the warpage of the package is studied. Second, the effect of package dimensions (the heat spreader thickness, the structural adhesive thickness and the substrate thickness) on the maximum residual stress as well as the warpage of the package is performed. Finally, this paper presents a 3D sliced model for solder joint reliability of the MCM assembly. A creep constitutive relation is adopted for the 63Sn/37Pb solder to account for its time and temperature dependence in thermal cycling. The fatigue life of solder joint is estimated by the Darveaux's approach. A series of parametric study is performed by changing the package dimensions. The results show that the largest die tends to experience highest stresses at its corner and has more influence on the warpage of the package than smaller dice. The results also show the most sensitivity factors that affect the package warpage and the second level solder joint reliability are the substrate thickness and the heat spreader thickness. The structural adhesive thickness has no major effect on the package warpage, the maximum von Mises stress of the package and the second level solder joint reliability.     

Board level solder joint reliability analysis of stacked die mixed flip-chip and wirebond BGA

Stacked die BGA has recently gained popularity in telecommunication applications. However, its board level solder joint reliability during the thermal cycling test is not as well-studied as common single die BGA. In this paper, solder joint fatigue of lead-free stacked die BGA with mixed flip-chip (FC) and wirebond (WB) interconnect is analyzed in detail. 3D fatigue model is established for stacked die BGA with considerations of detailed pad design, realistic shape of solder ball, and non-linear material properties. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. Based on the FC–WB stack die configuration, the critical solder ball is observed located between the top and bottom dice corner, and failure interface is along the top solder/pad interface. The modeling predicted fatigue life is first correlated to the thermal cycling test results using modified correlation constants, curve-fitted from in-house lead-free TFBGA46 (thin-profile fine-pitch BGA) thermal cycling test data. Subsequently, design analyzes are performed to study the effects of 20 key design variations in package dimensions, material properties, and thermal cycling test conditions. In general, thinner PCB and mold compound, thicker substrate, larger top or bottom dice sizes, thicker top die, higher solder ball standoff, larger solder mask opening, smaller PCB pad size, smaller thermal cycling temperature range, longer ramp time, and shorter dwell time contribute to longer fatigue life. SnAgCu is a common lead-free solder, and it has much better board level reliability performance than eutectic solder based on modeling results, especially low stress packages.     

湿热环境下倒装焊无铅焊点的可靠性

对板上倒装芯片底充胶进行吸湿实验,并结合有限元分析软件研究了底充胶在湿敏感元件实验标准MSL—1条件下吸湿和热循环阶段的解吸附过程,测定了湿热环境对Sn3.8Ag0.7Cu焊料焊点可靠性的影响,并用蠕变变形预测了无铅焊点的疲劳寿命。结果表明:在湿热环境下,底充胶材料内部残留的湿气提高了焊点的应力水平。当分别采用累积蠕变应变和累积蠕变应变能量密度寿命预测模型时,无铅焊点的寿命只有1740和1866次循环周期。     

Mechanical cycling fatigue of PBGA package interconnects

Increased packaging density in micro-electronic products has advantaged attach of BGA, micro-BGA, CSP, and DCA packages. These area array packages are assembled to circuit boards that are reduced in size and thickness, by necessity. These assemblies would include flexible thin laminate circuit boards with area array components attached by solder balls. In normal use, these assemblies would be subjected to numerous ultra-low frequency mechanical deflections; consider a keypad when the user enters telephone numbers. Most of the reliability studies of area array packages have dealt with temperature cycling induced fatigue. However, less attention has been paid to mechanical bending fatigue of these packages.A test method has been developed to elucidate the mechanical bending fatigue issues of BGA, micro-BGA, CSP, and DCA packages attached to printed circuit boards. Appropriate bending fatigue reliability models and their theoretical basis are being developed. The test method and preliminary mechanical cyclic fatigue data on a PBGA package will be presented as a function of printed circuit board thickness. Consideration will be given to fatigue fracture morphology and its relation to solder joint location and rate of crack growth.     

Solder joint reliability of TFBGA assemblies with fresh and reworked solder balls

In this article, the solder joint reliability of thin and fine-pitch BGA (TFBGA) with fresh and reworked solder balls is investigated. Both package and board level reliability tests are conducted to compare the solder joint performance of test vehicle with fresh and reworked solder balls. For package level reliability test, ball shear test is performed to evaluate the joint strength of fresh and reworked solder balls. The results show that solder balls with rework process exhibit higher shear strength than the ones without any rework process. The results also exhibit that the different intermetallic compound (IMC) formation at solder joints of fresh and reworked solder balls is the key to degradation of shear strength. For board level reliability tests, temperature cycling and bending cyclic tests are both applied to investigate the fatigue life of solder joint with fresh and reworked solder balls. It is observed that package with reworked solder ball has better fatigue life than the one with fresh solder ball after temperature cyclic test. As for bending cyclic test, in addition to test on as-assembled packages, reworked and fresh samples are subjected to heat treatment at 150 °C for 100 h prior to the bending cyclic test. The purpose is to let Au–Ni–Sn IMC resettle at solder joints of fresh solder ball and examine the influence of Au–Ni–Sn IMC on the fatigue life of solder joints (Au embrittlement effect). The final results confirm that reworked solder balls have better reliability performance than fresh one since Au embrittlement dose exist at fresh solder ball.     

Comprehensive board-level solder joint reliability modeling and testing of QFN and PowerQFN packages

For quad flat non-lead (QFN) packages, board-level solder joint reliability during thermal cycling test is a critical issue. In this paper, a parametric 3D FEA sliced model is established for QFN on board with considerations of detailed pad design, realistic shape of solder joint and solder fillet, and non-linear material properties. It has the capability to predict the fatigue life of solder joint during thermal cycling test within ±34% error. The fatigue model applied is based on a modified Darveaux’s approach with non-linear viscoplastic analysis of solder joints. A solder joint damage model is used to establish a connection between the strain energy density (SED) per cycle obtained from the FEA model and the actual characteristic life during thermal cycling test. For the test vehicles studied, the maximum SED is observed mostly at the top corner of peripheral solder joint. The modeling predicted fatigue life is first correlated to thermal cycling test results using modified correlation constants, curve-fitted from in-house QFN thermal cycling test data. Subsequently, design analysis is performed to study the effects of 17 key package dimensions, material properties, and thermal cycling test condition. Generally, smaller package size, smaller die size, bigger pad size, thinner PCB, higher mold compound CTE, higher solder standoff, and extra soldering at the center pad help to enhance the fatigue life. Comparisons are made with thermal cycling test results to confirm the relative trends of certain effects. Another enhanced QFN design with better solder joint reliability, PowerQFN, is also studied and compared with QFN of the same package size.     

Thermo-mechanical reliability analysis of a RF SiP module based on LTCC substrate

The RF SiP module based on LTCC substrate has attracted considerable attention in wireless communications for the last two decades. However, the thermo-mechanical reliability of this 3D LTCC architecture has not been well-studied as common as its traditional ceramic package structure. A practical RF SiP module based on LTCC substrate was presented and its thermo-mechanical reliability was analyzed in this paper, with emphasis on the reliability of heat reflow process, the operating state and fatigue of second-level solder joints. The configuration and assembly process of the SiP module were briefly introduced at first, and qualitative analysis was made according to the reliability problem that may occur in the manufacturing process and the operating state. Through FEM simulation, this paper studied the warpage and stress variation of the RF SiP module, as well as parametric studies of some key package dimensions. Solder joint reliability under temperature cycling condition was also analyzed in particular in this paper. The results show that for the heat reflow process and operating state, the maximum warpage is both on the top LTCC substrate, but the maximum stresses are on the outermost solder ball and the kovar column at the corner, respectively. There is a large residual stress on the critical solder ball at the end of the reflow process and the key package dimensions has little effect on it. The thickness of top LTCC substrate has a significant impact on the thermal deformation and thermal stress, followed by the height of kovar columns. The reason for the considerable thermal stress on the kovar column is the non-uniform of temperature distribution. The key to reducing thermal deformation and stress in the operating state is the employment of effective cooling measures. It is found by comparison that the reliability of critical solder joints can be greatly improved by adding suitable underfill.     

温度与振动耦合条件下的电路板级焊点失效模式与疲劳寿命分析

基于正交试验法研究不同温度与振动耦合条件下的板级焊点失效行为与模式,采用L₉（34）混合水平正交表设计了不同温度（T）、加速度功率谱密度（PSD）与频率（V）条件下的加速寿命试验,结果表明三者对焊点可靠性影响程度为T>PSD>V,且温度是影响焊点失效模式的主要因素,随温度的升高,焊点裂纹逐渐从近封装侧的界面金属化合物（IMC）层向钎体内部扩展,焊点失效模式从脆性断裂向韧性断裂演化.基于焊点失效数据分析,发现焊点疲劳寿命对数值与PCB板背侧最大应变范围存在关联关系,并采用多项式拟合的方法建立了焊点疲劳寿命模型,拟合结果显示,该模型能较好的评估温度与振动耦合条件下的焊点寿命,预测精度较高.