System-level power-aware design techniques in real-time systems

Power and energy consumption has recently become an important issue and consequently, power-aware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system, and networking layers. In this paper, we concentrate on power-aware design techniques for real-time systems. While the main focus is on hard real-time, soft real-time systems are considered as well. We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer-by-layer basis. We conclude with illustrative examples and open research challenges. This paper provides an overview of power-aware techniques for the real-time system engineer as well as an up-to-date reference list for the researcher.     

An Asynchronous Power Aware and Adaptive NoC Based Circuit

In complex embedded applications, optimisation and adaptation of both dynamic and leakage power have become an issue at SoC grain. A fully power-aware globally-asynchronous locally-synchronous network-on-chip (NoC) circuit is presented in this paper. Network-on-chip architecture combined with a globally-asynchronous locally-synchronous paradigm is a natural enabler for DVFS mechanisms. The circuit is arranged around an asynchronous network-on-chip providing scalable communication and a 17 Gb/s throughput while automatically reducing its power consumption by activity detection. Both dynamic and static power consumptions are globally reduced using adaptive design techniques applied locally for each synchronous NoC units. No fine control software is required during voltage and frequency scaling. Power control is localized and a minimal latency cost is observed.      

Power-Aware Data Management Based on Hybrid RAM-NVM Memory for Smart Bracelet

Wearable devices become popular because they can help people observe health condition. The battery life is the critical problem for wearable devices. The non-volatile memory (NVM) attracts attention in recent years because of its fast reading and writing speed, high density, persistence, and especially low idle power. With its low idle power consumption, NVM can be applied in wearable devices to prolong the battery lifetime such as smart bracelet. However, NVM has higher write power consumption than dynamic random access memory (DRAM). In this paper, we assume to use hybrid random access memory (RAM) and NVM architecture for the smart bracelet system. This paper presents a data management algorithm named bracelet power-aware data management (BPADM) based on the architecture. The BPADM can estimate the power consumption according to the memory access, such as sampling rate of data, and then determine the data should be stored in NVM or DRAM in order to satisfy low power. The experimental results show BPADM can reduce power consumption effectively for bracelet in normal and sleeping modes.     

A 2.4-Gsample/s DVFS FFT Processor for MIMO OFDM Communication Systems

This paper presents a new dynamic voltage and frequency scaling (DVFS) FFT processor for MIMO OFDM applications. By the proposed multimode multipath-delay-feedback (MMDF) architecture, our FFT processor can process 1-8-stream 256-point FFTs or a high-speed 256-point FFT in two processing domains at minimum clock frequency for DVFS operations. A parallelized radix-2⁴ FFT algorithm is also employed to save the power consumption and hardware cost of complex multipliers. Furthermore, a novel open-loop voltage detection and scaling (OLVDS) mechanism is proposed for fast and robust voltage management. With these schemes, the proposed FFT processor can operate at adequate voltage/frequency under different configurations to support the power-aware feature. A test chip of the proposed FFT processor has been fabricated using UMC 90 nm single-poly nine-metal CMOS process with a core area of 1.88 times1.88 mm² . The SQNR performance of this FFT chip is over 35.8 dB for QPSK/16-QAM modulation. Power dissipation of 2.4 Gsample/s 256-point FFT computations is about 119.7 mW at 0.85 V. Depending on the operation mode, power can be saved by 18%-43% with voltage scaling in TT corner.     

Low-Power Scan Testing: A Scan Chain Partitioning and Scan Hold Based Technique

Power consumption during scan testing operations can be significantly higher than that expected in the normal functional mode of operation in the field. This may affect the reliability of the circuit under test (CUT) and/or invalidate the testing process increasing yield loss. In this paper, a scan chain partitioning technique and a scan hold mechanism are combined for low power scan operation. Substantial power reductions can be achieved, without any impact on the test application time or the fault coverage and without the need to use scan cell reordering or clock and data gating techniques. Furthermore, the proposed design solution for scan power alleviation, permits the efficient exploitation of X-filling techniques for capture power reduction or the use of extreme (power independent) compression techniques for test data volume reduction.     

Architecture Design and Implementation of an Ad-Hoc Network for Disaster Relief Operations

This paper presents an ad-hoc sensor network especially developed for a disaster relief application that provides the rescue teams with a quickly deployable, cost-effective, and reliable tool to collect information about the presence of people in a collapsed building space and the state of the ruins. The hardware/software architecture of the wireless sensor nodes is developed for a low-cost design implementation. Energy efficiency is another objective of this paper, achieved by the combination of a low-power-mode algorithm and a power-aware routing strategy. A selected set of simulation studies indicate a reduction in energy consumption and a significant increase in node lifetime whereas network performance is not affected significantly. Finally, a lightweight management architecture is presented to facilitate autonomous management of ad-hoc sensor networks     

Early Stage Automatic Strategy for Power-Aware Signal Processing Systems Design

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology.     

一种新型时域波长交织的无源光网络

提出了一种基于时域波长交织的新型无源光网络架构,阐述了其基本工作原理,并给出了一种系统实现方案以改善光接入网物理层的安全性,并降低ONU的能耗。基于该架构,针对一个2通道,速率为1.25Gb/s的系统进行了仿真验证。结果表明,该架构在保证安全性和降低能耗的同时,能够满足光接入网的要求,实现20km的无误码传输。     

面向智能电网峰值负荷降低的用电数据分析

随着用电负荷需求不断增加所引发的峰值负荷过载问题,文中建立了智能家居(SH)和智能电网(SG)服务器之间数据通信模型,给出了配电网负荷需求管理的总体条件,并提出了一种面向智能电网(SG)的负荷数据分析DR管理方法,通过对用户的SH收集用电数据进行分析,设计了峰值负荷情况下的DR决策,分别从用户、电力公司和瞬时负荷变化三个角度设计了不同的峰值负荷降低算法。仿真结果表明,所提出的方法在很大程度上有效地降低了配电网的峰值负荷。     

Wake-up radio receiver based power minimization techniques for wireless sensor networks: A review

In a short period of time Wireless Sensor Networks (WSN) captured the imagination of many researchers with the number of applications growing rapidly. The applications span large domains including mobile digital health, structural and environmental monitoring, smart home, energy efficient buildings, agriculture, smart cities, etc. WSN are also an important contributor to the fast emerging Internet of Things infrastructure. Some of the design specifications for WSN include reliability, accuracy, cost, deployment versatility, power consumption, etc. Power consumption is (most often) the dominant constraint in designing such systems. This constraint has multi-dimensional implications such as battery type and size, energy harvester design, lifetime of the deployment, intelligent sensing capability, etc. Power optimization techniques have to explore a large design search space. Energy neutral system implementation is the ultimate goal in wireless sensor networks ensuring a perpetual/greener use and represents a hot topic of research. Several recent advances promise significant reduction of the overall sensor network power consumption. These advances include novel sensors and sensor interfaces, low energy wireless transceivers, low power processing, efficient energy harvesters, etc. This paper reviews a number of system level power management methodologies for Wireless Sensor Networks. Especially, the paper is focusing on the promising technology of nano-Watt wake-up radio receiver and its combination with mature power management techniques to achieve better performance. Some of the presented techniques are then applied in the context of low cost and battery powered toy robots.     

Design and analysis of low-power cache using two-level filter scheme

Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power, it is one of the most attractive targets for power reduction. This paper presents a two-level filter scheme, which consists of the L1 and L2 filters, to reduce the power consumption of the on-chip cache. The main idea of the proposed scheme is motivated by the substantial unnecessary activities in conventional cache architecture. We use a single block buffer as the L1 filter to eliminate the unnecessary cache accesses. In the L2 filter, we then propose a new sentry-tag architecture to further filter out the unnecessary way activities in case of the L1 filter miss. We use SimpleScalar to simulate the SPEC2000 benchmarks and perform the HSPICE simulations to evaluate the proposed architecture. Experimental results show that the two-level filter scheme can effectively reduce the cache power consumption by eliminating most unnecessary cache activities, while the compromise of system performance is negligible. Compared to a conventional instruction cache (32 kB, two-way) implemented with only the L1 filter, the use of a two-level filter can result in roughly 30% reduction in total cache power consumption. Similarly, compared to a conventional data cache (32 kB, four-way) implemented with only the L1 filter, the total cache power reduction is approximately 46%.     

Model-Driven Approach for Early Power-Aware Design Space Exploration of Embedded Systems

Due to the growing complexity of Systems-on-Chip (SoC) and the increasing cost of their redesign and fabrication, industrials are urgently looking for design methodologies allowing them to identify issues early in the design flow and to explore the largest possible space of solutions. Several aspects should be taken into account in this context, among which power consumption is considered as a major concern. In this paper, we present a Model Driven Engineering (MDE) approach for early power-aware Design Space Exploration (DSE). This approach facilitates designers work by abstracting the energetic behavior of embedded systems through high-level models targeting an automatic generation of power-aware simulation code. It offers also the possibility to model dynamic power management aspects in order to use the corresponding generated code for DSE. This approach was implemented in the DSE toolkit TTool by integrating power concepts in its DIPLODOCUS UML profile and its simulator. This paper illustrates the proposed approach through a Software-Defined Radio (SDR) case study integrating the Dynamic Slack Reclamation (DSR) policy for dynamic power management. The processor power estimates obtained by the generated simulation code were compared to those obtained from physical implementation on the Xilinx Zynq-7000 platform. This comparison showed that our MDE approach allows to take efficient design decisions early in the design flow.     

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)     

Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture

Coarse-grained reconfigurable architectures (CGRAs) require many processing elements (PEs) and a configuration memory unit (configuration cache) for reconfiguration of its PE array. Although this structure is meant for high performance and flexibility, it consumes significant power. Specially, power consumption by configuration cache is explicit overhead compared to other types of intellectual property (IP) cores. Reducing power is very crucial for CGRA to be more competitive and reliable processing core in embedded systems. In this paper, we propose a reusable context pipelining (RCP) architecture to reduce power-overhead caused by reconfiguration. It shows that the power reduction can be achieved by using the characteristics of loop pipelining, which is a multiple instruction stream, multiple data stream (MIMD)-style execution model. RCP efficiently reduces power consumption in configuration cache without performance degradation. Experimental results show that the proposed approach saves much power even with reduced configuration cache size. Power reduction ratio in the configuration cache and the entire architecture are up to 86.33% and 37.19%, respectively, compared to the base architecture.     

Improving the efficiency of Monte Carlo power estimation [VLSI]

In this paper, we propose two efficient statistical sampling techniques for estimating the total power consumption of large hierarchical circuits. We first show that, due to the characteristic of the sampling efficiency in Monte Carlo simulation, granularity of samples is an important issue in achieving high overall efficiency. The proposed techniques perform sampling both temporally (across different clock cycles) and spatially (across different modules) so that a smaller sample granularity can be achieved while maintaining the normality of samples. The first proposed technique, which is referred to as the module-based approach, samples each module independently when forming a power sample. The second technique, which is referred to as the cluster-based approach, lumps the modules of a hierarchical circuit into a number of clusters on which sampling is then performed. Both techniques adapt stratification to further improve the efficiency. Experimental results show that these techniques provide a reduction of 23× in simulation run time compared to existing Monte-Carlo simulation techniques     

Power-Aware Multimedia: Concepts and Design Perspectives

Mobile multimedia is a rising trend. A mobile device is light, thin, and small, but it is expected to be very powerful to support increasing multimedia functions, such as photos capture and display, real-time video communications, and movies and TV watching. To support these high computing and high bandwidth operations on a mobile device with limited energy, the power-aware design concept is expected to be introduced for further power optimization. A power-aware system is not only a conventional low power design, but also a design that can adaptively adjust its power consumption to specific conditions, such as different battery status, signal content, user preferences, and operating environments. In this article, we focus on the introduction of power-aware concepts and considerations to the architecture design of a video coder, followed by discussions of exciting power aware motion estimation and discrete cosine transform designs. Although these modules are dedicated architectures optimized for real-time processing, they can provide power scalability by embedding some reconfigurable points inside     

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Novel circuits and design methodology of the massively parallel processor based on the matrix architecture are introduced. A fine-grained processing elements (PE) circuit for high-throughput MAC operations based on the Booth's algorithm enhances the performance of a 16-bit fixed-point signed MAC, which operates up to 30.0GOPS/W. The dedicated I/O interface circuits are designed for converting the direction of data access and supporting the interleaved memory architecture, and they are implemented for maximizing the processor core efficiency. Power management techniques for suppressing current peaks and reducing average power consumption are proposed to enhance the robustness of the macro. The circuits and the design methodology proposal in this paper are attractive for achieving a high performance and robust massively parallel SIMD processor core employed in multimedia SoCs     

Window-based peak power model and Particle Swarm Optimization guided 3-dimensional bin packing for SoC test scheduling

This paper addresses the issue of power-aware test scheduling of cores in a System-on-Chip (SoC). While the existing approaches either use a fixed power value for the entire test session of a core or cycle-accurate power values, the proposed work divides the power profiles of cores into fixed-sized windows. This approach reduces the number of power values to be handled by the test scheduling algorithms while reducing the amount of pessimistic over-estimations of instantaneous power consumption. As a result, the power model can be integrated with more exhaustive meta-search techniques for generating power constrained test schedules. In this paper, the proposed power model has been integrated with a Particle Swarm Optimization (PSO) based 3-dimensional (3-D) bin packing technique to generate test schedules. Experimental results prove the quality of the approach to be high compared to the existing scheduling techniques.     

A variable frequency link for a power-aware network-on-chip (NoC)

Although the technology scaling has enabled designers to integrate a large number of processors onto a single chip realizing chip multi-processor (CMP), problems arising from technology scaling have made power reduction an important design issue. Since interconnection networks dissipate a significant portion of the total system power budget, it is desirable to consider interconnection network's power efficiency when designing CMP. In this paper, we present a variable frequency link for a power-aware interconnection network using the clock boosting mechanism, and apply a dynamic frequency scaling (DFS) policy, that judiciously adjusts link frequency based on link utilization parameter. Experimental result shows that history-based DFS successfully adjusts link frequency to track actual link utilization over time, demonstrating the feasibility of the proposed link as a power-aware interconnection network for system-on-chip (SoC).     

Performance analysis of an improved dynamic power management model in wireless sensor node

The energy consumption in the wireless sensor networks is a very critical issue which attracts immediate attention for the sake of the growing demand of the billion dollar market in future. The Dynamic Power Management (DPM) technique is a way of controlling and saving the energy usage in a sensor node. Previously, researchers have proposed lifetime improving stochastic models for wireless sensor networks and limited work has been done focusing on the wireless sensor node. This paper proposes an analyser based Semi-Markov model for DPM in the event-driven sensor node. The power consumption comparison with previously proposed models without this analyser shows the analyser significant contributes to lifetime improvement. The improved model is more power efficient, presents how the DPM model observes the input event arrival and power states of the sensor node components, and then dynamically manages the power consumption of the overall system. Further, to observe the effect of event arrival, missed events, waiting time, processor utilization on the power consumption and lifetime, the proposed DPM system with the single server queuing model is developed.