权电流型D/A转换器的设计

权电流网络用于克服电阻网络D／A转换器中模拟开关的导通电阻和导通压降。利用倒Ⅱ型电阻网络设计了一种新颖的权电流型D／A转换器。相比由倒T型电阻网络组成的权电流型D／A转换器，该电路具有明显的优点，使其在电子技术应用领域有重要的现实意义和实用价值。     

一种适用于模/数混合集成电路的新型低噪声电流控制逻辑

本文给出了一种新型低噪声电流控制逻辑结构，用于在模／数混合集成电路的设计中取代静态CMOS逻辑，以减小数字开关噪声通过衬底耦合对模拟电路性能的影响．在分析了该逻辑的基本工作原理后，本文对电流控制逻辑的逻辑结构，开关特性，噪声特性和功耗及功耗-延迟积等性能与静态CMOS逻辑作了比较，并用电路模拟进行了验证．理论分析和电路模拟的结果都显示，和静态CMOS逻辑相比，新型电流控制逻辑的峰值噪声电流下降了近三个数量级．该逻辑具有很好的设计灵活性和低电压工作性能，并已成功地应用于一个高性能的过采样A／D转换电路中．     

基于传输电流开关理论的电流型CMOS ADC电路设计

本文利用数字电路设计理论中的舆电流开关理论对Ａ／Ｄ转换器的转换过程进行了分析,提出了仅基于该理论的电流型ＣＭＯＳ Ａ／Ｄ转换器电路设计。与传统的Ａ／Ｄ转换器电路设计比较,它避免了复杂的模拟信号处理部分电路,显著地简化了电路结构。结果表明该电路设计具有正确的逻辑功能。     

用PWM实现廉价隔离型标准电流输出D/A转换器

分析了将脉宽调制(PWM)波形转换为模拟电压输出的D／A转换器基本理论，指出通过一个低通滤波器可以把经PWM的数模信号解调出来，给出了滤波器设计的参数选择方法，分析了D／A转换器分辨率和PWM参数的关系。在此基础上设计出简单的电压输出D／A转换器，该电路适合精度要求比较低的场合。在进一步分析该电路的基础上，设计了光电隔离、基准电压、I-V变换和功率放大等电路，得到了0mA～10mA和4mA～20mA模拟电流输出电路，该电路具有较高的精度和较大的负载驱动能力，可以应用于工业过程仪表的设计中。     

全新的双极性输出D/A转换器

应用倒Ⅱ型电阻网络．在求和放大嚣的输入端接入一个偏移电流，使输入最高位为1而其他各位输入为0时的输出Vo=0，同时将输入的符号位反相后接到一般的D／A转换嚣的输入，设计了具有双极性输出的D／A转换嚣。由于倒Ⅱ型电阻网络D／A转换嚣不仅具备权电阻网络D／A转换器的优点．而且拥有倒T型电阻网络D／A转换嚣的全部优点；所以由他构造的具有双极性输出的D／A转换器将具有更加优越的性能。使其在电子技术领域有更为广泛的应用前景和推广价值。同时用实验证明了所设计电路的正确性。     

一种高精度数控直流源的设计

设计采用硬件闭环负反馈方案实现恒流控制,用两路8位D/A组成一路16位D/A转换电路实现高精度输出电流设定。单片机89C52主要用于控制D/A电路产生稳定的控制电压、控制A/D电路完成电流测量,同时还兼管键盘、显示等人机接口。测试表明,采用该设计的数控直流源具有精度高、响应快、范围宽等优点。     

基于Pt100铂热电阻的温度变送器设计与实现

针对空压机专用变频器系统中温度检测的要求,设计并实现了一种三线制Pt100温度传感器。利用Pt100铂热电阻的电阻-温度函数关系,将温度信号转换为电压信号,经过两级放大电路对电压信号进行放大,再将电压信号转换为标准的电流信号输出。在A／D温度采集时,利用精密电流电压转换芯片,将电流信号转换为标准的电压信号。实践证明,该传感器有较高的稳定性和灵活性,性能良好且容易实现,成本低,值得推广应用。     

一种基于SET的A/D转换电路设计新方法

文章基于单电子晶体管SET（Single Electron Transistor）出了一个A／D转换电路．这种电路完全利用了SET库仑振荡效应，能够在室温度下正常工作。说明了采用该方法设计n—bitA／D转换电路仅需要一个电容分配器（由2n一2个电容构成）和2n个SET。同时给出了一个3-bit的A／D转换电路的设计实例，仿真结果表明．该电路可在室温下工作并具有良好的精确度。     

Apple—Ⅱ微机—色谱仪联机数据处理的16位A／D转移电路

本文介绍的16位A／D转换电路，是专为AppleⅡ与色谱仪联机数据处理而设计的，电路采用两片8位的D／A芯片，用EPROM替代转换中的逐位逼近寄存器，实现16位A／D转换，并采用A／D转换量程扩充处理方法，使该电路在处于小信号输入状态下的转换分辨率达到20位字长。     

基于C8051FF330D单片机的程控恒流源设计

给出了用C8051FF330D的内部电流型D/A转换器和电流/电压转换电路来输出0～4V的模拟信号量,用于控制恒流源输出电流,并使其按设定的值进行变化,从而完成可编程恒流源控制器的设计方法。利用该方法设计的程控恒流源具有电流纹波小、控制精度高和运行稳定等特点。     

基于对称三值逻辑的数模转换器研究

本文通过对称三值数字信号的开关理论分析和对称三值的数模转换的理论分析，设计了基于对称三值的数模转换电路。设计结果显示电路结构简单、合理，通过计算机模拟表明该数模转换电路的设计具有正确的逻辑功能。     

A 10-bit 200-MS/s CMOS parallel pipeline A/D converter

This paper describes a 10-bit 200-MS/s CMOS parallel pipeline analog-to-digital (A/D) converter that can sample input frequencies above 200 MHz. The converter utilizes a front-end sample-and-hold (S/H) circuit and four parallel interleaved pipeline component A/D converters followed by a digital offset compensation. By optimizing for power in the architectural level, incorporating extensively parallelism and double-sampling both in the S/H circuit and the component ADCs, a power dissipation of only 280 mW from a 3.0-V supply is achieved. Implemented in a 0.5-μm CMOS process, the circuit occupies an area of 7.4 mm². The converter achieves a differential nonlinearity and integral nonlinearity of ±0.8 LSB and ±0.9 LSB, respectively, while the peak spurious-free-dynamic-range is 55 dB and the total harmonic distortion better than 46 dB at a sampling rate of 200 MS/s     

A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

A 25-Ms/s 8-bit CMOS A/D converter for embedded application

The design of an 8-bit CMOS A/D converter is described which is intended for embedded operation in VLSI chips for video applications. The requirements on accuracy are analyzed and a comparator circuit is shown which realizes a high bandwidth. The full-flash architecture operates on wideband signals like CVBS in television systems. The A/D converter core measures 2.8 mm² in a 1 μm CMOS process. The embedded operation of the A/D converter is illustrated on a video line-resizing chip     

A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance amplifier at the outputs of the folding amplifiers and, due to careful circuit design, the comparators need no offset compensation. The result is a small area (0.7 mm² in 0.8 μm CMOS), high speed (70 MS/s), and low-power (110 mW at 5 V supply, including reference ladder) A/D converter. A 3.3 V supply version of the circuit runs at 45 MS/s and dissipates 45 mW     

PIPELINED多值A/D转换器

通过对多值ADC数学表示的分析,指出了多值ADC具有更高的信息密度。本文结合数字电路的开关信号理论,设计了Pipelined三值ADC。该ADC在保证较高转换速度的同时具有相对简单的电路结构。     

A 10 b 50 MHz pipelined CMOS A/D converter with S/H

A single 5 V, 10 b, 50 MHz pipelined CMOS analog-to-digital (A/D) converter with internal sample-and-hold (S/H) circuits was developed. The A/D converter features a newly developed S/H circuit with an 80 dB, 300 MHz operational amplifier, three-stage pipelined 4 b flash A/D converters with digital error correction functions, and double analog signal conversion paths whose operations are interleaved. The new A/D converter was fabricated with 0.8 μm CMOS technology     

A high-speed and high-resolution CMOS comparator with three-stage preamplifier

The accuracy of A/D and D/A converters depend largely upon their inner comparators. To guarantee 12-bit high resolution for an A/D converter, a precise CMOS comparator consisting of a three-stage differential preamplifier together with a positive feedback latch is proposed. Circuit structure, gain, the principle of input offset voltage storage and latching time constant for the comparator will be analyzed and optimized in this article. With 0.5 μm HYNIX mixed signal technology, the simulation result shows that the circuit has a precision of 400 μV at 20 MHz. The test result shows that the circuit has a precision of 600 μV at 16 MHz, and dissipates only 78 μW of power dissipation at 5 V. The size of the chip is 210 × 180 μm2. The comparator has been successfully used in a 10 MSPS 12-bit A/D converter. The circuit can be also used in a less than 13-bit A/D converter.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.