A dynamic CDMA network for multicore systems

Code-division multiple-access (CDMA) is a data transmission method based on the spreading code technology, wherein multiple data streams share the same physical medium with no interference. A novel architecture for on-chip communication networks based on this approach is devised. The proposed design allows sharing coding resources among network?s users through the use of dynamic assignment of spreading codes. Data transmission latency is reduced by adopting a parallel structure for the coding/decoding circuitry. A 14-node CDMA network based on the proposed architecture is synthesised using 65 nm ST technology library. Performance analysis reveals that the proposed approach achieves significantly lower data packet latency compared to both conventional CDMA and packet switched network-on-chip implementations. Large area and power savings compared to existing approaches are also obtained.     

Improving the performance of packet-switched networks-on-chip by SDM-based adaptive shortcut paths

Reducing the NoC power is critical for scaling up the number of nodes in future many-core systems. Most NoC designs adopt packet-switching to benefit from its high throughput and excellent scalability. These benefits, however, come at the price of the power consumption and latency overheads of routers. Circuit-switching, on the other hand, enjoys a significant reduction in power and latency of communication by directing data over pre-established circuits, but the relatively large circuit setup time and low resource utilization of this switching mechanism is often prohibitive. In this paper, we address one of the major problems of circuit-switching, i.e. the circuit setup time overhead, by an efficient and fast algorithm based on the time-division multiplexing (TDM) scheme. We then further improve the performance by reserving circuits for anticipated messages, and hence completely hide circuit setup time. To address the low resource utilization problem, we integrate the proposed circuit-switching into a packet switched NoC and use unused circuit resources to transfer packet-switched data. Evaluation results show considerable reduction in NoC power consumption and packet latency.     

"It's a small world after all": NoC performance optimization via long-range link insertion

Networks-on-chip (NoCs) represent a promising solution to complex on-chip communication problems. The NoC communication architectures considered so far are based on either completely regular or fully customized topologies. In this paper, we present a methodology to automatically synthesize an architecture which is neither regular nor fully customized. Instead, the communication architecture we propose is a superposition of a few long-range links and a standard mesh network. The few application-specific long-range links we insert significantly increase the critical traffic workload at which the network transitions from a free to a congested state. This way, we can exploit the benefits offered by both complete regularity and partial topology customization. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and a major improvement in the achievable network through with minimal impact on network topology.     

S-Mesh: a Mesh-based on-chip network with separation of control and transmission

The current network-on-chip (NoC) topology cannot predict subsequent switch node status promptly. Switch nodes have to perform various functions such as routing decision, data forwarding, packet buffering, congestion control and properties of an NoC system. Therefore, these make switch architecture far more complex. This article puts forward a separating on-chip network architecture based on Mesh (S-Mesh). S-Mesh is an on-chip network that separates routing decision flow from the switches. It consists of two types of networks: datapath network (DN) and control network (CN). The CN establishes data paths for data transferring in DN. Meanwhile, the CN also transfers instructions between different resources. This property makes switch architecture simple, and eliminates conflicts in network interface units between the resource and switch. Compared with 2D-Mesh, Torus Mesh, Fat-tree and Butterfly, the average packet latency in S-Mesh is the shortest when the packet length is more than 53 B. Compared with 2D-Mesh, the areas savings of S-Mesh is about 3%--7%, and the power dissipation is decreased by approximate 2%.     

Mapping and Scheduling for Circuit‐Switched Network‐on‐Chip Architecture

Network‐on‐chip (NoC) architecture provides a high‐performance communication infrastructure for system‐on‐chip designs. Circuit‐switched networks guarantee transmission latency and throughput; hence, they are suitable for NoC architecture with real‐time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication circuits, and allocates a proper bandwidth for each circuit. Simulation results show that the average waiting times of packets in a switch in 6×6, 8×8, and 10×10 mesh NoC networks are 0.59, 0.62, and 0.61, respectively. The latency of circuits is significantly decreased. Furthermore, the buffer of a switch in NoC only needs to accommodate the data of one time slot. The cost of the switch in the circuit‐switched network can be reduced using our scheme. Our design provides an effective solution for a critical step in NoC design.     

3-D Topologies for Networks-on-Chip

Several interesting topologies emerge by incorporating the third dimension in networks-on-chip (NoC). The speed and power consumption of 3D NoC are compared to that of 2D NoC. Physical constraints, such as the maximum number of planes that can be vertically stacked and the asymmetry between the horizontal and vertical communication channels of the network, are included in speed and power consumption models of these novel 3D structures. An analytic model for the zero-load latency of each network that considers the effects of the topology on the performance of a 3D NoC is developed. Tradeoffs between the number of nodes utilized in the third dimension, which reduces the average number of hops traversed by a packet, and the number of physical planes used to integrate the functional blocks of the network, which decreases the length of the communication channel, is evaluated for both the latency and power consumption of a network. A performance improvement of 40% and 36% and a decrease of 62% and 58% in power consumption is demonstrated for 3D NoC as compared to a traditional 2D NoC topology for a network size of N = 128 and N = 256 nodes, respectively.     

Multicast-enabled network-on-chip routers leveraging partitioned allocation and switching

Multicast on-chip communication is encountered in various cache-coherence protocols targeting multi-core processors, and its pervasiveness is increasing due to the proliferation of machine learning accelerators. In-network handling of multicast traffic imposes additional switching-level restrictions to guarantee deadlock freedom, while it stresses the allocation efficiency of Network-on-Chip (NoC) routers. In this work, we propose a novel partitioned NoC router microarchitecture, called SmartFork, which employs a versatile and cost-efficient multicast packet replication scheme that allows the design of high-throughput and low-cost NoCs. The design is adapted to the average branch splitting observed in real-world multicast routing algorithms. Compared to state-of-the-art NoC multicast approaches, SmartFork is demonstrated to yield high performance in terms of latency and throughput, while still offering a cost-effective implementation.     

Applying partial power-gating to bit-sliced network-on-chip

In the many-core systems, network-on-chip (NoC) serves as an efficient and scalable architecture to connect numerous on-chip resources, whereas it encounters the crisis of the increasing leakage power as technology is continually scaling down. Power-gating which is a representative low-power technique can be utilized to mitigate the increasing leakage power, but the disconnection problem suffered in the conventional power-gated NoC may severely affect network performance. In this paper, we propose a novel partial power-gating approach to avoid the performance loss caused by the disconnection. Firstly, we utilize the asymmetrical bit-slicing scheme to split router into two slices. After the bit-slicing of router datapath, the wide slices can be switched off to save some leakage power by using partial power-gating, but all narrow slices should be kept in ever-active state to avoid the disconnection. Next, owing to the slicing of router datapath, we redefine the packet format for the packet׳s slicing and transferring, and present two essential conversion modules to achieve packet׳s slicing and reassembling. In the synthetic traffic simulation, our design gains considerable power-saving at low-load and exhibits better performance behavior than the conventional power-gated design. The application simulation shows that our design can averagely save 27.5% of total power compared with the baseline design, and reduce 45.0% packet latency on average when compared with the conventional power-gated design. On balance, the bit-sliced NoC with partial power-gating has a better tradeoff between performance and power-efficiency.     

An interconnection architecture for network-on-chip systems

Network on Chip (NoC) is a discipline research path that primarily addresses the global communication in System on Chip (SoC). It is inspired and uses the same routing and switching techniques needed in multi-computer networks. Current shared-bus based on-chip communication architectures generally have limited scalability due to the nature of the buses especially when complex on-chip communication SoC is needed. The main goal is to have a dedicated communication infrastructure in the system that can scale up while minimizing the area and power. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we introduce a new NoC architecture by adapting a recursive topology structure. An experimental study is performed to compare this structure with basic NoC topologies represented by 2D mesh and Spidergon. The analysis illustrates the main features of this topology and its unique benefits. The simulation results show that recursive network outperforms 2D mesh and Spidergon in main performance metrics.     

Application-aware virtual paths insertion for NOCs

Network-on-chip (NoC) has rapidly become a promising alternative for complex system-on-chip architectures including recent multicore architectures. Additionally, optimizing NoC architectures with respect to different design objectives that are suitable for a particular application domain is crucial for achieving high-performance and energy-efficient customized solutions. Despite the fact that many researches have provided various solutions for different aspects of NoCs design, a comprehensive NoCs system solution has not emerged yet. This paper presents a novel methodology to provide a solution for complex on-chip communication problems to reduce power, latency and area overhead. Our proposed NoC communication architecture is based on setting up virtual source–destination paths between selected pairs of NoCs cores so that the packets belonging to distance nodes in the network can bypass intermediate routers while traveling through these virtual paths. In this scheme, the paths are constructed for an application based on its task-graph at the design time. After that, the run time scheduling mechanism is applied to improve the buffer management, virtual channel and switch allocation schemes and hence, the constructed paths are optimized dynamically. Moreover, in our design the router complexity and its overheads are reduced. Additionally, the suggested router has been implemented on Xilinx Virtex-5 FPGA family. The evaluation results captured by SPLASH-2 benchmark suite reveal that in comparison with the conventional NoC router, the proposed router takes 25% and 53% reduction in latency and energy, respectively besides 3.5% area overhead. Indeed, our experimental results demonstrate a significant reduction in the average packet latency and total power consumption with negligible area overhead.     

On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems

Homogeneous manycore systems are emerging for tera-scale computation and typically utilize Network-on-Chip (NoC) as the communication scheme between embedded cores. Effective defect tolerance techniques are essential to improve the yield of such complex integrated circuits. We propose to achieve fault tolerance by employing redundancy at the core-level instead of at the microarchitecture level. When faulty cores exist on-chip in this architecture, however, the physical topologies of various manufactured chips can be significantly different. How to reconfigure the system with the most effective NoC topology is a relevant research problem. In this paper, we first show that this problem is an instance of a well known NP-complete problem. We then present novel solutions for the above problem, which not only maximize the performance of the on-chip communication scheme, but also provide a unified topology to Operating System and application software running on the processor. Experimental results show the effectiveness of the proposed techniques.      

Xpipes: a network-on-chip architecture for gigascale systems-on-chip

The growing complexity of embedded multiprocessor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched networks-on-chip (NoC) have been proposed to support the trend for systems-on-chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called XpipesCompiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes-based synthesis flow for domain-specific communication architectures.     

All-Optical Wavelength-Bypassing Ring Communications Networks

We introduce an all-optical WDM packet communication network that performs wavelength bypassing at the routers. Packets that arrive at a wavelength (optical cross-connect) router at designated wavelengths are switched by the router without having their headers examined. Thus, the processing element of the router is bypassed by such packets. For packet traffic that uses wavelengths that do not bypass a switch, the headers of such packets are examined to determine if this switch is the destination for the flow. If latter is the case, the packet is removed. Otherwise, the packet is switched to a pre-determined output without incurring (network internal) queueing delays. We study a ring network with routers that employ such a WDM bypassing scheme. We present methods to construct wavelength graphs that define the bypassing pattern employed by the routers to guide the traffic flows distributed at each given wavelength. Performance is measured in terms of the network throughput and the average processing path length (i.e., the average number of switches not being bypassed). For a fixed total processing capacity, we show that a WDM bypassing ring network provides a higher throughput level than that exhibited by a non-bypassing ring network, using the same value of total link capacity. By using WDM bypassing, the average processing path length (and thus the packet latency) is reduced. We study a multitude of network loading configurations, corresponding to distinct traffic matrices and client-server scenarios. Higher throughput levels are obtained for network configurations driven by non-uniform traffic matrices. The demonstrated advantages of WDM bypassing methods shown here for WDM ring networks are also applicable to more general network topological layouts.     

Admission policies for integrated voice and data traffic in CDMApacket radio networks

The authors derive optimal admission policies for integrated voice and data traffic in packet radio networks employing code division multiple access (CDMA) with direct-sequence spread spectrum (DS/SS) signaling. The network performance is measured in terms of the average blocking probability of voice calls and the average delay and packet loss probability of data messages. The admission scheme determines the number of newly arrived voice users that are accepted in the network so that the long-term blocking probability of voice calls is minimized. In addition, new data arrivals are rejected if the mean delay or the packet loss probability of data exceeds a desirable prespecified level. A semi-Markov decision process (SMDP) is used to model the system operation. Then, a value iteration algorithm is used to derive the optimal admission control. Two models for the other-user interference of the CDMA system are considered: one based on thresholds and another based on the graceful degradation of the CDMA system performance, and their performance is compared. These admission policies find application in emerging commercial CDMA packet radio networks including cellular networks, personal communication networks, and networks of LEO satellites for global communications     

基于双频通信的空间飞行器自组网动态时隙分配

针对分布式空间飞行器自组网使用传统时分多址(Time Division Multiple Access,TDMA)时隙分配方式时网络时延大、传输效率不高的问题,提出了一种基于双频通信的动态时分多址时隙分配(Dual Frequency Dynamic Time Division Multiple Access,DF-D...     

Low-cost and low-power unidirectional torus network-on-chip with corner buffer power-gating

Network-on-chip (NoC) is one of critical communication architectures for the scaling of future many-core processors. The challenge for on-chip network is reducing design complexity to save both area and power while providing high performance such as low latency and high throughput. Especially, with increase of network size, both design complexity and power consumption have become the bottlenecks preventing proper network scaling. Moreover, as technology continuously scales down, leakage power takes up a larger fraction of total NoC power. It is increasingly important for a power-efficient NoC design to reduce the increasing leakage power. Power-gating, as a representative low-power technique, can be applied to an on-chip network for mitigating leakage power. In this paper, we propose a low-cost and low-power router architecture for the unidirectional torus network, and adopt an improved corner buffer structure for the inoffensive power-gating, which has minimal impact on network performance. Besides, an explicit starvation avoidance mechanism is introduced to guarantee injection fairness while decreasing its negative impact on network throughput. Simulation results with synthetic traffic show that our design can improve network throughput by 11.3% on average and achieve significant power-saving in low- and medium-load regions. In the SPLASH-2 workload simulation, our design can save on average 27.2% of total power compared to the baseline, and decrease 42.8% average latency compared to the baseline with power-gating.     

基于3G网络PS域的传真通信研究

传真通信在PSTN网上得到了广泛的应用,在3G网上虽然制定了CS域传真的相关标准,却并未开展应用。而PS域虽然提供了透明的数据传输通道,但在端到端通信和传输的实时性方面与固定IP网有较大差别。针对3G网CS域不能进行传真通信的现状,对PS域传真的可行性进行了研究,分析了PS域信道的特点,对实时传真模式和存储转发模式进行了比较,提出在PS域建立VPN实现端到端通信和存储转发的传真工作模式。     

无线NoC研究与进展

分析了无线NoC的一般结构,对两种典型拓扑结构及其相关特性进行了比较,并对无线NoC涉及到的关键通信机制,特别是片上天线、路由及通信协议对其性能的影响进行了讨论,最后对未来无线NoC的技术热点及难点问题进行了总结和展望。     

Millimeter wave wireless interconnects in deep submicron chips: Challenges and opportunities

On-chip wireless links offer the most promising solution to improve performance over traditional Networks-on-Chip (NoCs). Though, significant advancements are being made to support intra-chip wireless communication, a complete understanding of on-chip wireless channel, that facilitates design optimization of transceivers and antennas is still lacking. In this work, we derive on-chip wireless channel characteristics, taking into account antenna implementation, near field and multipath propagation effects. These observations are then used to study impact on wireless NoC performance, packet energy, delay and bandwidth. The study provides crucial insights for circuit designers to tune transceiver and antenna specifications to achieve desired network performance.     

Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication

Network on chip (NoC) is the solution to solve the problem of larger system on chip and bus based communication system. NoC provides scalable, highly reliable and modular approach for on chip communication and related problems. The wireless communication technologies such as IEEE 802.15.4 Zigbee technology follow mesh, star and cluster tree topology. The paper focuses on the development of machine learning model for design and FPGA synthesis of mesh, ring and fat tree NoC for different cluster size (N = 2, 4, 8, 16, 32, 64, 128 and 256). The fat-tree based topologies incorporate more links near the root of the tree, in order to fulfill the requirement for higher communication demand closer to the root of the tree, as compared to its leafs. It is an indirect topology in which not all routers are identical in terms of number of ports connecting to other routers or elements in the network. The research article presents the use of machine learning techniques to predict the FPGA resource utilization for NoC in advance. The present study helps in NoC chip planning before designing the chip itself by taking into account known hardware design parameters, memory utilization and timing parameters such as minimum and maximum period, frequency support etc. The machine learning is carried out based on multiple linear regression, decision tree regression and random forest regression which estimate the accuracy of the design and good performance. The interprocess communication among nodes is verified using Virtex-5 FPGA, in which data flows in packets and can vary up to ‘n’ bit. The designs are developed in Xilinx ISE 14.2 and simulated in Modelsim 10.1b with the help of VHDL programming language. The developed model has been validated and has performed well on independent test data.