“数字信号处理”中循环卷积的简单计算方法

"数字信号处理"课程中,在定义两个序列的循环卷积时,在时域一般都是依据定义直接进行计算,但是这种方法很繁琐。本文通过分析循环卷积与线性卷积的关系,提出了一个非常简单的用于计算循环卷积的方法。笔者通过具体的计算实例,详细介绍了本文提出的方法。     

线性卷积与循环卷积的教学研究

本文针对“数字信号处理”课程中线性卷积与循环卷积存在的教学难题,从两种卷积的物理概念人手,讨论了其运算规则和等价条件,提出了一种利用线性卷积快速计算循环卷积的简便方法,最后通过Matlab仿真对该计算方法进行了验证.     

线性卷积与循环卷积等价关系及水声通信应用

线性卷积与循环卷积的等价关系是"数字信号处理"课程的重点内容之一.在计算循环卷积时,通常利用线性卷积的周期延拓来计算周期卷积,再对周期卷积取主值区间得到循环卷积.本文结合水声通信这一海洋信号处理领域的研究热点之一,针对水声通信中最新使用的零填充正交频分复用系统,介绍基于线性卷积的循环卷积计算方法及其具体应用,并通过实例对该方法进行演示.     

"数字信号处理"中分段滤波的教学探讨

分段滤波是"数字信号处理"课程重要的知识点和难点之一,它有两种实现方法:重叠相加法和重叠保留法.针对现有教材和课堂教学中从循环卷积与线性卷积关系出发讨论重叠相加法和重叠保留法的局限性,本文从滤波器的瞬态响应和稳态响应出发,阐述重叠相加法和重叠保留法如何保证各段滤波输出的连续性,并讨论了重叠相加法和重叠保留法各段线性卷积与圆周卷积的关系,以及各段滤波输入/输出数据的关系,以帮助学生深入理解分段滤波的本质,达到学以致用.     

基于符号动力学的混沌信号处理研究

基于1-D分段线性映射函数构造的混沌系统符号动力学,该文研究了一种能直接对混沌符号序列进行加、减及乘法运算的方法。由两串符号序列之间的轨道距离定义推导并证明了相应的运算法则。通过FIR数字滤波器卷积和操作的计算机数值仿真表明,采用这些方法运算得到的结果与传统二进制算术编码算法完全等效,可应用于混沌信号处理系统。     

基于中国余数定理和CSD乘法的线性卷积设计

给出了应用中国余数定理和CSD乘法实现线性卷积的算法.将一维循环卷积映射为多维循环卷积,缩减算法强度,使乘法数量降到最少;通过移位相加实现常系数乘法,系数采用正则符号数编码使加法数量最小.利用循环卷积和线性卷积的关系,计算线性卷积,使线性卷积的功耗和面积最小.最后采用modelsim仿真和quartus7.2综合,并将仿真结果与理论计算结果进行了比较.表明该线性卷积器工作可靠、精度高,具有较好的实用价值.     

基于线性相关的不同点循环相关 计算方法

在“数字信号处理”课程中，相关是一项重要的信号处理运算，在时延估计、随机信号的统计特性分析以及随机信号的功率谱估计等方面有着重要的应用。结合相关和卷积的关系，本文推导了线性相关与循环相关的转化关系，提出了一种基于线性相关的循环相关计算方法，能基于线性相关结果来快速计算不同点数的循环相关，仿真结果表明，相比于直接根据定义计算循环相关的方法，本文提出的方法能显著提高计算效率。     

“数字信号处理”中重叠保留法的证明

重叠保留法是计算一个短序列与一个无限长序列线性卷积的有效方法。就我们所知，多数《数字信号处理》教材详细叙述了重叠保留法的步骤，有些教材还从线性卷积与循环卷积的关系出发给出了重叠保留法的原理，笔者认为这种解释不够清楚、也不够严谨。本文给出了一个较为严谨而准确的证明。     

数字信号处理中分段滤波的教学探讨

分段滤波是“数字信号处理”课程重要的知识点和难点之一,它有两种实现方法：重叠相加法和重叠保留法。针对现有教材和课堂教学中从循环卷积与线性卷积关系出发讨论重叠相加法和重叠保留法的局限性,本文从滤波器的瞬态响应和稳态响应出发,阐述重叠相加法和重叠保留法如何保证各段滤波输出的连续性,并讨论了重叠相加法和重叠保留法各段线性卷积与圆周卷积的关系,以及各段滤波输入/输出数据的关系,以帮助学生深入理解分段滤波的本质,达到学以致用。     

基于分圆类构造卷积压缩感知测量矩阵

卷积压缩感知是近年来兴起的新型压缩感知技术。卷积压缩感知选用循环矩阵作为测量矩阵,其采样可以简化为卷积的过程,因此大大降低算法复杂度。该文基于分圆类构造适用于卷积压缩感知的测量矩阵,测量值通过利用确定性序列循环卷积信号,然后进行随机2次采样获得。该文构造的测量矩阵的相关性小于已有文献构造的测量矩阵的相关性。模拟仿真结果表明,该文构造的测量矩阵与同等条件下的随机高斯矩阵相比,可以更好地恢复稀疏信号;所构造的矩阵还可以应用于信道估计以及2维图像的重构。     

基于圆周卷积的长序列小波变换快速实现

根据小波变换的基本特点,在运用重叠保留法对长序列进行分段处理的基础上,提出用圆周卷积来实现快速小波变换中大量的线性卷积运算。通过Matlab仿真实现,结果验证了算法的正确性,运算速度较传统线性卷积方法有很大提高。该方法有着很好的并行度,有利于信号的实时处删。     

Direct reconstruction of cone-beam data acquired with a vertex pathcontaining a circle

Cone-beam data acquired with a vertex path satisfying the data sufficiency condition of Tuy can be reconstructed using exact filtered backprojection algorithms. These algorithms are based on the application to each cone-beam projection of a two-dimensional (2-D) filter that is nonstationary, and therefore more complex than the one-dimensional (1-D) ramp filter used in the approximate algorithm of Feldkamp, Davis, and Kress (1984) (FDK). We determine in this paper the general conditions under which the 2-D nonstationary filter reduces to a 2-D stationary filter, and also give the explicit expression of the corresponding convolution kernel. Using this result and the redundancy of the cone-beam data, a composite algorithm is derived for the class of vertex paths that consist of one circle and some complementary subpath designed to guarantee data sufficiency. In this algorithm the projections corresponding to vertex points along the circle are filtered using a 2-D stationary filter, whereas the other projections are handled with a 2-D nonstationary filter. The composite algorithm generalizes the method proposed by Kudo and Saito (1990), in which the circle data are processed with a 1-D ramp filter as in the FDK algorithm. The advantage of the 2-D filter introduced in this paper is to guarantee that the filtered cone-beam projections do not contain singularities in smooth regions of the object. Tests of the composite algorithm on simulated data are presented.     

六点拟合的正弦信号的插值多项式测频

本文提出一种新的快速测量正弦信号频率的方法,它主要利用三次多项式插值函数来拟合经过DFT变换的数据点,然后通过求插值函数的极值点来进行频率估计。仿真结果证明方法的有效性和简便性,并对其CPLD快速实现进行探讨。     

六点拟合的正弦信号的插值多项式测频

本文提出一种新的快速测量正弦信号频率的方法,它主要利用三次多项式插值函数来拟合6个经过DFT变换的数据点,然后通过求插值函数的极值点来进行频率估计。仿真结果证明方法的有效性和简便性。     

A new method for D-dimensional exact deconvolution

Deconvolution is an important problem of signal processing, and conventional approaches, including Fourier methods, have stability problems due to the zeros of the convolution kernel. We present a new method of multidimensional exact deconvolution. This method is always stable, even when the convolution kernel h(n) has zeros on the unit circle, and there exist closed-form solutions for the one-dimensional (1-D) case (D=1). For the multidimensional case (D>1), the proposed method yields stable solutions when det(h)=D. This solution set covers a portion of all possible convolution kernels, including the ones that have zeros on the multidimensional unit circle. This novel time-domain method is based on the fact that the convolution inverse of a first-order kernel can be found exactly in multidimensional space. Convolution inverses for higher order kernels are obtained using this fact and the zeros of the convolution kernel. The presented method is exact, stable, and computationally efficient. Several examples are given in order to show the performance of this method in 1-D and multidimensional cases     

基于数据共轭重排的修正二维MUSIC算法分析

在阐述二维MUSIC算法基本原理的基础上,通过将接收数据共轭重排的再利用、构造相关矩阵,提出一种基于正交阵列的修正二维MUSIC算法。在快拍次数有限时,此算法可以明显改善信号的波达方向估计性能,特别是相干信号波达方向(DOA)的估计性能,计算机仿真结果证明了该改进算法的有效性和可行性。     

An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels

Design of a high-performance digital architecture for computing 2-D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial results of the convolution sum. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less log₂ and inverse-log₂ modules. An effective data-handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The systolic architecture employs parallel and pipelined processing and is able to produce one output every clock cycle. The new design resulted in approximately 40% reduction in hardware resource when compared to the approach of multiplier-based quadrant symmetric architecture. The proposed architecture design is capable of performing convolution operations for 63.3, 1024×1024 frames or 66.4 million outputs per second with 22×22 kernel in a Xilinx's Virtex 2v2000ff896-4 FPGA at maximum clock frequency of 66.4 MHz. The error analysis performed in two image-processing applications of edge detection and noise filtering shows that the hardware implementation with proposed design provides accurate results similar to the software implementation.