GaSb: A New Alternative Substrate for Epitaxial Growth of HgCdTe

In this work, GaSb is proposed as a new alternative substrate for the growth of HgCdTe via molecular beam epitaxy (MBE). Due to the smaller mismatch in both lattice constant and coefficient of thermal expansion between GaSb and HgCdTe, GaSb presents a better alternative substrate for the epitaxial growth of HgCdTe, in comparison to alternative substrates such as Si, Ge, and GaAs. In our recent efforts, a CdTe buffer layer technology has been developed on GaSb substrates via MBE. By optimizing the growth conditions (mainly growth temperature and VI/II flux ratio), CdTe buffer layers have been grown on GaSb substrates with material quality comparable to, and slightly better than, CdTe buffer layers grown on GaAs substrates, which is one of the state-of-the-art alternative substrates used in growing HgCdTe for the fabrication of mid-wave infrared detectors. The results presented in this paper indicate the great potential of GaSb to become the next generation alternative substrate for HgCdTe infrared detectors, demonstrating MBE-grown CdTe buffer layers with rocking curve (double crystal x-ray diffraction) full width at half maximum of ～60 arcsec and etch pit density of ～10⁶ cm^?2.     

Strain Reduction in Selectively Grown CdTe by MBE on Nanopatterned Silicon on Insulator (SOI) Substrates

Silicon-based substrates for the epitaxy of HgCdTe are an attractive low-cost choice for monolithic integration of infrared detectors with mature Si technology and high yield. However, progress in heteroepitaxy of CdTe/Si (for subsequent growth of HgCdTe) is limited by the high lattice and thermal mismatch, which creates strain at the heterointerface that results in a high density of dislocations. Previously we have reported on theoretical modeling of strain partitioning between CdTe and Si on nanopatterned silicon on insulator (SOI) substrates. In this paper, we present an experimental study of CdTe epitaxy on nanopatterned (SOI). SOI (100) substrates were patterned with interferometric lithography and reactive ion etching to form a two-dimensional array of silicon pillars with ～250 nm diameter and 1 μm pitch. MBE was used to grow CdTe selectively on the silicon nanopillars. Selective growth of CdTe was confirmed by scanning electron microscopy (SEM), atomic force microscopy (AFM), and X-ray photoelectron spectroscopy (XPS). Coalescence of CdTe on the silicon nanoislands has been observed from the SEM characterization. Selective growth was achieved with a two-step growth process involving desorption of the nucleation layer followed by regrowth of CdTe at a rate of 0.2 Å s^?1. Strain measurements by Raman spectroscopy show a comparable Raman shift (2.7 ± 2 cm^?1 from the bulk value of 170 cm^?1) in CdTe grown on nanopatterned SOI and planar silicon (Raman shift of 4.4 ± 2 cm^?1), indicating similar strain on the nanopatterned substrates.     

Heteroepitaxy of HgCdTe(112) infrared detector structures on Si(112) substrates by molecular-beam epitaxy

High-quality, single-crystal epitaxial films of CdTe(112)B and HgCdTe(112)B have been grown directly on Si(112) substrates without the need for GaAs interfacial layers. The CdTe and HgCdTe films have been characterized with optical microscopy, x-ray diffraction, wet chemical defect etching, and secondary ion mass spectrometry. HgCdTe/Si infrared detectors have also been fabricated and tested. The CdTe(112)B films are highly specular, twin-free, and have x-ray rocking curves as narrow as 72 arc-sec and near-surface etch pit density (EPD) of 2 × 10⁶ cm⁻² for 8 μm thick films. HgCdTe(112)B films deposited on Si substrates have x-ray rocking curve FWHM as low as 76 arc-sec and EPD of 3-22 × 10⁶ cm⁻². These MBE-grown epitaxial structures have been used to fabricate the first high-performance HgCdTe IR detectors grown directly on Si without use of an intermediate GaAs buffer layer. HgCdTe/Si infrared detectors have been fabricated with 40% quantum efficiency and R₀A = 1.64 × 10⁴ Ωm₂ (0 FOV) for devices with 7.8 μm cutoff wavelength at 78Kto demonstrate the capability of MBE for growth of large-area HgCdTe arrays on Si.     

Orientation dependence of HgCdTe epitaxial layers grown by MOCVD on Si substrates

Orientation dependence of HgCdTe epilayers grown by MOCVD on Si substrates was studied. Substrate orientation is considered to be one of the most sensitive factors to enable hetero-epitaxial growth on silicon substrates, especially in the case of a low temperature growth process. The present work was carried out with characterized features of a low temperature process for HgCdTe growth on Si and using a thin CdTe buffer layer. The (100), (100) misoriented toward [110], (311), (211), (111), and (331) oriented Si substrates were used in the present work. The best results were obtained on (211)Si substrates with an x-ray full width at half maximum of 153 arc sec for a 5 (im thickness HgCdTe layer and 69 arc sec for a 10 um thickness layer. It was found that the effective lattice mismatch of CdTe/Si heterosystem was reduced to 0.6% (for the 611 lattice spacing of CdTe and 333 spacing of Si) in the case of (133)CdTe/(211)Si.     

Molecular beam epitaxy grown long wavelength infrared HgCdTe on Si detector performance

The use of silicon as a substrate alternative to bulk CdZnTe for epitaxial growth of HgCdTe for infrared (IR) detector applications is attractive because of potential cost savings as a result of the large available sizes and the relatively low cost of silicon substrates. However, the potential benefits of silicon as a substrate have been difficult to realize because of the technical challenges of growing low defect density HgCdTe on silicon where the lattice mismatch is ∼19%. This is especially true for LWIR HgCdTe detectors where the performance can be limited by the high (∼5×10⁶ cm⁻²) dislocation density typically found in HgCdTe grown on silicon. We have fabricated a series of long wavelength infrared (LWIR) HgCdTe diodes and several LWIR focal plane arrays (FPAs) with HgCdTe grown on silicon substrates using MBE grown CdTe and CdSeTe buffer layers. The detector arrays were fabricated using Rockwell Scientific’s planar diode architecture. The diode and FPA and results at 78 K will be discussed in terms of the high dislocation density (∼5×10⁶ cm²) typically measured when HgCdTe is grown on silicon substrates.     

Cadmium telluride growth on patterned substrates for mercury cadmium telluride infrared detectors

Patterned silicon-on-insulator (SOI) substrates have been proposed to grow low defect density CdTe. The CdTe epilayers so obtained will enable the growth of good-quality mercury cadmium telluride (HgCdTe) layers subsequently. This would increase the scope for better performance of infrared detectors fabricated on the HgCdTe epilayers. A background of our previous work on metal organic chemical vapor deposition (MOCVD) of GaN on nanopatterned alternative silicon substrates has been presented. Residual stress measurements were made on the GaN epilayers by spatially resolved Raman spectroscopy, which shows reduced strain in the epilayer growth on the patterned substrates. A theoretical approach of strain in planar substrates, compliant substrates, and patterned compliant substrates is presented with detailed plots.     

Recent Progress in MBE Growth of CdTe and HgCdTe on (211)B GaAs Substrates

Alternate substrates for molecular beam epitaxy growth of HgCdTe including Si, Ge, and GaAs have been under development for more than a decade. MBE growth of HgCdTe on GaAs substrates was pioneered by Teledyne Imaging Sensors (TIS) in the 1980s. However, recent improvements in the layer crystal quality including improvements in both the CdTe buffer layer and the HgCdTe layer growth have resulted in GaAs emerging as a strong candidate for replacement of bulk CdZnTe substrates for certain infrared imaging applications. In this paper the current state of the art in CdTe and HgCdTe MBE growth on (211)B GaAs and (211) Si at TIS is reviewed. Recent improvements in the CdTe buffer layer quality (double crystal rocking curve full-width at half-maximum?≈?30?arcsec) with HgCdTe dislocation densities of ≤10⁶?cm^?2 are discussed and comparisons are made with historical HgCdTe on bulk CdZnTe and alternate substrate data at TIS. Material properties including the HgCdTe majority carrier mobility and dislocation density are presented as a function of the CdTe buffer layer quality.     

Te-rich liquid phase epitaxial growth of HgCdTe on Si-based substrates

The growth of high quality (111)B oriented HgCdTe layers on CdZnTe/GaAs/Si and CdTe/Si substrates by Te-rich slider liquid phase epitaxy (LPE) is reported. Although the (111) orientation is susceptible to twinning, a reproducible process yielding twin-free layers with excellent surface morphology has been developed. The electrical properties and dislocation density in films grown on these substrates are comparable to those measured in HgCdTe layers grown on bulk CdTe substrates using the same LPE process. This is surprising in view of the large lattice mismatch that exists in these systems. We will report details of both the substrate and HgCdTe growth processes that are important to obtaining these results.     

Growth and Analysis of HgCdTe on Alternate Substrates

Dislocations generated at the HgCdTe/CdTe(buffer layer) interface are demonstrated to play a significant role in influencing the crystalline characteristics of HgCdTe epilayers on alternate substrates (AS). A dislocation density >10⁸?cm^?2 is observed at the HgCdTe/CdTe interface. Networks of dislocations are generated at the HgCdTe/CdTe interface. The dislocation networks are observed to entangle. Significant dislocation reduction occurs within a few microns of the HgCdTe/CdTe interface. The reduction in dislocation density as a function of depth is enhanced by annealing. Etch pit density and x-ray diffraction full-width at half-maximum values increase as a function of the lattice mismatch between HgCdTe epilayer and the buffer layer/substrate. The experimental results suggest that only by reducing HgCdTe/CdTe lattice mismatch will the desired crystallinity be achieved for HgCdTe epilayers on AS.     

MBE growth and device processing of MWIR HgCdTe on large area Si substrates

The traditional substrate of choice for HgCdTe material growth has been lattice matched bulk CdZnTe material. However, as larger array sizes are required for future devices, it is evident that current size limitations of bulk substrates will become an issue and therefore large area Si substrates will become a requirement for HgCdTe growth in order to maintain the cost-efficiency of future systems. As a result, traditional substrate mounting methods that use chemical compounds to adhere the substrate to the substrate holder may pose significant technical challenges to the growth and fabrication of HgCdTe on large area Si substrates. For these reasons, non-contact (indium-free) substrate mounting was used to grow mid-wave infrared (MWIR) HgCdTe material on 3″ CdTe/Si substrates. In order to maintain a constant tepilayer temperature during HgCdTe nucleation, reflection high-energy electron diffraction (RHEED) was implemented to develop a substrate temperature ramping profile for HgCdTe nucleation. The layers were characterized ex-situ using Fourier transform infrared (FTIR) and etch pit density measurements to determine structural characteristics. Dislocation densities typically measured in the 9 10⁶ cm⁻² to 1 10⁷ cm⁻² range and showed a strong correlation between ramping profile and Cd composition, indicating the uniqueness of the ramping profiles. Hall and photoconductive decay measurements were used to characterize the electrical properties of the layers. Additionally, both single element and 32 32 photovoltaic devices were fabricated from these layers. A RA value of 1.8 10⁶-cm² measured at −40 mV was obtained for MWIR material, which is comparable to HgCdTe grown on bulk CdZnTe substrates.     

Inductively coupled plasma etching for large format HgCdTe focal plane array fabrication

Inductively coupled plasma (ICP) using hydrogen-based gas chemistry has been developed to meet requirements for deep HgCdTe mesa etching and shallow CdTe passivation etching in large format HgCdTe infrared focal plane array (FPA) fabrication. Large format 2048×2048, 20-μm unit-cell short wavelength infrared (SWIR) and 2560×512, 25-μm unit-cell midwavelength infrared (MWIR) double-layer heterojunction (DLHJ) p-on-n HgCdTe FPAs fabricated using ICP processing exhibit >99% pixel operability. The HgCdTe FPAs are grown by molecular beam epitaxy (MBE) on Si substrates with suitable buffer layers. Midwavelength infrared detectors fabricated from 4-in. MBE-grown HgCdTe/Si substrates using ICP for mesa delineation and CdTe passivation etching demonstrate measured spectral characteristics, RoA product, and quantum efficiency comparable to detectors fabricated using wet chemical processes. Mechanical samples prepared to examine physical characteristics of ICP reveal plasma with high energy and low ion angle distribution, which is necessary for fine definition, high-aspect ratio mesa etching with accurate replication of photolithographic mask dimensions.     

MBE growth of HgCdTe on silicon substrates for large-area infrared focal plane arrays: A review of recent progress

We review the rapid progress that has been made during the past three years in the heteroepitaxial growth of HgCdTe infrared detector device structures on Si substrates by molecular-beam epitaxy. The evolution of this technology has enabled the fabrication of high performance, large-area HgCdTe infrared focal-plane arrays on Si substrates. A key element of this heteroepitaxial approach has been development of high quality CdTe buffer layers deposited on Si(112) substrates. We review the solutions developed by several groups to address the difficulties associated with the CdTe/Si(112) heteroepitaxial system, including control of crystallographic orientation and minimization of defects such as twins and threading dislocations. The material quality of HgCdTe/Si and the performance of HgCdTe detector structures grown on CdTe/Si(112) composite substrates is reviewed. Finally, we discuss some of the challenges related to composition uniformity and defect generation encountered with scaling the MBE growth process for HgCdTe to large-area Si substrates.     

Long wavelength infrared, molecular beam epitaxy, HgCdTe-on-Si diode performance

In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations of high-performance 1024×1024 focal plane arrays (FPAs) using Rockwell Scientific’s double-layer planar heterostructure (DLPH) architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, >5E6 cm⁻²), and these dislocations act as conductive pathways for tunneling currents that reduce the R_oA and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR HgCdTe grown on bulk CdZnTe.     

HgCdTe/Si materials for long wavelength infrared detectors

The heteroepitaxial growth of HgCdTe on large-area Si substrates is an enabling technology leading to the production of low-cost, large-format infrared focal plane arrays (FPAs). This approach will allow HgCdTe FPA technology to be scaled beyond the limitations of bulk CdZnTe substrates. We have already achieved excellent mid-wavelength infrared (MWIR) and short wavelength infrared (SWIR) detector and FPA results using HgCdTe grown on 4-in. Si substrates using molecular beam epitaxy (MBE), and this work was focused on extending these results into the long wavelength infrared (LWIR) spectral regime. A series of nine p-on-n LWIR HgCdTe double-layer heterojunction (DLHJ) detector structures were grown on 4-in. Si substrates. The HgCdTe composition uniformity was very good over the entire 4-in. wafer with a typical maximum nonuniformity of 2.2% at the very edge of the wafer; run-to-run composition reproducibility, realized with real-time feedback control using spectroscopic ellipsometry, was also very good. Both secondary ion mass spectrometry (SIMS) and Hall-effect measurements showed well-behaved doping and majority carrier properties, respectively. Preliminary detector results were promising for this initial work and good broad-band spectral response was demonstrated; 61% quantum efficiency was measured, which is very good compared to a maximum allowed value of 70% for a non-antireflection-coated Si surface. The R₀A products for HgCdTe/Si detectors in the 9.6-μm and 12-μm cutoff range were at least one order of magnitude below typical results for detectors fabricated on bulk CdZnTe substrates. This lower performance was attributed to an elevated dislocation density, which is in the mid-10⁶ cm⁻² range. The dislocation density in HgCdTe/Si needs to be reduced to <10⁶ cm⁻² to make high-performance LWIR detectors, and multiple approaches are being tried across the infrared community to achieve this result because the technological payoff is significant.     

Suppression of strain-induced cross-hatch on molecular beam epitaxy (211)B HgCdTe

Because the performance of HgCdTe-based photodiodes can be significantly degraded by the presence of dislocations, we have systematically investigated and suppressed lattice-mismatch-induced cross-hatch formation and the associated generation of dislocations in (211)B HgCdTe/CdZnTe. A series of HgCdTe epilayers were deposited simultaneously on pairs of substrates with differing ZnTe mole fractions. Epilayers’ CdTe mole fraction and substrates’ ZnTe mole fractions were measured using optical-transmission spectra. Lattice mismatch and residual strain were estimated from room-temperature, x-ray diffraction, and double-crystal rocking-curve measurements (DCRC). It was found that cross-hatch patterns were suppressed in epilayers deposited on nearly lattice-matched substrates (|Δa/a_sub|<0.02%). Such epilayers exhibited excellent crystalline quality as revealed by defect-decoration etching (etch-pit density (EPD)<10⁵ cm⁻²) and x-ray diffraction (full-width at half-maximum (FWHM) ∼10 arcsec). In addition to determining the upper limits of lattice mismatch needed to eliminate cross-hatch, we investigated the use of reticulated substrates as a means to suppress cross-hatch. We found that growth on reticulated mesa structures (<100 μm) with edges parallel to [01-1] resulted in epilayers with substantially reduced cross-hatch-line densities despite large lattice mismatch (Δa/a_sub <0.04%). The use of reticulated substrates could suppress cross-hatch because of lateral-alloy variation in large substrates and complex multistack epilayers (e.g., multicolor detectors).     

Direct growth of CdZnTe/Si substrates for large-area HgCdTe infrared focal plane arrays

Direct epitaxial growth of high-quality 100lCdZnTe on 3 inch diameter vicinal {100}Si substrates has been achieved using molecular beam epitaxy (MBE); a ZnTe initial layer was used to maintain the {100} Si substrate orientation. The properties of these substrates and associated HgCdTe layers grown by liquid phase epitaxy (LPE) and subsequently processed long wavelength infrared (LWIR) detectors were compared directly with our related efforts using CdZnTe/ GaAs/Si substrates grown by metalorganic chemical vapor deposition (MOCVD). The MBE-grown CdZnTe layers are highly specular and have both excellent thickness and compositional uniformity. The x-ray full-width at half-maximum (FWHM) of the MBE-grown CdZnTe/Si increases with composition, which is a characteristic of CdZnTe grown by vapor phase epitaxy, and is essentially equivalent to our results obtained on CdZnTe/GaAs/Si. As we have previously observed, the x-ray FWHM of LPE-grown HgCdTe decreases, particularly for CdZnTe compositions near the lattice matching condition to HgCdTe; so far the best value we have achieved is 54 arc-s. Using these MBE-grown substrates, we have fabricated the first high-performance LWIR HgCdTe detectors and 256 x 256 arrays using substrates consisting of CdZnTe grown directly on Si without the use of an intermediate GaAs buffer layer. We find first that there is no significant difference between arrays fabricated on either CdZnTe/Si or CdZnTe/GaAs/Si and second that the results on these Si-based substrates are comparable with results on bulk CdZnTe substrates at 78K. Further improvements in detector performance on Si-based substrates require a decrease in the dislocation density.     

Relevance of Thermal Mismatch in Large-Area Composite Substrates for HgCdTe Heteroepitaxy

It is well known that the large lattice mismatch (>14%) associated with CdTe/Si, CdTe/Ge, and CdTe/GaAs composite substrates, is a great contributor to large dislocation densities and other defects that limit the performance of HgCdTe-based infrared detectors. Though thermal expansion mismatch is another possible contributor to material defects, little work has been done towards documenting and understanding its effects in these systems. Here, we perform studies to determine the relative contributions of lattice and thermal mismatch to CdTe film characteristics, including dislocation density and residual stress. Unannealed and thermally cycled films are characterized using x-ray diffraction, defect decoration, and Nomarski and transmission electron microscopy. For CdTe/Si, the residual stress is consistently observed to be tensile, while for CdTe/Ge and CdTe/GaAs, a compressive residual film stress is measured. We show based on theoretically predicted stress levels that the experimental measurements imply the dominance of thermal mismatch in the residual stress characteristics.     

异质衬底外延碲镉汞薄膜位错抑制技术进展

分子束外延碲镉汞技术是制备第三代红外焦平面探测器的重要手段,基于异质衬底的碲镉汞材料具有尺寸大、成本低、与常规半导体设备兼容等优点,是目前低成本高性能红外探测器发展中的研究重点。对异质衬底上碲镉汞薄膜位错密度随厚度的变化规律进行了建模计算,结果显示ρ~1/h模型与实验结果吻合度好,异质衬底上原生碲镉汞薄膜受位错反应半径制约,其位错密度无法降低至5×10 6 cm-2以下,难以满足长波、甚长波器件的应用需求。为了有效降低异质外延的碲镉汞材料位错密度,近年来出现了循环退火、位错阻挡和台面位错吸除等位错抑制技术,本文介绍了各技术的原理及进展,分析了后续发展趋势及重点。循环退火和位错阻挡技术突破难度大,发展潜力小,难以将碲镉汞位错密度控制在5×105 cm-2以内。台面位错吸除技术目前已经显示出了巨大的发展潜力和价值,后续与芯片工艺融合后,有望大幅促进低成本长波、中长波、甚长波器件的发展。     

3英寸Si基碲镉汞分子束外延工艺研究

随着红外焦平面阵列规模的扩大,由于尺寸和成本的限制,传统晶格匹配的碲锌镉衬底逐渐成为碲镉汞红外焦平面探测器发展的瓶颈,大尺寸、低成本硅基碲镉汞材料应运而生。本文采用分子束外延工艺生长获得了3 in Si基中波碲镉汞薄膜材料,通过采用金相显微镜、傅里叶红外光谱仪、双晶X射线衍射仪、湿化学腐蚀位错密度(EPD)法、Hall测试系统等检测手段对Si基中波碲镉汞分子束外延薄膜材料进行表面、光学、结构和电学性能表征,并采用标准平面器件工艺制备中波640×512焦平面探测阵列进行材料验证,结果表明该材料性能与国际先进水平相当。     

Threading and misfit-dislocation motion in molecular-beam epitaxy-grown HgCdTe epilayers

Lattice mismatch between the substrate and the absorber layer in single-color HgCdTe infrared (IR) detectors and between band 1 and band 2 in two-color detectors results in the formation of crosshatch lines on the surface and an array of misfit dislocations at the epi-interfaces. Threading dislocations originating in the substrate can also bend into the interface plane and result in misfit dislocations because of the lattice mismatch. The existence of dislocations threading through the junction region of HgCdTe IR-photovoltaic detectors can greatly affect device performance. High-quality CdZnTe substrates and controlled molecular-beam epitaxy (MBE) growth of HgCdTe can result in very low threading-dislocation densities as measured by the etch-pit density (EPD ∼ 10⁴cm⁻²). However, dislocation gettering to regions of high stress (such as etched holes, voids, and implanted-junction regions) at elevated-processing temperatures can result in a high density of dislocations in the junction region that can greatly reduce detector performance. We have performed experiments to determine if the dislocations that getter to these regions of high stress are misfit dislocations at the substrate/absorber interface that have a threading component extending to the upper surface of the epilayer, or if the dislocations originate at the cap/absorber interface as misfit dislocations. The preceding mechanisms for dislocation motion are discussed in detail, and the possible diode-performance consequences are explored.