S 波段连续波速调管宽带输出电路的设计与测试

本文开展了一种用于通信系统的4.6%带宽的S 波段连续波宽带速调管KS4158 的研制工作,重点研究了该速调管的宽带输出电路,详细介绍了宽带输出电路的两种设计方案：滤波器加载重叠模双间隙耦合腔宽带输出电路和三节滤波器加载宽带输出电路。文中还介绍了基于矢量网络分析仪的宽带输出电路的扫频测量法,给出了这两种宽带输出电路的测试结果。最后,给出了分别采用上述两种宽带输出电路方案的两只速调管的测试结果,并对这两种方案进行了分析和比较,其中采用三节滤波器加载宽带输出电路方案的样管的连续波输出功率大于17kW,瞬时带宽大于4.6%。     

An Output Response Analyzer Circuit for ADC Built-in Self-Test

In this paper, a structure of the output response analyzer (ORA) circuit for analog-to-digital converters (ADCs) built-in self-test (BIST) is presented. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to estimate the degradation of signal-to-noise ratio (SNR) value. The appropriate approximations of the testing parameters reduce difficulties in designing the complete ORA circuit. In addition, the feature of reusable hardware in the calculation of sine-wave reference histograms and the computing capability of ADCs’ parameters further improves the ORA design. This design is compact and easily to be adjusted by different setting. The developed ORA circuits are synthesized in a 0.18-μm technology to analyze the outputs of an 8-bit ADC to verify the designs.     

N-phase astable multivibrator †

The conventional way of getting n-phase output From a clock generator involves a counter to base ‘ n ’ with a decoding network or a ring counter or some other arrangement, which can be used only for symmetrical phase outputs. The circuit, described here will give, in its simpler form, symmetrical or asymmetrical n-phase output.     

Correlation properties of a general binary combiner with memory

Correlation properties of a general binary combiner with an arbitrary number M of memory bits are derived and novel design criteria proposed. For any positive integer m, the sum of the squares of the correlation coefficients between all nonzero linear functions of m successive output bits and all linear functions of the corresponding m successive inputs is shown to be dependent upon a particular combiner, unlike the memoryless combiners. The minimum and maximum values of the correlation sum as well as the necessary and sufficient conditions for them to be achieved are determined. It turns out that the security of combiners with memory can be considerably improved if M is not small.An efficient linear sequential circuit approximation (LSCA) method is developed for obtaining output and input linear functions with comparatively large correlation coefficients which is feasible for large M and works for any practical scheme. The method consists in deriving and solving a linear sequential circuit with additional nonbalanced inputs that is based on linear approximations of the output and the component next-state functions. The corresponding correlation attack on combiners with linear feedback shift registers is analyzed and it is shown that every such combiner with or without memory is essentially zero-order correlation immune.A preliminary version of this paper was presented at Eurocrypt '92 and was published in the proceedings. This research was supported in part by the Science Fund of Serbia, Grant #0403, through the Institute of Mathematics, Serbian Academy of Arts and Sciences.     

Multiple-output parity bit signature for exhaustive testing

In this article we propose a multiple-output parity bit signature generation method for exhaustive testing of VLSI circuits. Given a multiple-output combinational circuit, a parity bit signature is generated by first EXORing all the outputs to produce a new output function and then feeding this resulting function to a single-output parity bit signature generator. The method preserves all the desirable properties of the conventional single-output circuits response analyzers and can be readily implemented using the current VLSI technology.     

A high-linear wide-tunable CMOS transconductor for video frequency applications

In this paper a new CMOS transconductor structure based on a g_m-boosted degenerated differential pair is presented for applications in the video frequency range. The proposed circuit combines two techniques, a switchable array of source degenerating MOS resistors and a programmable output current mirror, in order to widen the G_m tuning range while maintaining linearity. Degeneration MOS resistors are made common-mode voltage independent thanks to a simple control circuit. Post-layout simulation results from a 0.35 μm design supplied at 3.3 V show a wide tuning range (10–100 MHz), good linearity (−58.4 dB for an output signal voltage of 1.1 V_p–p) and low excess phase (<0.5° over the whole tuning range).     

Bandwidth optimization of a low power,high speed CMOS current op amp

A current op amp with a differential output and a single-ended input can be configured from a single second generation current conveyor and an output stage with a differential floating current source. Owing to a very simple basic configuration with a single dominant pole, this design combines a high bandwidth with a high open loop gain. In this paper we present the basic configuration, derive the fundamental equations for the performance of the op amp, and describe some design considerations with respect to an optimization of the op amp for a high bandwidth. Simulation results are given from a commercially available 2µm CMOS process resulting in an open loop differential gain of 94dB and a gain-bandwidth product of 128M H z at a supply voltage of 3V and a supply current of 25µA. The design has been experimentally verified through a test circuit and experimental results from this confirm the expected behaviour.     

Test Generation for Mixed-Signal Devices Using Signal Flow Graphs

We describe a new reverse simulation approach to analog and mixed-signal circuit test generation that parallels digital test generation. We invert the analog circuit signal flow graph, reverse simulate it with good and bad machine outputs, and obtain test waveforms and component tolerances, given circuit output tolerances specified by the functional test needs of the designer. The inverted graph allows backtracing to justify analog outputs with analog input sinusoids. Mixed-signal circuits can be tested using this approach, and we present test generation results for two mixed-signal circuits and four analog circuits, one being a multiple-input, multiple-output circuit. This analog backtrace method can generate tests for second-order analog circuits and certain non-linear circuits. These cannot be handled by existing methods, which lack a fault model and a backtrace method. Our proposed method also defines the necessary tolerances on circuit structural components, in order to keep the output circuit signal within the envelope specified by the designer. This avoids the problem of overspecifying analog circuit component tolerances, and reduces cost. We prove that our parametric fault tests also detect all catastrophic faults. Unlike prior methods, ours is a structural, rather than functional, analog test generation method.     

Review of microwave distributed superconducting vortex-flow transistor amplifiers

The dynamics of fluxons in the vortex flow transistor (VFT) has been much studied. The fluxon transit time determines the fundamental speed limit of operation. Since fluxons can travel at the velocity of electromagnetic waves in the junction, the VFT has the potential for operating in high frequency systems ( ≈ 100 GHz). However, owing to the low input and output impedance of the VFT, use of the device in a conventional circuit would be quite limited. A distributed amplifier configuration consisting of many VFTs has been proposed to remedy the problems of low impedance levels. However, the realization of such an amplifier circuit at microwave or millimetre wave frequencies depends on obtaining a circuit model. In this paper, microwave superconducting VFT distributed amplifiers using the balanced control technique is reviewed. This kind of amplifier has the advantage that the capacitive feedthrough effect is decreased to a negligible extent. This is the major limiting factor for high frequency applications. The self-field effect which makes the current step inclined is reduced by injecting bias current only around the region of one end of the junction thus obtaining steeper I- V characteristics. With the asymmetric geometry, the slope of the current step is about one hundred times steeper than those obtained with the conventional overlap geometry. Owing to the diamagnetic behaviour of the Josephson junction, a little of the magnetic field induced by the current in the control line is allowed to penetrate the junction. Thus, the transresistance r_m of a VFT is very small. Some methods for maximizing r_m and minimizing the output impedance r₀ also appear in this review. The feasibility of fabricating VFT distributed amplifiers using low-T_c superconducting material has been demonstrated. The power gain of the amplifier can be as high as 15 dB with a flat frequency response.     

Current-tunable current-mode multifunction filter based on dual-output current-controlled conveyors

In this paper, a current-tunable current-mode multifunction filter with two inputs and two outputs employing only four dual-output current-controlled conveyors (DO-CCCIIs) and two grounded capacitors is proposed. By appropriately connecting the input and output terminals, the proposed circuit can provide lowpass, bandpass, highpass, bandstop and allpass current responses. The filter also offers an independent electronic control of the natural frequency (ω_o) and the quality factor (Q) through adjusting the bias currents of the DO-CCCIIs. No critical matching conditions are imposed for realizing all the filter responses, and all the incremental parameter sensitivities are low. The characteristics of the proposed circuit are simulated using PSPICE to confirm the theory.     

A novel current-mode multiphase sinusoidal oscillator using MO-CDTAs

This article presents a novel current-mode multiphase sinusoidal oscillator. The oscillator can produce two groups of n output currents and one group of 2n output currents (n being even or odd) with equal amplitude and equal-phase space. The circuit only uses one multi-output current differencing transconductance amplifier and one grounded capacitor for each section, and is easy to integrate. Its oscillation condition and frequency can be electronically tuned linearly and independently, and its outputs possess high impedance. It is important that the multi-frequency oscillation in the oscillator is studied and a method for eliminating unnecessary oscillation is given. In addition, the inverting amplifier with the automatic gain control is employed to reduce the distortion of output signals. Finally, the frequency error is analysed and the simulated results are illustrated.     

A Compact C‐Band 50 W AlGaN/GaN High‐Power MMIC Amplifier for Radar Applications

A C‐band 50 W high‐power microwave monolithic integrated circuit amplifier for use in a phased‐array radar system was designed and fabricated using commercial 0.25 μm AlGaN/GaN technology. This two‐stage amplifier can achieve a saturated output power of 50 W with higher than 35% power‐added efficiency and 22 dB small‐signal gain over a frequency range of 5.5 GHz to 6.2 GHz. With a compact 14.82 mm² chip area, an output power density of 3.2 W/mm² is demonstrated.     

Transient power supply current monitoring—A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI _DDQ testing.     

High-gain,high-bandwidth,rail-to-rail,constant-gm CMOS operational amplifier

This study presents a high-gain, high-bandwidth, constant-g_m , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18?µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181?×?173?µm² and it consumes a power of 2.41?mW at a supply voltage of 1.8?V. The op-amp achieves a dc gain of 94.3?dB and a bandwidth of 45?MHz when the output capacitive load is connected to an effective load of 42.5?pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6?mA and an SR of 17?V/µs.     

Fault Diagnosis of Nonlinear Analog Circuits Using Neural Networks with Wavelet and Fourier Transforms as Preprocessors

A neural-network based analog fault diagnostic system is developed for nonlinear circuits. This system uses wavelet and Fourier transforms, normalization and principal component analysis as preprocessors to extract an optimal number of features from the circuit node voltages. These features are then used to train a neural network to diagnose soft and hard faulty components in nonlinear circuits. Our neural network architecture has as many outputs as there are fault classes where these outputs estimate the probabilities that input features belong to different fault classes. Application of this system to two sample circuits using SPICE simulations shows its capability to correctly classify soft and hard faulty components in 95% of the test data. The accuracy of our proposed system on test data to diagnose a circuit as faulty or fault-free, without identifying the fault classes, is 99%. Because of poor diagnostic accuracy of backpropagation neural networks reported in the literature (Yu et al., Electron. Lett., Vol. 30, 1994), it has been suggested that such an architecture is not suitable for analog fault diagnosis (Yang et al., IEEE Trans. on CAD, Vol. 19, 2000). The results of the work presented here clearly do not support this claim and indicate this architecture can provide a robust fault diagnostic system.     

A 0.5 μm Concurrent Testable Chip of a Fifth-Order g m -C Filter

In this paper, we describe a testable chip of a fifth-order g _m -C low-pass filter that has a passband from 0 to 4.5 MHz. We use a current-mode method for the error detection of this filter. By comparing the current consumed by the circuit under test (CUT) and the current converted from the voltage levels of the CUT, abnormal function of circuit components can be concurrently and efficiently detected. A test chip has been fabricated using a 0.5 m, 2P2M CMOS technology. Measurement results show that this current-mode approach has little impact on the performance of the filter and can detect faults in the filter effectively. The area overhead of the circuitry for testing in this chip is about 18%.     

A forward converter topology with independently and precisely regulated multiple outputs

A forward converter topology with independently and precisely regulated multiple outputs is presented in this paper. In this topology, each regulated output has its own feedback control circuit that controls the appropriate synchronous rectifiers in the pertinent output stage. All output circuits are voltage-decoupled from each other, and the cross-regulation between the outputs is eliminated. Steady state analysis as well as small signal modeling is performed to understand the topology and to provide design guidance. A prototype circuit with two outputs is built, and experimental results are presented for proof-of-concept.     

Bounds on pseudoexhaustive test lengths

Pseudoexhaustive testing involves applying all possible input patterns to the individual output cones of a combinational circuit. Based on our new algebraic results, we have derived both generic (cone-independent) and circuit-specific (cone-dependent) bounds on the minimal length of a test required so that each cone in a circuit is exhaustively tested. For any circuit with five or fewer outputs, and where each output has k or fewer inputs, we show that the circuit can always be pseudoexhaustively tested with just 2^k patterns. We derive a tight upper bound on pseudoexhaustive test length for a given circuit by utilizing the knowledge of the structure of the circuit output cones. Since our circuit-specific bound is sensitive to the ordering of the circuit inputs, we show how the bound can be improved by permuting these inputs     

Increasing precision of measuring the radiofrequency dynamic range of a receiver

A circuit of a device for measuring the radiofrequency dynamic range of a receiving unit is suggested, which provides high precision due to the use of digital blocks for determining maximal and minimal signal values at the output peak detectors, connected to the outputs of the selective pass band filters of the linear circuit.     

New electronically tunable current-mode universal biquad filter using translinear current conveyors

In this study, a new electronically tunable current-mode universal filter with two inputs and two outputs employing one translinear current conveyor, one translinear current conveyor with controlled current gain and two grounded capacitors is presented. The proposed circuit offers the following attractive features: realisation of low-pass, band-pass, high-pass, band-stop and all-pass current responses from the same configuration; employment of the minimum active and passive components; no requirement of component matching conditions; independent current-control of the parameters natural frequency (ω_o) and quality factor (Q); low active and passive sensitivities; and high impedance output. The characteristics of the proposed circuit are simulated using PSPICE to confirm the theory.