A GeSi-buffer structure for growth of high-quality GaAs epitaxial layers on a Si substrate

A SiGe-buffer structure for growth of high-quality GaAs layers on a Si (100) substrate is proposed. For the growth of this SiGe-buffer structure, a 0.8-μm Si_0.1 Ge_0.9 layer was first grown. Because of the large mismatch between this layer and the Si substrate, many dislocations formed near the interface and in the low part of the Si_0.1Ge_0.9 layer. A 0.8-μm Si_0.05Ge_0.95 layer and a 1-μm top Ge layer were subsequently grown. The strained Si_0.05Ge_0.95/Si_0.1Ge_0.9 and Ge/Si_0.05Ge_0.95 interfaces formed can bend and terminate the upward-propagated dislocations very effectively. An in-situ annealing process is also performed for each individual layer. Finally, a 1–3-μm GaAs film was grown by metal-organic chemical vapor deposition (MOCVD) at 600°C. The experimental results show that the dislocation density in the top Ge and GaAs layers can be greatly reduced, and the surface was kept very smooth after growth, while the total thickness of the structure was only 5.1 μm (2.6-μm SiGe-buffer structure +2.5-μm GaAs layer).     

Room temperature oxidation of Cu3Ge and Cu3(Si1−xGex) on Si1−xGex

Room temperature oxidation of Cu₃(Si_1−xGe_x) and Cu₃Ge films grown on Si_1−xGe_x at a temperature of 200–400°C was studied using transmission electron microscopy (TEM) in conjunction with energy dispersive spectrometry (EDS). For Cu₃(Si_1−xGe_x) and Cu₃Ge films grown at 200°C and then exposed to air, room temperature oxidation occurred. The Cu₃Ge film was superior to the Cu₃(Si_1−xGe_x) film in reducing the oxidation rate because of its higher Ge concentration. Annealing at higher temperatures such as 400°C resulted in Ge segregation out of the Cu₃(Si_1−xGe_x) film or Si diffusion from the Si_1−xGe_x substrate into the Cu₃Ge overlayer, and hence enhanced the oxidation rate of Cu₃(Si_1−xGe_x) and Cu₃Ge films. The present study shows that upon exposure to air even the Cu₃Ge film grown on Si_1−xGe_x is subject to room-temperature oxidation, revealing that the use of Cu₃Ge contacts on Si_1−xGe_x may be limited by some strict conditions.     

Solid phase epitaxial growth of Dy-germanide films on Ge(0 0 1) substrates

Dy thin films are grown on Ge(0 0 1) substrates by molecular beam deposition at room temperature. Subsequently, the Dy film is annealed at different temperatures for the growth of a Dy-germanide film. Structural, morphological and electrical properties of the Dy-germanide film are investigated by in situ reflection high-energy electron diffraction, and ex situ X-ray diffraction, atomic force microscopy and resistivity measurements. Reflection high-energy electron diffraction patterns and X-ray diffraction spectra show that the room temperature growth of the Dy film is disordered and there is a transition at a temperature of 300-330 °C from a disordered to an epitaxial growth of a Dy-germanide film by solid phase epitaxy. The high quality Dy₃Ge₅ film crystalline structure is formed and identified as an orthorhombic phase with smooth surface in the annealing temperature range of 330-550 °C. But at a temperature of 600 °C, the smooth surface of the Dy₃Ge₅ film changes to a rough surface with a lot of pits due to the reactions further.     

Effects of base layer thickness on reliability of CVD Si3N4 stack gate dielectrics

Effects of the base layer in Si₃N₄/SiON stack gate dielectrics, in particular, the physical thickness of the base layer, on the dielectric reliability, MOSFET performance and process controllability are investigated. It is found that the electrical characteristics such as TDDB lifetime as well as the Si₃N₄ film property in Si₃N₄/SiON stack dielectrics with the same capacitance oxide equivalent thickness strongly depend on the SiON-base layer thickness. From the TDDB measurements for both stress polarities and from the Si₃N₄ stoichiometry by the X-ray photoelectron spectroscopy analysis, the optimum SiON-base layer thickness is determined to be approximately 1 nm, in order to obtain longer TDDB lifetime and surperior n-ch MOSFET performance. The obtained results are considered to attribute to the nitrogen profile in the Si₃N₄/SiON stack dielectrics and the strained layer thickness near SiON/Si interface.     

Growth and electrical properties of the (Si/Ge)-on-insulator structures formed by ion implantation and subsequent hydrogen-assisted transfer

Systematic features of endotaxial growth of intermediate germanium layers at the bonding interface in the silicon-on-insulator structure consisting of buried SiO₂ layer implanted with Ge⁺ ions are studied in relation to the annealing temperature. On the basis of the results for high-resolution electron microscopy and thermodynamic analysis of the Si/Ge/SiO₂ system it is assumed that the endotaxial growth of the Ge layer occurs via formation of a melt due to enhanced segregation and accumulation of Ge at the Si/SiO₂ interface. Effect of germanium at the bonding interface on the Hall mobility of holes in silicon layers with nanometer-scale thickness is studied. It is found that the structures including the top silicon layer with the thickness 3–20 nm and incorporating germanium feature the hole mobility that exceeds by a factor of 2–3 the hole mobility in corresponding Ge-free silicon-on-insulator structures.     

Control of strain relaxation behavior of Ge1−xSnx buffer layers

We have investigated how to realize a strain-relaxed Ge_1−xSn_x layer with large in-plane lattice constant as a buffer layer for a tensile-strained Ge layer. This paper reports the dependence of strain relaxation behavior in Ge_1−xSn_x layers on the misfit strain at the interface between Ge_1−xSn_x layers and substrates. We examined control of the misfit strain by growth of Ge_1−xSn_x layers on bulk-Si and virtual Ge substrates. Large misfit strain between the Ge_1−xSn_x layer and the Si substrate leads to strain relaxation during growth and high degree of strain relaxation after annealing. However, it also leads to interfacial mixing and surface roughening with annealing. As a result, the Ge_1−xSn_x layer having a Sn content of 9.2% was achieved, and it has a potential to induce a tensile strain of 0.99% in Ge layer.     

Anomalous distribution of germanium implanted into a SOI dielectric layer after the annealing of radiation defects

The germanium-distribution profile is investigated in a Si/SiO₂/Si structure after the implantation of ⁷⁴Ge into SiO₂ dielectric layer, bonding with the Si device layer, and high-temperature annealing. The anomalously high transport and accumulation of ⁷⁴Ge atoms near the SiO₂/Si interface far from the bonded boundary is found. The observed ⁷⁴Ge distribution is beyond the framework of the existing model of diffusion of Ge in Si and SiO₂ after postimplantation annealing. A modified model of diffusion of Ge atoms near the Si/SiO₂ interface qualitatively explaining the observed features is proposed.     

Novel Cu/Cr/Ge/Pd Ohmic Contacts on Highly Doped n-GaAs

The thermal stability of the Cu/Cr/Ge/Pd/n⁺-GaAs contact structure was evaluated. In this structure, a thin 40 nm layer of chromium was deposited as a diffusion barrier to block copper diffusion into GaAs. After thermal annealing at 350°C, the specific contact resistance of the copper-based ohmic contact Cu/Cr/Ge/Pd was measured to be (5.1 ± 0.6) × 10⁻⁷ Ω cm². Diffusion behaviors of these films at different annealing temperatures were characterized by metal sheet resistance, X-ray diffraction data, Auger electron spectroscopy, and transmission electron microscopy. The Cu/Cr/Ge/Pd contact structure was very stable after 350°C annealing. However, after 400°C annealing, the reaction of copper with the underlying layers started to occur and formed Cu₃Ga, Cu₃As, Cu₉Ga₄, and Ge₃Cu phases due to interfacial instability and copper diffusion.     

Solid phase reaction of Ti with Si−Ge layers prepared by Ge-implantation

Titanium germanosilicide films from thin Ti films (∼27.5 nm) are formed by solid phase reaction of Ti/Si_0.62Ge_0.38 bilayer at different annealing temperatures ranging from 600°C to 800°C. The effect of crystallographic state of Si−Ge alloy film on the reaction, phase formations, and polymorphic phase transformations, stability of germanosilicides have been investigated by x-ray diffraction, atomic force microscope, and sheet resistance measurements. Both amorphous and relaxed epitaxial Si_0.62Ge_0.38 films are prepared by Ge-multiple implantations into Si wafers with appropriate dose and energy followed by different post-implantation RTA schemes comprising alternative implantation and annealing in on case, and single final annealing in another one. XRD results indicate that the reaction sequence in both cases is found to be Ti/Si like with the formation of C49-Ti(Si−Ge)₂ as a precursor to the low resistivity C54-Ti(Si−Ge)₂. The films formed on amorphous alloy layer exhibit lower polymorphic transition temperature (∼750°C), smoother surface, lower sheet resistance and less agglomeration as compared to those on c:Si−Ge films. These characteristics are due to enhanced nucleation of C54 phase as a result of greater number of nucleation sites in the reaction with amorphous films. The formation of Ti(Si−Ge)₂ films is, however, accompanied by the decrease of Ge content in Ti(Si−Ge)₂ films formed on both amorphous and crystalline alloy films and indicates possible segregation/diffusion effects during the germanosilicidation.     

Post metallization annealing study in La2O3/Ge MOS structure

The study on post metallization annealing (PMA) in electrical characteristics and interfacial properties of La₂O₃/Ge structures has been conducted. The PMA treatment in N₂ ambient induces the growth of interfacial Ge oxide layer accompanied with decrease of capacitance value and interface trap density. The interface-layer growth is caused by the oxidation of Ge substrate due to the hydroxyl group absorbed in La₂O₃ from the ambient. The metal electrode capping might prevent the hydroxyl from evaporating during annealing, which enhances the interface reaction. On the other hand, leakage current increment has been observed for the sample with PMA in case of using Pt gate electrode. It is due to the diffusion of Pt and/or Ge and a Pt-germanide formation in La₂O₃ film during PMA. This leakage current increment can be suppressed by using Ta or W electrode which has less reactivity with Ge than Pt at high temperature.     

Formation of Ni(Ge1−xSnx) layers with solid-phase reaction in Ni/Ge1−xSnx/Ge systems

We have demonstrated the formation of Ni(Ge_1−ySn_y) layers on Ge_1−xSn_x layers by using solid-phase reaction for samples with Sn contents ranging from 2.0% to 6.5%. We have also investigated solid-phase reaction products in Ni/Ge_1−xSn_x/Ge samples after annealing and the crystalline properties of nickel-tin-germanide layer/Ge_1−xSn_x contact structures. After annealing at temperatures ranging from 350 to 550 °C, the formation of polycrystalline Ni(Ge_1−ySn_y) layers has been observed on epitaxial Ge_1−xSn_x layers with Sn contents ranging from 2.0% to 6.5%. We also observed anisotropic crystal deformation of NiGe with the incorporation of Sn atoms into substitutional sites in NiGe. In the case of the Ni/Ge_1−xSn_x/Ge sample with a Sn content of 3.6%, the formation of an epitaxial Ni₂(Ge_1−zSn_z) layer on the Ge_1−xSn_x layer was found. The formation of β-Sn crystallites was observed after annealing at above 450 °C in samples with a high Sn content of 6.5%. This β-Sn formation is due to the precipitation of Sn atoms. In all samples annealed at 350 °C, the morphology of Ni-Ge-Sn layers is smooth and uniform. However, the surface roughness and interface roughness increase for an annealing temperature of 550 °C. In particular, in the sample with a Sn content of 6.5%, the temperature at which agglomeration noticeably occurs is as low as 450 °C.     

Paramagnetic Ge dangling bond type defects at (1 0 0)Si1−xGex/SiO2 interfaces (Invited Paper)

The work addresses the occurrence of Ge dangling bond type point defects at Ge_xSi_1?x/insulator interfaces as evidenced by conventional electron spin resonance (ESR) spectroscopy. Using multifrequency ESR, we report on the observation and characterization of a first nontrigonal Ge dangling bond (DB)-type interface defect in SiO₂/(1 0 0)Ge_xSi_1?x/SiO₂/(1 0 0)Si heterostructures (0.27 ? x ? 0.93) manufactured by the condensation technique, a selective oxidation method enabling Ge enrichment of a buried epitaxial Si-rich SiGe layer. The center, exhibiting monoclinic-I (C_2v) symmetry is observed in highest densities of ～7 × 10¹² cm^?2 of Ge_xSi_1?x/SiO₂ interface for x ～ 0.7, to disappear for x outside the ]0.45–0.87[ interval, with remarkably no copresence of Si P_b-type centers. Neither are trigonal Ge DB centers observed, enabling unequivocal spectral analysis. Initial study of the defect passivation under annealing in molecular H₂ has been carried out. On the basis of all data the defect is depicted as a Ge P_b1-type center, i.e., distinct from a trigonal basic Ge P_b(0)-type center (Ge₃Ge). The modalities of the defect’s occurrence as unique interface mismatch healing defect is discussed, which may widen our understanding of interfacial DB centers in general.     

Compliant substrates: A comparative study of the relaxation mechanisms of strained films bonded to high and low viscosity oxides

Relaxation of compressively strained heteroepitaxial Si_0.7Ge_0.3 films bonded to high and low viscosity glass compliant layers was investigated. These structures were formed by transferring Si_0.7Ge_0.3 films to Si substrates covered with thermal SiO₂ and borophosphorosilicate glass (BPSG) films. Relaxation was studied through thermal annealing experiments. For the low viscosity BPSG, relaxation was observed near 800°C and was accompanied by buckling of the Si_0.7Ge_0.3 film. At this temperature, no change in the Si_0.7Ge_0.3 film bonded to thermal SiO₂ was observed, and through this comparison relaxation on BPSG is interpreted as the result of viscous flow of the glass. Finally, film buckling was successfully avoided by patterning the strained films into small areas prior to annealing, and is an indication that film expansion must be considered for elastic strain relaxation on compliant media.     

Origin of an absorption band peaked at 5560 cm−1 and related to divacancies in Si1−x Gex

It is found that two types of centers are formed in Si_1?x Ge_x single crystals as a result of irradiation with fast electrons: divacancies (V ₂) characteristic of silicon and the V ₂ ^* centers; the latter are complexes of divacancies V ₂ with germanium atoms (V ₂Ge). It is shown that an absorption band peaked at about 5560 cm^?1 is a superposition of two absorption bands that correspond to the above centers. The V ₂ divacancies diffuse during isochronous heat treatment and interact with germanium atoms, thus giving rise to additional V ₂ ^* centers. The latter have a higher thermal stability than the V ₂ centers do, and their annealing temperature increases with increasing content of germanium.     

Control of Interface Traps in HfO2 Gate Dielectric on Silicon

The effects of postdeposition annealing (PDA) on the interface between HfO₂ high-k dielectric and bulk silicon were studied in detail. The key challenges of successfully adopting the high-k dielectric/Si gate stack into advanced complementary metal–oxide–semiconductor (CMOS) technology are mostly due to interfacial properties. We have proposed a PDA treatment at 600°C for several different durations (5 min to 25 min) in nitrogen or oxygen (95% N₂ + 5% O₂) ambient with a 5-nm-thick HfO₂ film on a silicon substrate. We found that oxidation of the HfO₂/Si interface, removal of the deep trap centers, and crystallization of the film take place during the postdeposition annealing (PDA). The optimal PDA conditions for low interface trap density were found to be dependent on the PDA duration. The formation of an amorphous interface layer (IL) at the HfO₂/Si interface was observed. The growth was due to oxygen incorporated during thermal annealing that reacts with the Si substrate. The interface traps of the bonding features, defect states, and hysteresis under different PDA conditions were studied using x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), transmission electron microscopy (TEM), and leakage current density–voltage (J–V) and capacitance–voltage (C–V) techniques. The results showed that the HfO₂/Si stack with PDA in oxygen showed better physical and electrical performance than with PDA in nitrogen. Therefore, PDA can improve the interface properties of HfO₂/Si and the densification of HfO₂ thin films.     

Interfacial reaction and electrical property of Ge/Ni/ZnSe for blue laser diode

Interfacial reaction and electrical property of the Ge/Ni/ZnSe have been investigated as a fundamental study to develop ohmic contacts to p-ZnSe, using x-ray diffraction, Auger electron spectroscopy, cross-sectional transmission electron microscopy, and capacitance-voltage measurement. Ni/ZnSe, Ni/Ge systems have been also studied for comparison with the Ge/Ni/p-ZnSe system and the electrical property could be related to the interfacial reaction. After annealing at 170°C, Ni₃Se₂ and NiGe were formed at Ni/ZnSe and Ge/Ni interface, respectively. The increase of annealing temperature resulted in the decomposition of Ni₃Se₂ through the reaction with Ge. The change of the Schottky barrier height strongly depended on the annealing temperature. According to the result of Ni/ZnSe interface reaction, Ni₃Se₂ in the Ni/ZnSe interface lowered the Schottky barrier height. At higher annealing temperature, the Schottky barrier height increased and it was mainly due to the thermal decomposition of ZnSe.     

Role of a Si0.95Ge0.05 epilayer cap on boron diffusion in silicon under inert and dry oxidizing ambient annealing

Silicon (Si) and Si with a 60 nm Si_0.95Ge_0.05 epilayer cap (Si_0.95Ge_0.05/Si) were implanted with 60 keV, 1×10¹³ cm⁻² boron (B) followed by annealing in nitrogen (N₂) or dry oxygen (O₂) in two different anneal conditions. B⁺implantation energy and dose were set such that the B peak is placed inside Si in Si_0.95Ge_0.05/Si samples and concentration independent B diffusion is achieved upon annealing. For samples annealed above 1075 °C, Ge diffusing from the Si_0.95Ge_0.05 epilayer cap in Si_0.95Ge_0.05/Si samples reached the B layer inside Si and resulted in retarded B diffusion compared to the Si samples. For annealing done at lower temperatures, diffusion of Ge from Si_0.95Ge_0.05 epilayer cap does not reach the B layer inside Si. Thus B diffusion profiles in the Si and Si_0.95Ge_0.05/Si samples appear to be similar. B diffusion in dry oxidizing ambient annealing of Si_0.95Ge_0.05/Si samples further depends on the nature of Si_0.95Ge_0.05 oxidation which is set by the duration and the thermal budget of the oxidizing anneal.     

Strain relaxation and dopant distribution in the rapid thermal annealing of Co with Si/Si1−xGex/Si heterostructure

The reaction of cobalt with the Si-sacrificial cap in the strained Si/Si_1−xGe_x/Si MBE grown heterostructure was studied. The Si-cap is added to prevent the relaxation of the SiGe and to guarantee uniform and reliable silicidation reaction. The Si_1−xGe_x epilayer, with Ge content between 18 and 28 at%, was highly B doped, while the Si-cap was undoped or B doped either during growth or by ion implantation. Cobalt evaporation was followed by rapid thermal annealing at 450–700°C for 30 sec in N₂ or Ar+10%H₂. When the silicide penetrated the Si-cap/Si_1−xGe_x interface, noticeable out-diffusion of Ge and B to the surface was observed. In spite of the presence of the Si-cap significant strain relaxation was observed in three cases: (1) in the implanted samples, although the implantation was confined to the Si-cap, (2) when the Co layer was too thick, such that the silicide penetrated the SiGe layer and (3) when the Ge content in the SiGe layer was relatively high (27.5%).     

The physical properties of CdTe doped with V and Ge

CdTe:(V, Ge) single crystals are grown using the Bridgman-Stockbarger method. The impurity concentrations in the melt are N_V = 1 × 10¹⁹ cm^?3 and N_Ge = 5 × 10¹⁸ and 1 × 10¹⁹ cm^?3. Electrical and galvanomagnetic characteristics are studied in the temperature range 300–400 K. It is found that the equilibrium characteristics are governed by deep levels (ΔE = 0.75–0.95 eV) located close to the midgap. Low-temperature optical absorption spectra indicate that the impurity levels of V and Ge ions in the low-energy region are in different charge states. In addition, the samples are annealed in Cd vapor and then rapidly cooled. This annealing causes the decomposition of various complexes formed during the crystal growth and an increase in both electrical conductivity and charge carrier concentration.