安华高科技门驱动光电耦合器

安华高科技（Avago Technologies）推出两款采用扩展型SSO（Stretched Small Outline）封装的新型门驱动光电耦合器，主要适用干家用电器和工业应用领域的交流和直流无刷电机。ACPL—W302和ACPL—W314光电耦合器的封装尺寸据称比传统的双列直插式封装要小50％，同时产品外形更薄。这些光电耦合器可以实现长达8mm的耙电距离和电气间隙，符合IEC、UL和CSA对增强安全和绝缘调节的要求。ACPL—W302是一款峰值电流为0．4A的隔离门驱动光电耦合器，而ACPL—W314N是一款峰值电流为0．6A的隔离门驱动光电耦合器。这两款产品在1000V的共模电压（VCM）下皆实现了15kV／us的最小共模瞬变免疫性，     

基于2ED020I12-F2的IGBT驱动电路设计

绝缘栅双极型晶体管(IGBT)驱动电路的设计是保证系统可靠运行的重要环节。文中基于英飞凌的磁隔离驱动芯片2ED020I12-F2进行IGBT驱动电路的设计,对2ED020I12-F2的工作过程进行了分析,研究了芯片对IGBT的开通关断及过压过流保护等的工作原理。并运用2ED020I12-F2及其他器件设计了带有变压器隔离与自给电源功能的IGBT驱动电路,且通过实际试验证明了驱动电路设计的正确性与可靠性。     

一种带控制信号的隔离型PWM功率放大器的设计

本文详细介绍了一种带电机方向控制信号的隔离型单极PWM功率放大器的设计原理和实现方法,通过优化栅极驱动电路以减小电路震荡、提高电路效率,通过设计信号、电源三端隔离电路,有效地增强了电路的抗干扰能力和可靠性,本文将重点阐述该种PWM功率放大器的关键技术及其解决方案。     

门极驱动光耦改善电机逆变器精度与效率

在开发可靠并具高成本效益的电动机控制系统时,设计工程师需要能够提供更多保护、更高效益并且能够在高噪声环境下运行的光电耦合器.Avago Technologies(安华高科技)宣布推出了智能型门极驱动光电耦合器产品--ACPL-332J和-331J系列高速绝缘栅双极晶体管(IGBT)光电耦合器非常适于工业逆变器和电源管理应用,如隔离式IGBT/功率MOSFET门极驱动、交流和无刷直流电动机驱动、工业用逆变器和不断电系统等.     

一种高频电磁隔离的驱动方法研究

针对电力电子电路高频化应用趋势,提出了一种高频电磁隔离驱动方法。文中分析了基于数字控制芯片和模拟电路实现电磁隔离驱动的工作原理, 具体给出了硬件电路的设计和软件的配置方法。 该电磁隔离驱动方法,能为脉宽连续变化的控制脉冲提供隔离放大,且脉冲占空比能在 0 ~ 1. 0 的范围内进行调节,除了具有绝缘强度高,抑制共模干扰能力强等优点之外,还具有成本低、动态响应速度快的优点,适用于高功率密度要求下电力电子变换器中开关管的驱动。实验结果表明:研究的驱动方法是行之有效的,具有很好的实际应用价值。     

基于光耦HCPL316J的大功率IGBT驱动电路研究

本文主要对逆变器等功率装置的IGBT驱动电路进行研究,从门极驱动电压、门极驱动电阻、驱动电路功率与IGBT的关系以及驱动保护等方面分析了驱动电路的设计。最后设计了以基于光电耦合器HCPL316J的驱动电路,计算了电路的参数。通过驱动实验和短路保护实验,验证了设计的正确性。     

基于某PWM控制器的雷达伺服直流控制系统设计

设计一个脉宽调制（Pulsewidthmodulates,PWM）控制器的雷达伺服直流控制系统,对整个控制系统的方案背景及模型的建立进行了分析、介绍。该设计对PWM控制器中的脉宽调制电路、隔离驱动电路、功率驱动电路、保护电路等各主要电路分别进行原理或功能上的描述,同时对雷达伺服直流控制系统总体设计及其中的电磁兼容性问题也进行详细的讨论。实验表明,该设计具有较好的动、静态性能,可广泛用于各型雷达伺服直流控制系统中。     

IGBT驱动电路

本文在分析了IGBT驱动条件的基础上介绍了几种常见的IGBT驱动电路,设计了一种基于光耦HCPL-316J的IGBT驱动电路.实验证明该电路具有良好的驱动及保护能力.     

大功率背光源用LED驱动电路的研究现状与进展

结合具体的LED驱动电路控制芯片,对峰值电流控制型、平均电流控制型、单级单开关非隔离型LED驱动电路的原理、优缺点和性能改进措施做了论述。给出了采用频率抖动技术的LED驱动电路的传导EMI峰值及平均值测量结果和基于IR2540的平均电流控制型LED驱动电路的工作波形及效率测量结果,并对脉冲恒流源型LED驱动电路的原理做了简要的介绍,最后从恒流精度、效率、成本3个方面综合分析了LED驱动电路的发展趋势。     

基于IR2136的无刷直流电机驱动电路的设计

实现了一个基于IR2136的适用于无刷直流电机的三相全桥驱动电路的设计。详细介绍了电路的信号隔离模块、逻辑综合电路、三相逆变驱动电路和过流保护电路,并对电路中的关键参数进行了计算分析和选择,最后通过Saber仿真分析软件对设计完成的电路进行了仿真。仿真分析结果证明,电路的设计性能完全满足使用要求。     

High performance damascene metal gate MOSFETs for 0.1 μm regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (~1000°C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450°C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO₂ or Ta₂O₅ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance     

Influences of structure around gate-edge on high electric field strength in MISFETs with high-k gate dielectrics

In this paper, dependences of electric field strength around gate-edge in gate dielectrics of MISFETs with high-k gate dielectrics on design parameters are studied. It is newly found that locations of sidewall/gate dielectric interfaces relative to gate electrode edges are critical to electric field strength of high-k MISFETs. Electric field can be as high as 4 MV/cm, which could have large influences on the yield of large scale integrated circuits (LSIs) with high-k gate dielectrics. An explanation of this phenomenon is given by considering discontinuity in electric field at interfaces between two materials with different dielectric constants. It is clarified that an electrical potential of side and top surfaces of gate dielectrics is strongly affected by the discontinuity of electric field strength at interfaces. As a result, electric field strength around gate electrode edges critically depends on locations of sidewall/gate dielectrics interfaces relative to gate electrode edges. Based on the physical considerations, a structure, in which gate sidewalls are also made of high-k materials, is studied from the viewpoint of electric field strength around gate electrode edges. It is shown that this structure effectively suppresses electric field strength around gate edges.     

Modeling the partition of noise from the gate-tunneling current in MOSFETs

Expressions for the spectral densities of the gate/source and gate/drain noise currents caused by current flow through the gate oxide of MOSFETs are derived. It is shown that these noise currents can also be expressed in terms of equivalent gate and drain noise currents, and by linearizing the position dependence of the gate current density, simple analytic expressions for these equivalent noise currents and their correlation are obtained in terms of the total gate current and the drain/source partition ratio. It is also shown that the predictions of this simple theory are consistent with published experimental data and results from numerical simulations.     

恒压应力下超薄Si_3N_4/SiO_2叠层栅介质与SiO_2栅介质寿命比较

以等效氧化层厚度(EOT)同为2.1nm的纯SiO2栅介质和Si3N4/SiO2叠层栅介质为例,给出了恒定电压应力下超薄栅介质寿命预测的一般方法,并在此基础上比较了纯SiO2栅介质和Si3N4/SiO2叠层栅介质在恒压应力下的寿命.结果表明,Si3N4/SiO2叠层栅介质比同样EOT的纯SiO2栅介质有更长的寿命,这说明Si3N4/SiO2叠层栅介质有更高的可靠性.     

栅压对LDMOS在瞬态大电流下工作的温度影响

研究 LDMOS在一次雪崩击穿后的大电流区,栅压对器件内部温度的影响.结果表明:温度随正栅压升高而升高,随负栅压升高而降低,并分析了有源区内电场强度、电流密度和功率密度随栅压的变化规律.从而证明,与LDMOS栅接地时相比,正栅压降低了器件的静电放电能力,而负栅压则提高了器件的静电放电能力.     

恒电流应力引起HfO_2栅介质薄膜的击穿特性

利用磁控溅射的方法在p- Si上制备了高k(高介电常数)栅介质Hf O2薄膜的MOS电容,对薄栅氧化层电容的软击穿和硬击穿特性进行了实验研究.利用在栅极加恒电流应力的方法研究了不同面积Hf O2 薄栅介质的击穿特性以及击穿对栅介质的I- V特性和C- V特性的影响.实验结果表明薄栅介质的击穿过程中有很明显的软击穿现象发生,与栅氧化层面积有很大的关系,面积大的电容比较容易发生击穿.分析比较了软击穿和硬击穿的区别,并利用统计分析模型对薄栅介质的击穿机理进行了解释     

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options

Novel analytical models for subthreshold current and subthreshold slope of a generic underlap DGMOSFET are proposed. The proposed models are validated with published models, experimental data along with numerical simulation results. The reasonably good agreement shows the accuracy of the proposed model. It is demonstrated how device subthreshold leakage current and subthreshold slope values can be favorably affected by proper back gate biasing, back gate asymmetry and gate work function engineering in combination with gate underlap engineering. It is demonstrated that independent gate operation in combination with gate underlap engineering significantly reduce subthreshold leakage currents as compared to nonunderlap-tied gate DGMOSFET. With the reduction in body thickness, an improvement in subthreshold slope value of underlap 4T DGMOSFET is seen, particularly as back/front gate oxide asymmetry. Developed models demonstrate that asymmetric work function underlap 4T DGMOSFETs would have better device subthreshold slope value along with increased back gate oxide asymmetry.     

Sudden failures associated with the gate oxide of CMOS transistors

Sudden failures appearing during static gate bias — temperature aging of CMOS transistors are investigated in this paper. Shorts between the gate and substrate as well as open gate circuits are found to be failure modes appearing during testing. The subsequent failure analysis reveals that the reaction between the aluminium and gate oxide is the failure mechanism, while defects in P⁺-diffusion regions (which are transferred onto the gate oxide) are the cause of the observed failures.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.     

高k栅介质MOSFET的栅电流模型

提出了包括有限势垒高度下反型层量子化效应以及多晶硅耗尽效应在内的直接隧穿电流模型.在该模型的基础上,研究了采用不同高介电常数栅介质材料时MOSFET的栅电流与介质材料的介电常数、禁带宽度及和Si导带不连续等参数之间的关系.所获得的结果能够为新型栅介质材料的选取提供依据.