Design principles for low-voltage low-power analog integrated circuits

In this paper it is argued that there are good reasons to choose current as the information-carrying quantity in the case of low-voltage low-power design constraints. This paper focuses on the influence of the transfer quality on that choice. To obtain power-efficient transfer quality, indirect feedback is shown to be a good alternative to traditional feedback techniques.     

Mixed Full Adder topologies for high-performance low-power arithmetic circuits

This paper deals with the implementation of Full Adder chains by mixing different CMOS Full Adder topologies. The approach is based on cascading fast Transmission-Gate Full Adders interrupted by static gates having driving capability, such as inverters or Mirror Full Adders, thus exploiting the intrinsic low power consumption of such topologies. The obtained mixed-topology circuits are optimized in terms of delay by resorting to simple analytical models.Delay, power consumption and the Power-Delay Product (PDP) in both mixed-topology and traditional Full Adder chains were evaluated through post-layout Spectre simulations with a 0.35 μm, 0.18 μm and 90 nm CMOS technology considering different design targets, i.e., minimum power consumption, PDP, Energy-Delay Product (EDP) and delay. The results obtained show that the mixed-topology approach based on Mirror adders are capable of a very low power consumption (comparable to that of the low-power Transmission-Gate Full Adder) and a very high speed (comparable with or even greater than that of the very fast Dual-Rail Domino Full Adder). This also enables a high degree of design freedom, given that the same (mixed) topology can be used for a wide range of applications. This greater flexibility also affords a significant reduction in the design effort.     

Vertically integrated sensors for advanced imaging applications

A thin film on ASIC (TFA) image sensor is fabricated depositing an amorphous silicon thin-film detector onto a CMOS ASIC. With regards to advanced imaging systems, TFA provides enhanced performance and more flexibility than conventional technologies. Extensive on-chip signal processing is feasible, as well as small pixels for high resolution imagers. Two new TFA imager prototypes have recently been fabricated. High-resolution image sensor (HIRISE II) with 1024×128 pixels is an active pixel sensor suited for digital photography. Local autoadaptiver sensor (LARS II) with 368×256 pixels splits the illumination information into two signals, thereby providing a dynamic range of more than 120 dB, as required by automotive applications. Both prototypes include correlated double sampling and double delta sampling for efficient suppression of fixed pattern noise     

GaAs low-power integrated circuits for a high-speed digital signalprocessor

A high-speed 4-bit ALU, 4×4-bit multiplier, and 8×8-bit multiplier/accumulator have been implemented in low-power GaAs enhanced/depletion E/D direct-coupled FET logic (DCFL). Circuits are fabricated with a high-yield titanium tungsten nitride self-aligned gate MESFET process. The 4-bit ALU performs at up to 1.2 GHz with only 131-mW power dissipation. The multiplication time for the 4×4-bit array multiplier is 940 ps, which is the fastest multiplication time reported for any semiconductor technology. The 8×8-bit two's complement multiplier/accumulator uses 4278 FETs (1317 logic gates) and exhibits a multiplication time of 3.17 ns. the fastest yet reported for a multiplier of this type. Yield on the best wafer for the 4×4-bit and 8×8-bit circuits is 94 and 43%, respectively. A digital arithmetic subsystem has been demonstrated, consisting of the 8×8-bit multiplier/accumulator, two of the 4-bit ALUs, three logical multiplexers, and a logical demultiplexer. The subsystem performs arithmetic and logic functions required in signal processing at clock rates as high as 325 MHz     

Modeling of the bulk versus SOI CMOS performances for the optimal design of APS circuits in low-power low-voltage applications

In this paper, we present the top-down design of an active pixel sensor (APS) circuit using an analytical model of its architecture. The model is applied to compare the performances of bulk versus silicon-on-insulator (SOI) CMOS processes and devices on the designs and performance of several 50-frames/s imagers in 2-/spl mu/m and 0.25-/spl mu/m CMOS with different pixels array sizes. For 2-/spl mu/m SOI, results show a reduction by two of the power consumption and a dynamic range increase of 0.85 V under a 3-V supply. This results in an SNR of 79 dB instead of 76. Fixed pattern noise (FPN) is also reduced from 2.7 to 1.8 mV which represents 0.26% and 0.08% of the dynamic range, respectively. For 0.25-/spl mu/m CMOS SOI, results show a reduction by 6.5 of the power consumption, FPN more than five time better, and a dynamic range increase of 0.29 V under a 1.5-V supply. However, because of the increase of the thermal noise due to the particular design choice, an SNR of 60.3 dB is achieved compared to 63 in bulk. A better SNR in SOI than in bulk can be achieved but at the expense of power consumption and FPN. However, this could be combined with an increase in pixels number in SOI compared to bulk. Potential results achievable in SOI have to our knowledge never been reached by bulk APS imagers up to now.     

A new systematic design approach for low-power analog integrated circuits

In this paper, a new design approach for systematic design and optimization of low-power analog integrated circuits is presented based on the proper combination of a simulation-equation based optimization algorithm using geometric programming as an optimization approach and HSPICE as a simulation and verification tool by a knowledge-based transistor sizing tool which uses physical-based gm/I_D characteristic in all regions of transistor operation to increase the accuracy in a reasonable simulation time. The proposed design methodology is successfully used for automated design and optimization of an operational amplifier with hybrid-cascode compensation using 0.18 μm CMOS technology parameters with the main purpose of minimizing the power consumption of the circuit.     

A low-power integrated tuner for cable telephony applications

This paper describes an integrated tuner for cable telephony in a 0.35 /spl mu/m, 27 GHz SOI BiCMOS technology. The IC integrates a complete dual-conversion signal path including upconverter, downconverter, variable-gain amplifier, LO synthesizers with fully integrated voltage-controlled oscillators, gain control circuitry, as well as digital calibration and interface circuits. It accepts signals in the 200-880 MHz band and produces a 44 MHz IF. Drawing 168 mA from a 3 V supply, the tuner system has a worst case noise factor of 7.3 dB, system phase noise below -78 dBc/Hz at a 10 kHz offset, spurs below -42 dBc for 137 5 dBmV input channels, a gain of 60 dB, and gain control range of 68 dB. The 13 mm/sup 2/ IC meets specifications across an outdoor temperature range of -40/spl deg/C to 100/spl deg/C in production lots.     

Computation sharing programmable FIR filter for low-power and high-performance applications

This paper presents a programmable digital finite-impulse response (FIR) filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.     

RESURF LDMOSFET with a trench for SOI power integrated circuits

A new structure of RESURF LDMOSFET is proposed, based on silicon-on-insulator, to improve the characteristics of the breakdown voltage and the specific on-resistance, where a trench is applied under the gate in the drift region. A trench is used to reduce the electric field under the gate when the concentration of the drift region is high, thereby increasing the breakdown voltage and reducing the specific on-resistance. Detailed numerical simulations demonstrate the characteristics of this device and indicate an enhancement on the performance of the breakdown voltage and the specific on-resistance in comparison with an optimal conventional device with LOCOS under the gate.     

Underlap channel metal source/drain SOI MOSFET for thermally efficient low-power mixed-signal circuits

In this paper it has been shown that employing an underlap channel created by varying the lateral doping straggle in dopant-segregated Schottky barrier SOI MOSFET not only improves the scalability but also suppresses the self-heating effect of this device. Although in strong inversion region the reduced effective gate voltage due to voltage drop across the underlap lengths reduces the drive current, in weak/moderate inversion region defined at I_D=5 μA/μm and V_DS=0.5 V the analog figures of merit such as transconductance, transconductance generation factor and intrinsic gain of the proposed underlap device are improved by 15%, 35% and 20%, respectively over the conventional overlap channel structure. In addition to this, at V_DD=0.5 V the gain-bandwidth product in a common-source amplifier based on proposed underlap device is improved by ～20% over an amplifier based on the conventional overlap channel device. The mixed-mode device/circuit simulation results of CMOS inverter, NAND and the NOR gates based on these devices also show that at V_DD=0.5 V the switching energy, static power dissipation and the propagation delay in the case of proposed underlap device are reduced by ～10%, ～35% and ～25%, respectively, over the conventional overlap device. Thus, significant improvement in analog figures of merit and the reduction in digital design metrics at lower supply voltage show the suitability of the proposed underlap device for low-power mixed-signal circuits.     

A high-performance lateral geometry transistor for complementary integrated circuits

The lateral geometry transistor has shown itself to be highly useful in the realization of low-frequency integrated circuits. This simple structure has been limited essentially to dc applications, however, by bandwidth and switching time performance. The p-n-p device to be described in this paper substantially overcomes these deficiencies by the addition of an n+ diffusion directly beneath the emitter region. As a result of the steeper gradient at the bulk, or planar, portion of the emitter-base junction, injection occurs primarily near the surface. It is possible to control the dimensions of the buried layer such that injection of carriers greater than a few micrometers from the collector will be minimized. A further consequence of the n+ region is the introduction of a graded base such that minority carrier transport is enhanced. The improved transistor structure has demonstrated the feasibility of obtaining an f_{T} of 10 MHz to 20 MHz at collector currents of 100 µA and rise, fall, and storage times in the tens of nanoseconds.     

Building ultra-low-power high-temperature digital circuits in standard high-performance SOI technology

For ultra-low-power applications, digital integrated circuits may operate at low frequency to reduce dynamic power consumption. At high temperature, the power consumption of such circuits is completely dominated by static power dissipation due to leakage currents. In this contribution, we propose a new logic style, namely ultra-low-power (ULP) logic style which achieves negative V_gs self-biasing, to benefit from the small area and low dynamic power of high-performance deep-submicron SOI technologies while keeping ultra-low leakage, even at high temperature. In 0.13 μm partially-depleted SOI CMOS technology, the static power consumption at 200 °C is reduced by nearly three orders of magnitude at the expense of increased delay and area.     

Novel two-step SDB technology for high-performance thin-film SOI/MOSFET applications

A novel two-step oxided silicon wafer direct bonding process (TSDB) for fabricating high-quality SOI substrates is presented, which has no contamination, no complex thinning process and no subsurface damage. The fracture strength of the SOI/TSDB material is 180 kg/cm/sup 2/. SOI/TSDB NMOS and PMOS devices (0.8-3 mu m) have shown that the typical values of electron and hole surface channel mobility are 680 and 320 cm/sup 2//Vs, respectively. A high device transconductance and high on-off current ratio have also been obtained.<>     

A fully integrated SOI RF MEMS technology for system-on-a-chip applications

In this paper, a silicon-on-insulator (SOI) radio-frequency (RF) microelectromechanical systems (MEMS) technology compatible with CMOS and high-voltage devices for system-on-a-chip applications is experimentally demonstrated for the first time. This technology allows the integration of RF MEMS switches with driver and processing circuits for single-chip communication applications. The SOI high-voltage device (0.7-/spl mu/m channel length, 2-/spl mu/m drift length, and over 35-V breakdown voltage), CMOS devices (0.7-/spl mu/m channel length and 1.3/-1.2 V threshold voltage), and RF MEMS capacitive switch (insertion loss 0.14 dB at 5 GHz and isolation 9.5 dB at 5 GHz) are designed and fabricated to show the feasibility of building fully integrated RF systems. The performance of the fabricated RF MEMS capacitive switches on low-resistivity and high-resistivity SOI substrates will also be compared.     

Comparison of SOI and junction isolation for substrate crosstalksuppression in mixed mode integrated circuits

Using two-dimensional computer simulations and measurements on silicon, it is shown that whereas silicon-on-insulator (SOI) based processes provide high isolation from crosstalk in mixed mode analogue-digital integrated circuits, p-i-n junction isolation can provide equal or better crosstalk immunity with less expense     

Monolithically integrated low-power phototransceivers foroptoelectronic parallel sensing and processing applications

A low-power GaAs-based monolithically integrated phototransceiver, consisting of a high-gain heterojunction phototransistor (WPT) and a microcavity light-emitting diode (MCLED) or a low-threshold vertical-cavity surface-emitting laser (VCSEL), is demonstrated. The HPT and MCLED/VCSEL are grown by molecular-beam epitaxy in a single step. The phototransistor exhibits a responsivity of 60 A/W at an input power of 1 μW. The input and output wavelengths are 850 and 980 nm, respectively. The MCLED-based phototransceiver exhibits an optical gain of 7 dB and power dissipation of 400 μW for an input power of 1.5 μW. The small signal modulation bandwidth is 80 MHz. On the other hand, the VCSEL-based phototransceiver exhibits an optical gain of 10 dB and power dissipation of 760 μW for an input power of 2.5 μW     

Performance characteristics of SOI DRAM for low-power application

Process integration of cell capacitors that can circumvent the usual difficulties of large topographic height difference and high-temperature process are presented. A 16 Mbit silicon-on-insulator (SOI) DRAM with a 0.3 μm design rule is successfully fabricated and analyzed for processing integrity and circuit performance based on process integration of the cell capacitor using the pattern-bonded SOI (PBSOI) technology. Measurements for the strobe access time (tRAC) acid the operation current (I_ccl) show significant improvement (over 25%) for the SOI DRAM compared to those for the 16 Mbit bulk counterpart with the same circuit and layout. On the transistor side, ultra-low-voltage transistor technology using the body bias control schemes is also implemented and investigated. Devices with small leakage current and almost ideal subthreshold swing are obtained. The results give us guidance for transistor and process schematics for low-voltage DRAM application     

Fully integrated blue/UV SOI CMOS photosensor for biomedical and environmental applications

In this paper, we present a microsystem for measuring optical power in blue/UV wavelengths (from λ = 200 nm to λ = 450 nm) which includes a photodiode and the analog processing circuit of the photodiode signal, fully integrated in 2 μm SOI CMOS technology. The photodiode has a maximum responsivity for λ = 400 nm. Th photosensor functions as a current to frequency converter. Measurements of the microsystem illuminated by blue and UV LEDs demonstrate the good linear behavior, sensitivity and efficiency of the system.     

Technology for the design of low-power circuits

Operation of integrated circuits at micropower levels requires transistors with adequate current gain at collector currents of 1 /spl mu/A and less and resistors of the order of 1 M/spl Omega/ within reasonable areas. Factors affecting current gain at low currents are discussed and design criteria presented that optimize gain at low collector current. A benefit of micropower operation is low-current noise. Factors tending to optimize noise performance are discussed. In order to obtain voltage gain at low collector current, high values of load resistance are required. Both passive and active loads suitable for incorporation in micropower integrated circuits are discussed.     

A 900-MHz fully integrated SOI power amplifier for single-chipwireless transceiver applications

This paper presents a silicon-on-insulator (SOI) fully integrated RF power amplifier for single-chip wireless transceiver applications. The integrated power amplifier (IPA) operates at 900 MHz, and is designed and fabricated using a 1.5-μm SOI LDMOS/CMOS/BJT technology. This technology is suitable for the complete integration of the front-end circuits with the baseband circuits for low-cost low-power high-volume production of single-chip transceivers. The IPA is a two-stage Class E power amplifier. It is fabricated along with the on-chip input and output matching networks. Thus, no external components are needed. At 900 MHz and with a 5-V supply, the power amplifier delivers 23-dBm output power to a 50-Ω load with 16-dB gain and 49% power-added efficiency