Rate monotonic scheduling re-analysed

In this paper, we re-analyse the rate monotonic scheduler. Traditionally, the schedulability condition was obtained from the greatest lower bound of utilisation factors over all the task sets that (are schedulable and) fully utilise the processor. We argue that full utilisation is not very appropriate for this purpose. We re-establish Liu and Layland's classic schedulability theorem by finding the greatest lower bound of utilisation factors over all the unschedulable task sets instead. The merits of our approach include: Firstly, the fact that the bound is both sound and tight for schedulability follows directly from definition; Secondly, our proof is simpler technically.     

Sensitivity analysis for fixed-priority real-time systems

At early stages in the design of real-time embedded applications, the timing attributes of the computational activities are often incompletely specified or subject to changes. Later in the development cycle, schedulability analysis can be used to check the feasibility of the task set. However, the knowledge of the worst-case response times of tasks is often not sufficient to precisely determine the actions that would correct a non-schedulable design. In these situations, sensitivity analysis provides useful information for changing the implementation, by giving a measure of those computation times that must be reduced to achieve feasibility, or those that can be increased in case of a product extension, or providing the range of feasible periods for selecting the proper task activation rates. In this work, we exploit the concept of feasibility region to propose a faster and more concise solution to the sensitivity analysis problem with respect to existing techniques based on binary search. Furthermore, we show how the formalization of other problems in the feasibility domain, such as managing overloads through elastic scheduling, can be extended to the exact analysis.     

Iterative Learning Control for uncertain systems: Robust monotonic convergence analysis

In this paper, we present a novel Robust Monotonic Convergence (RMC) analysis approach for finite time interval Iterative Learning Control (ILC) for uncertain systems. For that purpose, a finite time interval model for uncertain systems is introduced. This model is subsequently used in an RMC analysis based on μ analysis. As a result, we can handle additive and multiplicative uncertainty models in the RMC problem formulation, analyze RMC of linear time invariant MIMO systems controlled by any linear trial invariant ILC controller, and formulate additional straightforward RMC conditions for ILC controlled systems. To illustrate the derived results, we analyze the RMC properties of linear quadratic (LQ) norm optimal ILC.     

Worst-case execution-time analysis for embedded real-time systems

In this article we give an overview of the worst-case execution time (WCET) analysis research performed by the WCET group of the ASTEC Competence Centre at Uppsala University. Knowing the WCET of a program is necessary when designing and verifying real-time systems. The WCET depends both on the program flow, such as loop iterations and function calls, and on hardware factors, such as caches and pipelines. WCET estimates should be both safe (no underestimation allowed) and tight (as little overestimation as possible). We have defined a modular architecture for a WCET tool, used both to identify the components of the overall WCET analysis problem, and as a starting point for the development of a WCET tool prototype. Within this framework we have proposed solutions to several key problems in WCET analysis, including representation and analysis of the control flow of programs, modeling of the behavior and timing of pipelines and other low-level timing aspects, integration of control flow information and low-level timing to obtain a safe and tight WCET estimate, and validation of our tools and methods. We have focussed on the needs of embedded real-time systems in designing our tools and directing our research. Our long-term goal is to provide WCET analysis as a part of the standard tool chain for embedded development (together with compilers, debuggers, and simulators). This is facilitated by our cooperation with the embedded systems programming-tools vendor IAR Systems.     

Power efficient rate monotonic scheduling for multi-core systems

More computational power is offered by current real-time systems to cope with CPU intensive applications. However, this facility comes at the price of more energy consumption and eventually higher heat dissipation. As a remedy, these issues are being encountered by adjusting the system speed on the fly so that application deadlines are respected and also, the overall system energy consumption is reduced. In addition, the current state of the art of multi-core technology opens further research opportunities for energy reduction through power efficient scheduling. However, the multi-core front is relatively unexplored from the perspective of task scheduling. To the best of our knowledge, very little is known as of yet to integrate power efficiency component into real-time scheduling theory that is tailored for multi-core platforms. In this paper, we first propose a technique to find the lowest core speed to schedule individual tasks. The proposed technique is experimentally evaluated and the results show the supremacy of our test over the existing counterparts. Following that, the lightest task shifting policy is adapted for balancing core utilization, which is utilized to determine the uniform system speed for a given task set. The aforementioned guarantees that: (i) all the tasks fulfill their deadlines and (ii) the overall system energy consumption is reduced.     

Rate monotonic schedulability tests using period-dependent conditions

Feasibility and schedulability problems have received considerable attention from the real-time systems research community in recent decades. Since the publication of the Liu and Layland bound, many researchers have tried to improve the schedulability bound of the RM scheduling. The LL bound does not make any assumption on the relationship between any of the task periods. In this paper we consider the relative period ratios in a system. By reducing the difference between the smallest and the second largest virtual period values in a system, we can show that the RM schedulability bound can be improved significantly. This research has also proposed a system design methodology to improve the schedulability of real time system with a fixed system load.

实时系统时间并行模型确定性分析

研究实时并行系统的确定性,采用面向执行体构件建模和广义测度固定点理论研究系统收敛条件.把实时系统构建为用时间信号联系的面向执行的构件集合,采用超致密时间(SDT)表示混合系统信号标签模型,定义构件为时间模型上的偏序集函数,构成有反馈作用的偏序集函数组合,用广义超测度空间固定点理论分析时间并行模型因果构件的收敛性和系统响应的存在和唯一性.     

实时系统动态行为模型的一种形式分析方法*

提出了一种基于统一建模语言UML 2.0的实时系统动态行为模型的形式分析方法。首先给出了UML顺序图的形式化描述,分析了UML顺序图中事件之间的关系;在此基础上,给出一种对象自动机来描述每个对象在UML顺序图描述的场景中所参与的事件序列的方法,并将该方法扩展到带有组合片段的UML 2.0顺序图;最后通过分析UML 2.0顺序图中的时间建模机制,给出了从UML 2.0顺序图中提取时间约束得到时间自动机的算法。     

Quantitative analysis of hardware support for real-time operating systems

Microprocessor architects, supported by advances in VLSI technology, have been enormously successful at steadily accelerating the performance of application software. However, operating system performance has lagged due to a divergence between operating system and architectural trends. Unfortunately, some recent work in this area has targeted average-case performance improvements with little or no consideration for the worst-case behavior that must be considered for real-time applications. This paper explores whether one can improve the worst-case performance of operating systems, and as a result, the schedulability of real-time task-sets, using specific hardware-assisted operating system primitives without sacrificing flexibility. The Intel 80960XA Microprocessor, which directly supports basic operating system primitives in hardware, provides an excellent platform to explore operating system hardware and software boundary issues. This paper specifically analyzes the viability of an hardware-assisted fixed-priority scheduler. Using the Real-Time Mach operating system, we did two ports to the 80960XA: one representative of generic RISC implementations, and another which exploited the hardware-supported operating system primitives. We measured the performance of the operating system primitives in both cases and found an average performance improvement factor of 3 for the hardware accelerated version. We applied a formal scheduling model to evaluate the relative performance of the two implementations for two representative real-time applications. The hardware accelerated version reduced operating system burden by factors of 2.66 and 4.1 for the avionics and inertial navigational system task sets, respectively.     

Design optimization for real-time systems with sustainable schedulability analysis

Real-Time Systems - The design of modern real-time systems not only needs to guarantee their timing correctness, but also involves other critical metrics such as control quality and energy...     

Static analysis of real-time distributed systems

A static analysis for reasoning about the temporal behaviors of programs in real-time distributed programming languages is proposed. The analysis is based on the action set semantics using the pure maximal parallelism model. It is shown how to specify and verify various timing properties of real-time programs. The approach provides only an approximate timing behavior, because the state information is ignored. However, many interesting properties such as parallel actions, deadlocks, livelocks, terminations, temporal errors, and failures, can be identified. Furthermore, the approach is compositional and thus makes it possible to reason about the timing properties incrementally. The method not only leads to efficient algorithms for the static analysis of CSP programs but also applies to many other languages     

Transition-aware DVS algorithm for real-time systems using tree structure analysis

Dynamic voltage scaling (DVS) is a key technique for embedded real-time systems to reduce energy consumption by lowering the supply voltage and operating frequency. Many existing DVS algorithms have to generate the canonical schedules or estimate the lengths of slack time in advance for generating the voltage scaling decisions. Therefore, these methods have to compute the schedules with exponential time complexities in general. In this paper, we consider a set of jitter-controlled, independent, periodic, hard real-time tasks scheduled according to preemptive pinwheel model. Our approach constructs a tree structure corresponding to a schedule and maintains the data structure at each early-completion point. Our approach consists of off-line and on-line algorithms which consider the effects of transition time and energy. The off-line and on-line algorithm takes O(k + n log n) and O(k + (p_max/p_min)) time complexity, respectively, where n, k, p_max and p_min denotes the number of tasks, jobs, longest and shortest task period, respectively. Experimental results show that the proposed approach is effective in reducing computational complexity, transition time and energy overhead.     

Modeling and analysis of scheduling for distributed real-time embedded systems

Aimed at the deficiencies of resources based time Petri nets (RBTPN) in doing scheduling analysis for distributed real-time embedded systems, the assemblage condition of complex scheduling sequences is presented to easily compute scheduling length and simplify scheduling analysis. Based on this, a new hierarchical RBTPN model is proposed. The model introduces the definition of transition border set, and represents it as an abstract transition. The abstract transition possesses all resources of the set, and has the highest priority of each resource; the execution time of abstract transition is the longest time of all possible scheduling sequences. According to the characteristics and assemblage condition of RBTPN, the refinement conditions of transition border set are given, and the conditions ensure the correction of scheduling analysis. As a result, it is easy for us to understand the scheduling model and perform scheduling analysis.     

Scheduling analysis based on model checking for multiprocessor real-time systems

Real-time systems (RTS) are omnipresent in several domains. The trend is to use multiprocessor architecture to satisfy the timing constraints of such systems. The model-checking methods have proven to be useful for making the development process reliable at a high abstraction level. Based on this approach, the present paper proposes a new technique for scheduling analysis of a partitioned multiprocessor RTS. Starting from a model with dynamic priority time Petri Nets modeling the system, we have proposed a generation of a reduced states graph. Thus, through the properties of the graph the schedulability is checked. Our approach provides an implementation of a Partition Checker tool, which produces an affirmation of the schedulability or a counterexample in the case of non-schedulable system to reduce the SW/HW space exploration.     

基于多级一致性协议的多核处理器WCET分析方法

由于多核处理器优越的计算性能,多核处理器现已广泛应用在嵌入式实时系统中. 相对于单核处理器,多核处理器存在资源共享竞争、并行任务干扰等因素,尤其是缓存（Cache）一致性问题,导致任务最坏情况执行时间（worst-case execution time,WCET）的预测更加困难.基于以上因素,提出基于多级一致性协议的多核处理器WCET分析方法.该方法针对多级一致性协议体系架构,提出多级一致性域的概念,将多核处理器的数据访问分为域内访问和跨域访问2个层次,根据Cache读写策略和MESI（modify exclusive shared invalid）一致性协议,得出一致性域内部和跨一致性域的Cache状态更新函数,从而实现多级一致性协议嵌套情况下的WCET分析.实验结果表明,在改变Cache配置参数的情况下,该方法分析结果与GEM5仿真结果的变化趋势一致,经过相关性分析,GEM5仿真结果与该方法分析结果相关性系数不低于0.98;在分析精度方面,该方法的平均过估计率为1.30,相比现有方法降低了0.78.

     

Focusing real-time systems analysis on user operations

A way is presented to model and validate complex, real-time systems by describing these systems from the viewpoints of the major parties in system development: the customer, the user, and the implementer. The models representing these points of view are called, respectively, the requirements model, the operations-concept model, and the implementation model. The focus is on how the concept of operations can be formally factored into established real-time system-analysis methods in terms a nontechnical user can understand. The approach integrates and refines several real-time-oriented modeling methods, including structured analysis, finite-state machines, and threads. Modeling needs are discussed, the multiview paradigm is presented, and an extensive example of a bottle-filling system is given to illustrate the use of the method     

Sensitivity analysis of complex embedded real-time systems

The robustness of an architecture to changes is a major concern in the design of efficient and reliable state-of-the-art embedded real-time systems. Robustness is important during design process to identify if and in how far a system can accommodate later changes or updates, or whether it can be reused in a next generation product. In the product life-cycle, robustness helps the designer to perform changes as a result of product updates, integration of new components and subsystems, or modifications of the environment. In this paper we determine robustness as a performance reserve, the slack in performance before a system fails to meet timing requirements. This is measured as design sensitivity. Due to complex component interactions, resource sharing and functional dependencies, one-dimensional sensitivity analysis might not cover all effects that modifications of one system property may have on system performance. One reason is that the variation of one property can also affect the values of other system properties requiring new approaches to keep track of simultaneous parameter changes. In this paper we present a framework for one-dimensional and multi-dimensional sensitivity analysis of real-time systems. The framework is based on compositional analysis that is scalable to large systems. The one-dimensional sensitivity analysis combines a binary search technique with a set of formal equations derived from the real-time scheduling theory. The multi-dimensional sensitivity analysis engine consists of an exact algorithm that extends the one-dimensional approach, and a stochastic algorithm based on evolutionary search techniques.     

Some algorithms for analysis and synthesis of real-time multiprocessor computing systems

The problem of preemptive scheduling in a real-time multiprocessor computing system with release time/deadline intervals is investigated. Approximate algorithms based on the generalization of a single-processor algorithm of relative priority are developed and compared to the exact maximum flow algorithm. An algorithm has been developed for the case where requests for the tasks occur periodically with given periods. An algorithm for determining the values of the processor performance for which there exists an admissible schedule for a given assembly of tasks with release time/deadline intervals has been developed.