A retrospective on the VAX VMM security kernel

The development of a virtual-machine monitor (VMM) security kernel for the VAX architecture is described. The focus is on how the system's hardware, microcode, and software are aimed at meeting A1-level security requirements while maintaining the standard interfaces and applications of the VMS and ULTRIX-32 operating systems. The VAX security kernel supports multiple concurrent virtual machines on a single VAX system, providing isolation and controlled sharing of sensitive data. Rigorous engineering standards were applied during development to comply with the assurance requirements for verification and configuration management. The VAX security kernel has been developed with a heavy emphasis on performance and system management tools. The kernel performs sufficiently well that much of its development was carried out in virtual machines running on the kernel itself, rather than in a conventional time-sharing system     

KSJ－2850机宏指令处理方案的设计与实现

ＫＳＪ－２８５０是我国第一台自主研制ＣＰＵ的、在体系结构级与ＶＡＸ系列兼容的计算机。它在系统设计上的重要技术成果之一是实现了高效率的宏指令处理方案。这一方案的实施对提高ＣＰＵ速度起到了重要作用。本文即介绍它的设计思想和实现方法。     

Microcode Optimization: Examples and Approaches

Firmware engineering strategies range from hand coding to the use of optimizing compilers. For fine-tuned microcode we often need the advantages of both ends of the spectrum.     

数值协处理器微码电路的分析与检测

主要讨论用于完成数值协处理器各种运算的微码电路。简单介绍微码电路在协处理器中的重要性,具体介绍微程序控制模块的工作原理,微码电路的微码地址产生、微程序和微子程序的调用、四阈值微码的译码及微码电路的检测电路。     

Verified microcode design

The avoidance of errors in any engineering profession is highly desirable. The increasing complexity of hardware devices makes the task of producing a correct implementation increasingly difficult using traditional design techniques. Mathematical techniques now appear to offer the opportunity to produce correct designs using a method that can eliminate the introduction of errors. This approach is not only desirable from an ‘academic’ viewpoint but may also become an economic necessity. This paper describes how mathematical transformations on the source code of a programming language were used to aid the development of microcode for the IMS T800 transputer floating-point microprocessor. The process for developing the microcode is demonstrated through a simple example of a single instruction.     

Microcode processing: Positioning and directions

Microcode is an important innovation in computer engineering. the authors discuss the evolution of microcode from its introduction to its decline and to its likely resurgence in custom computing machines. Furthermore, they present a microcoded machine augmented with field-programmable gate arrays (FPGAs) and provide experimental evidence that it can substantially increase the performance of some media benchmarks.     

Microcode Compression Using Structured-Constrained Clustering

Modern microprocessors have used microcode as a way to implement legacy (rarely used) instructions, add new ISA features and enable patches to an existing design. As more features are added to processors (e.g. protection and virtualization), area and power costs associated with the microcode memory increased significantly. A recent Intel internal design targeted at low power and small footprint has estimated the costs of the microcode ROM to approach 20% of the total die area (and associated power consumption). Moreover, with the adoption of multicore architectures, the impact of microcode memory size on the chip area has become relevant, forcing industry to revisit the microcode size problem. A solution to address this problem is to store the microcode in a compressed form and decompress it at runtime. This paper describes techniques for microcode compression that achieve significant area and power savings, while proposes a streamlined architecture that enables high throughput within the constraints of a high performance CPU. The paper presents results for microcode compression on several commercial CPU designs which demonstrates compression ratios ranging from 50 to 62%. In addition, it proposes techniques that enable the reuse of (pre-validated) hardware building blocks that can considerably reduce the cost and design time of the microcode decompression engine in real-world designs.     

Horizon: a retargetable compiler for horizontal microarchitectures

The vertical migration of complex application code into horizontal microcode makes traditional methods of handwritten and hand-optimized microcode with primitive assembly languages impractical. Higher-level languages that permit abstraction from low-level timing and concurrency details are considered a major step toward alleviating the problem. This approach is feasible only if compilers for these languages exist that can produce high-quality microcode and that can be targeted to new machines with modest effort and high reliability. An overview is provided of the Horizon retargetable microcode compiler, which facilitates the production of highly optimized microcode and the targeting of the compiler to specific machines