The electrical and physical analysis of Pt gate/Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

In order to examine the electrical and physical properties of Al₂O₃ layers with dual thickness on a chip, Pt gate/Al₂O₃ with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al₂O₃ layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al₂O₃ layers showed a good leakage current density of −5.4×10⁻⁶ A/cm² and −2.5×10⁻⁹ A/cm² at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×10¹⁰ cm⁻²eV⁻¹ near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al₂O₃ layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al₂O₃ layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al₂O₃ layer and high reliability regions with a thick Al₂O₃ layer.     

Memory Effect of Metal-Insulator-Silicon Capacitor with HfO<Subscript>2</Subscript>-Al<Subscript>2</Subscript>O<Subscript>3</Subscript> Multilayer and Hafnium Nitride Gate

Metal-insulator-silicon capacitors have been fabricated using novel insulators of SiO₂/HfO₂-Al₂O₃-HfO₂ (HAH)/Al₂O₃ and metallic HfN gate, exhibiting a program-erasable characteristic. The memory capacitor presents a large memory window of 2.4 V under +12 V program/–14 V erase for 10 ms, no erase saturation, and sufficient electron- and hole-trapping efficiencies such as an electron density of ∼7 × 10¹² cm^–2 under 13 V program for 0.5 ms and a hole density of ∼4 × 10¹² cm^–2 under –12 V erase for 0.5 ms. The observed properties are attributed to the introduction of high permittivity atomic-layer-deposited HAH/Al₂O₃ as well as high work function HfN gate. The related mechanism is addressed accordingly.     

Pt/Al stacked metals gate MESFET

A new InP MESFET structure both with a gate structure of stacked metal and with a active channel of stacked layer is proposed. The gate metals are constituted by a double metal structure, Pt/Al. It improves the barrier height and reduces the reverse leakage current in the MFSFET. This is due to the formation of Al₂O₃, and becoming a Pt/Al/Al₂O₃/InP, metal-insulating-semiconductor structure in the gate region of the transistor. The conductive channel is constituted by a stack-layered structure, a n-InP layer and an i-InP layer. A transfer characteristics of excellent pitch off, and transconductance of 93 mS/mm is derived. It also shows a negative differential resistance effect on the MESFET. The illumination and temperature effect of the transistor are brought into discussed.     

The electrical properties and stability of the hafnium silicate/Si<Subscript>0.8</Subscript>Ge<Subscript>0.2</Subscript>(100) interface

The effect of post-oxidation N₂ annealing and post-metallization forming-gas annealing on the electrical properties of Pt/Hf-silicate (3 nm)/Si_0.8Ge_0.2(100)/n-type Si(100) metal-oxide semiconductor (MOS) capacitors is reported. Capacitance-voltage (C-V) and current density-voltage (J-V) measurements of asgrown, 3-nm-thick, hafnium-silicate films containing ∼12at.%Hf indicate a large number of bulk and interface traps with a current density of ∼10⁻² A/cm² at V_FB+1 V. Post-ultraviolet (UV)/O₃ oxidation annealing in N₂ at 350°C for 30 min leads to a significant improvement in the electrical characteristics of the film. A post-metallization anneal (PMA) at 450°C for 30 min in forming gas (90% N₂:10% H₂), however, degraded the electrical properties of the films. X-ray photoelectron spectroscopy (XPS) analyses of the forming-gas-annealed films indicate that a possible cause for the degradation in electrical properties is the hydrogen-induced reduction of GeO₂ in the interfacial Si_xGe_1−xO₂ oxide layer to elemental germanium. Implications for the introduction of hafnium silicate as a viable gate dielectric for SiGe-based devices are discussed.     

Protein-Assembled Nanocrystal-Based Vertical Flash Memory Devices with Al<Subscript>2</Subscript>O<Subscript>3</Subscript> Integration

This work presents vertical flash memory devices with protein-assembled PbSe nanocrystals as a floating gate and Al₂O₃ as a control oxide. The advantage of a vertical structure is that it improves cell density. Protein assembly improves uniformity of nanocrystals, which reduces threshold voltage variation among devices. The introduction of Al₂O₃ as a control oxide provided lower voltage/faster operation and hence less power consumption compared with the devices fabricated with SiO₂. The integration of Al₂O₃ appeared to be compatible with the protein assembly approach. In conclusion, Al₂O₃ has the potential to become the high-k control oxide due to its relatively high electron/hole barrier heights, and high permittivity.     

Efficient Outdiffusion of Hydrogen from Mg-Doped Nitrides by NF<Subscript>3</Subscript> Annealing

High concentration (more than 1 × 10¹⁸ cm⁻³) of hydrogen atoms remaining in Mg-doped GaN epitaxial layers grown by metalorganic chemical vapor deposition even after conventional annealing in N₂ ambient could induce degradation in GaN-based devices containing Mg-doped layers. In this study, by annealing Mg-doped nitrides in NF₃ ambient, we successfully reduced residual hydrogen below mid-10¹⁷ cm⁻³, which is much smaller than by N₂ annealing. NF₃ annealing enhances outdiffusion of hydrogen from the bulk, which is possibly because the nitrogen and fluorine radicals decomposed from NF₃ accelerate desorption of hydrogen adatoms from the surface. The proposed method for Mg activation would improve the reliability of GaN-based light-emitting diodes and laser diodes.     

Effect of Rapid Thermal Annealing on Sputtered CaCu<Subscript>3</Subscript>Ti<Subscript>4</Subscript>O<Subscript>12</Subscript> Thin Films

Calcium copper titanium oxide (CaCu₃Ti₄O₁₂, abbreviated to CCTO) films were deposited on Pt/Ti/SiO₂/Si substrates at room temperature (RT) by radiofrequency magnetron sputtering. As-deposited CCTO films were treated by rapid thermal annealing (RTA) at various temperatures and in various atmospheres. X-ray diffraction patterns and scanning electron microscope (SEM) images demonstrated that the crystalline structures and surface morphologies of CCTO thin films were sensitive to the annealing temperature and ambient atmosphere. Polycrystalline CCTO films could be obtained when the annealing temperature was 700°C in air, and the grain size increased signifi- cantly with annealing in O₂. The 0.8-μm CCTO thin film that was deposited at RT for 2 h and then annealed at 700°C in O₂ exhibited a high dielectric constant (ε′) of 410, a dielectric loss (tan δ) of 0.17 (at 10 kHz), and a leakage current density (J) of 1.28 × 10⁻⁵ A/cm² (at 25 kV/cm).     

GaAs-based metal-oxide semiconductor field-effect transistors with Al2O3 gate dielectrics grown by atomic layer deposition

We demonstrate GaAs-based, metal-oxide-semiconductor field-effect transistors (MOSFETs) with excellent performance using an Al₂O₃ gate dielectric, deposited by atomic layer deposition (ALD). This achievement is very significant because Al₂O₃ possesses highly desirable physical and electrical properties as a gate dielectric. These MOSFET devices exhibit extremely low gate-leakage current, high transconductance, and high dielectric breakdown strength. A short-circuit, current-gain, cutoff frequency (f_T) of 14 GHz and a maximum oscillation frequency (f_max) of 25.2 GHz have been achieved from a 0.65-μm gate-length device. The interface trap density (D_it) of Al₂O₃/GaAs is evaluated by the hysteresis of drain-source current, I_ds, versus gate-source bias, V_gs, and the frequency dispersion of transconductance, g_m.     

Trapping and reliability issues in GaN-based MIS HEMTs with partially recessed gate

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al₂O₃. Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator.The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability.     

Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

Comparative study of AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors with Al2O3 and HfO2 gate oxide

AlGaN/GaN metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with Al₂O₃ gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO₂ gate oxide. The capacitance (C)-voltage (V) curve of the Al₂O₃/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C-V curve of the HfO₂/GaN diodes, indicating better quality of the Al₂O₃/GaN interface. The saturation of drain current in the I_D-V_GS relation of the Al₂O₃ AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO₂ AlGaN/GaN MOSHFETs. The gate leakage current of the Al₂O₃ MOSHFET was five to eight orders of magnitude smaller than that of the HfO₂ MOSHFETs.     

Effect of electron trapping on IGFET characteristics

At large applied voltages, electrons flowing from the source to the drain of a n-channel insulated-gate field-effect transistor (IGFET) may gain sufficient energy from the high-field region near the drain to be emitted into the gate insulator layer near the drain junction. The trapping of these hot electrons in the gate insulator results in transconductance degradation and/or threshold voltage shift. There is also evidence of surface-state generation resulting from hot-electron emission into the SiO₂ layer. The extent of the resultant transconductance degradation and/or threshold shift depends strongly on the electron trapping characteristics of the gate insulator. For devices having SiO₂/Si₃N₄ as gate insulator, electron trapping is completely dominated by the Si₃N₄ layer. In this case, channel hot-electron effect results in threshold shift alone. For devices having SiO₂ as gate insulator, the trapping characteristics depend on its positive oxide-charge concentration. In this case, channel hot-electron effect results in a combination of transconductance degradation and threshold shift.     

Influence of Si<Subscript>3</Subscript>N<Subscript>4</Subscript> passivation on surface trapping in SiC metal-semiconductor field-effect transistors

The SiC metal-semiconductor field-effect transistors (MESFETs) have been reported to have current instability and strong dispersion caused by trapping phenomena at the surface and in the substrate, which degrade direct-current (DC) and radio-frequency (RF) performance. This paper illustrates the change in electrical characteristics of SiC MESFETs after Si₃N₄ passivation. Because of a reduction of surface trapping effects, Si₃N₄ passivation can diminish current collapse under pulsed DC conditions, increasing the RF power performance. The reduction of surface trapping effects is verified by the change in the ratio of the drain current to the gate current under pinch-off conditions.     

Drain current enhancement and negligible current collapse in GaN MOSFETs with atomic-layer-deposited HfO2 as a gate dielectric

Accumulation-type GaN metal-oxide-semiconductor field-effect-transistors (MOSFET’s) with atomic-layer-deposited HfO₂ gate dielectrics have been fabricated; a 4 μm gate-length device with a gate dielectric of 14.8 nm in thickness (an equivalent SiO₂ thickness of 3.8 nm) gave a drain current of 230 mA/mm and a broad maximum transconductance of 31 mS/mm. Owing to a low interfacial density of states (D_it) at the HfO₂/GaN interface, more than two third of the drain currents come from accumulation, in contrast to those of Schottky-gate GaN devices. The device also showed negligible current collapse in a wide range of bias voltages, again due to the low D_it, which effectively passivate the surface states located in the gate-drain access region. Moreover, the device demonstrated a larger forward gate bias of +6 V with a much lower gate leakage current.     

Effect of partial la filling on high-temperature thermoelectric properties of IrSb<Subscript>3</Subscript>-based skutterudite compounds

We previously reported that IrSb₃-based ternary compounds showed good electrical properties and that relatively high thermal conductivity prevented the enhancement of the efficiency of these compounds.¹ Recently, we have investigated the high-temperature thermoelectric properties of La-filled IrSb₃-based skutterudite compounds from the viewpoint of a decrease in lattice thermal conductivity. It has been confirmed from Rietveld analysis that the La ions are partially placed in cages of La-filled and Ge-charge-compensated La_YIr₄Ge_3YSb_12−3Y compounds and 53% filling of La ions is obtained. Owing to the rattling effect of La ions in cages, the La-filled and Ge-charge-compensated La_YIr₄Ge_3YSb_12−3Y compounds exhibit tremendously decreased lattice thermal conductivity at room temperature, 1.8 W/mK from 10.2 W/mK of binary IrSb₃.     

High electric-field-induced strain beahvior of single-crystal Pb(Mg<Subscript>1/3</Subscript>Nb<Subscript>2/3</Subscript>)O<Subscript>3</Subscript>-xPbTiO<Subscript>3</Subscript> multilayer piezoelectric actuators

Two 10-mm-long multilayer prototype actuators were fabricated by a stack method using 55 pieces of 5 mm×5 mm×0.15 mm Pb(Mg_1/3Nb_2/3)O₃-xPbTiO₃ (PMNT) single crystals and PZT-5A ceramics, respectively. The strain values for PMNT multilayer piezoelectric actuators are twice those of PZT-5A multilayer actuators, and 20.8-μm displacements can be achieved at the same E-field of 15 kV/cm. Although thermal and electrical history markedly impact dielectric and piezoelectric performance of PMNT crystals, the PMNT multilayer actuator can still achieve large displacements with approximately linear behavior below 60°C. Broad stable dynamic displacement characteristic and fast displacement response make the new-type actuators promising candidates for the application in new-generation high-performance solid-state actuators.     

Modeling the effect of thin gate insulators (SiO2, SiN,Al2O3 and HfO2) on AlGaN/GaN HEMT forward characteristics grown on Si,sapphire and SiC

GaN-based high electron mobility transistors (HEMTs) with a Schottky metal gate have been demonstrated to be an excellent candidate for high frequency, high temperature and high power applications. Nevertheless, their typical (and virtually inevitable) high gate leakage current, severely limits gate voltage swing, output power and breakdown voltage. GaN metal–insulator –semiconductor HEMTs or MIS-HEMTs (formed by introducing a thin dielectric film between the gate metal and semiconductor) is one of the effective solutions that reduce gate leakage and improve device performance. In this work, we evaluate the effect that the introduction of this gate insulator has on the on-state of the HEMT. For this reason, we develop a complete set of compact closed-form expressions for the evaluation of on-resistance, drain and saturation current and transconductance for a MIS-HEMT. This physical-based model describes the mobility in a 2D electron gas channel by means of optical phonon scattering and is explored with insulators based on SiO₂, SiN_x, Al₂O₃, and HfO₂.     

Microstructure and Characteristics of Thin-Film La<Subscript>0.8</Subscript>Sr<Subscript>0.2</Subscript>Co<Subscript>0.5</Subscript>Ni<Subscript>0.5</Subscript>O<Subscript>3</Subscript>/ZnO:Al Heterocontact CO Sensors Prepared by RF Magnetron Sputtering

Highly sensitive CO gas sensors based on heterocontacts of ZnO:Al on La_0.8Sr_0.2Co_0.5Ni_0.5O₃ (LSCNO) were fabricated successfully. La_0.8Sr_0.2Co_0.5Ni_0.5O₃ thin films were coated on (100) silicon wafers by a sol-gel method including the Pechini process followed by a spin-coating procedure. Then, ZnO:Al films prepared by radiofrequency (RF) magnetron sputtering at various oxygen partial pressures and deposited on as-deposited La_0.8Sr_0.2Co_0.5Ni_0.5O₃ films were investigated. The results revealed that the CO sensing ability of the film prepared with the ratio of O₂/Ar = 5/5 (ratio of volume flow rate) was the worst, owing to the highest (002) plane orientation in the ZnO:Al film. In contrast, the ZnO:Al film prepared with O₂/Ar = 3/7 exhibited better CO sensitivity. Furthermore, all two-layer samples showed higher CO sensitivities than single-layer samples. The CO sensitivity of ZnO:Al/La_0.8Sr_0.2Co_0.5Ni_0.5O₃ thin film was 45% for 500 ppm CO at a sensing temperature of 200°C.     

The properties of photo chemical-vapor deposition SiO<Subscript>2</Subscript> and its application in GaN metal-insulator semiconductor ultraviolet photodetectors

High-quality SiO₂ insulating layers were successfully deposited onto GaN by a photo chemical-vapor deposition (photo-CVD) technique using a deuterium (D₂) lamp as the excitation source. The interface-trap density, D_it, was estimated to be 8.4×10¹¹ cm⁻²eV⁻¹ for the photo-CVD SiO₂ layers prepared at 300°C. It was found that the leakage current was only 6.6×10⁻⁷ A/cm² with an applied field of 4 MV/cm for the 300°C photo-CVD-grown Al/SiO₂/GaN metal-insulator semiconductor (MIS) capacitor. It was also found that the photo-CVD SiO₂ layer could be used to suppress the dark current of nitride-based photodetectors. A large photocurrent to dark-current contrast ratio higher than three orders of magnitude and a maximum 0.12 A/W responsivity were observed from the fabricated indium tin oxide (ITO)/photo-SiO₂/GaN MIS ultraviolet (UV) photodetectors. Furthermore, it was found that corresponding noise-equivalent power (NEP) and normalized detectivity, D*, of our ITO/photo-SiO₂/GaN MIS UV photodetectors was 2.19×10⁻⁹ W and 2.03 × 10⁸ cmHz_0.5W⁻¹, respectively, for a given bandwidth of 500 Hz.     

Growth and doping of SiC-thin films on low-stress,amorphous Si<Subscript>3</Subscript>N<Subscript>4</Subscript>/Si substrates for robust microelectromechanical systems applications

The N₂-doped 3C-SiC thin films have been grown by low-pressure, chemical vapor deposition (LPCVD) on amorphous Si₃N₄/p-Si (111) substrates using the single, organosilane-precursor trimethylsilane [(CH₃)₃SiH]. The effects of N₂ flow rate and growth temperature on the electrical properties of SiC films were investigated by Hall-effect measurements. The electron-carrier concentration is between 10¹⁷–10¹⁸/cm³. The lowest resistivities at 400 K and 300 K are 1.12×10⁻² and 1.18×10⁻¹ cm, respectively. The corresponding sheet resistances are 75.02 Ω/□ and 790.36 Ω/□. The SiC film structure was studied by x-ray diffraction. The 3C-SiC films oriented in the 〈111〉 direction with a 2ϑ peak at 35.5° and line widths between 0.18–0.25° were obtained. The SiC/Si₃N₄ interface is very smooth and free of voids. The fabrication of microelectromechanical (MEMS) structures incorporating the SiC films is discussed.