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SDH指针调整引起的抖动是SDH网中重要的传输损伤,如何抑制指针调整引起的抖动已经成为SDH系统设计中一个关键的问题,本文提出一种能有效减低抖动的方法-调制前馈泄漏法,并对这种方法进行了理论分析和计算。 相似文献
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道德介绍了用计算机模拟计算SDH提针调整抖动的方法,并给出了模拟结果。然后,在采用了抑制指针高速抖动的自适应比特泄漏技术的基础上,研究了PDH信号在SDH和PDH混合网中传输时指针调整拌动的积累规律。 相似文献
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光同步数字传输网由于采用指针调整技术进步同步复用,可能会给经由SDH传送的准同步数字信号带来较大的抖动损伤。道德给出了计算机模拟计算SDH指针调整在PDH信号上产生抖动的方法及其模拟结果,然后对这种抖动进行了理论分析。 相似文献
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SDH指针调整技术的研究 总被引:1,自引:0,他引:1
本文首先讲述了SDH的指针调整原理,并举例说明了指针调整时指针字节各比特状态的变化过程,接着论述了指针调整对PDH支路信号所造成的传输损伤,介绍了一种减小指针调整引入抖动的解同步器,讨论了SDH/PDH混合网抖动累积的统计规律。 相似文献
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抑制SDH网中指针调整抖动方法的研究 总被引:1,自引:0,他引:1
本文提出了一种基于预测算法的SDH去同步器,以消除由于SDH网中指针调整引起的低频、大幅度相位跃变所产生的抖动。本文对这种去同步器给出了详细设计方法,并对输出时钟的抖动进行了数学分析,证明该方法能有效地滤除由于指针调整引起的抖动。 相似文献
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本文首先介绍了抖动的基本概念以及SDH系统指针调整引入抖动的机理;接着着重讨论了降低SDH网络指针调整引入抖动的原理并给出PLL型去同步器和两种新型去同步器;最后指出采用上述原理的去同步器,在其SDH系统中高达4.6ppm时钟频漂情况下可使输出抖动降至0.6UI以下。 相似文献
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本文首先介绍了抖动的基本概念以及SDH系统指针调整引入抖动的机理;接着着重讨论了降低SDH网络指针调整引入抖动的大批量并给出PL型去同步器和两种新型去同步器;最后指出采用上述原理的去同步器,在其SDH系统中高达4.6ppm时钟频漂情况下可使输出抖动降至0.6UI以下。 相似文献
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由于工作的原因 ,参加了某省广电系统有线电视SDH传输网的建设 ,在整个网络的设计和施工过程中发现有线电视在SDH网络中传输有以下几个问题需要加以注意。1 时钟与同步(1)SDH网中信号的同步机理是采用指针调整 ,通过指针调整进行信号的相位校准 ,它不同于PDH所采用的正 /负码速调整技术。在SDH网中可能出现SDH线路抖动。同步分配网中由于随机噪声引起同步信号的漂移及PDH码速调整技术的不同 ,PDH支路信号映射至SDH信号时信号发生相位变化 ,在PDH/SDH边界上引起附加抖动和漂移 ,对视频信号而言 ,将造成可… 相似文献
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塞入式调整与指针调整是用在同步数字体系(SDH)传输系统中的技术,文章将对这两种技术的实现原理、各自特点作详细的比较,对其产生的候时抖动进行分析,并给出实现去抖动的方法。 相似文献
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Pulse stuffing and pointer adjustment are necessary for clock rate adaptation in synchronizers used in synchronous digital transmission networks (e.g.,, SDH/SONET). The method of adaptive threshold modulation (AT-Mod) may be used in the synchronizer to reduce the resulting waiting time jitter. This paper in detail addresses the performance of the method of AT-Mod technique. Using a nonlinear model to represent the thresholder, the paper provides mathematical expressions for the filtered jitter power resulting from AT-Mod in the synchronizer. The accuracy of using such a nonlinear technique is also demonstrated. Furthermore, the possibility of improving the AT-Mod circuit for further jitter reduction is discussed. Because the improved AT-Mod circuits are not always guaranteed to be stable, a stability analysis is presented. The impact of input noise on the filtered jitter is also investigated in the paper 相似文献
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The timing jitter induced by pointer adjustments in the basic STM-1 frame represents a serious technical problem in SDH-based networks. This paper describes two jitter reduction techniques to cope with this phenomenon. The first technique is based on digital phase-lock loop (PLL) theory, and obtained through two structural modifications of a previously proposed desynchronizer. The second technique is entirely novel, and it avoids the generation of the random noise with uniform probability density, which is required in PLL-type desynchronizers to smooth the 1-b phase steps at the output of the first stage. We describe two different methods to adapt the speed of this desynchronizer to the incoming pointer adjustment statistics. The performance of both jitter reduction techniques is investigated in both the normal mode and the degraded mode of operation of the network. Using a design example, it is shown that the peak-to-peak jitter in the presence of isolated pointer adjustments that characterize the normal operation mode is kept below 0.1 b. It is also shown that with frequency offsets up to 4.6 ppm in the degraded mode, the peak-to-peak jitter does not exceed 0.6 b. Lower jitter values are achievable if the complexity and memory requirements of the desynchronizer are allowed to increase 相似文献