On the multiple negative-differential-resistance (MNDR) InGaP-GaAsresonant tunneling bipolar transistors

Two InGaP/GaAs resonant tunneling bipolar transistors (RTBTs) with different superlattice (SL) structures in the emitters are fabricated and studied. The uniform and modulated widths of barriers are respectively utilized in the specific SL structures. Based on the calculations, the ground state and first excited state minibands are estimated from the transmission probability. The electron transport of RT through SL structures is significantly determined by the electric field behaviors across the barriers. Experimentally, the excellent transistor characteristics including the small saturation voltage, small offset voltage and high breakdown voltages are obtained due to the insertion of δ-doping sheet at the base-collector (B-C) heterointerface. Furthermore, at higher current regimes, the double- and quaternary-negative difference resistance (NDR) phenomena are observed in agreement with the theoretical prediction at 300 K     

Heterojunction vertical FETs revisited: potential for 225-GHzlarge-current operation

The high-speed operation of submicrometer Al_xGa_1-x As/GaAs unipolar heterojunction transistors is examined using two-dimensional time-dependent self-consistent ensemble Monte Carlo simulation. Careful device design can significantly increase ballistic injection over the heterojunction in steady state by eliminating retarding gate-induced space-charge reversal there. Design for optimal large-signal transient operation must also avoid gate-voltage-dependent ballistic injection. General design principles for optimizing high-speed operation are proposed. The resulting VFETs show cutoff frequencies of 225 GHz at large drain currents at 300 K, with frequency-independent two-port y parameters     

Ballistic transport in high electron mobility transistors

A general ballistic FET model that was previously used for ballistic MOSFETs is applied to ballistic high electron mobility transistors (HEMTs), and the results are compared with experimental data for a sub-50 nm InAlAs-InGaAs HEMT. The results show that nanoscale HEMTs can be modeled as an intrinsic ballistic transistor with extrinsic source/drain series resistances. We also examine the "ballistic mobility" concept, a technique proposed for extending the drift-diffusion model to the quasi-ballistic regime. Comparison with a rigorous ballistic model shows that under low drain bias the ballistic mobility concept, although nonphysical, can be used to understand the experimental phenomena related to quasi-ballistic transport, such as the degradation of the apparent carrier mobility in short channel devices. We also point out that the ballistic mobility concept loses validity under high drain bias. The conclusions of this paper should be also applicable to other nanoscale transistors with high carrier mobility, such as carbon nanotube FETs and strained silicon MOSFETs.     

nanoMOS 2.5: A two-dimensional simulator for quantum transport in double-gate MOSFETs

A program to numerically simulate quantum transport in double gate metal oxide semiconductor field effect transistors (MOSFETs) is described. The program uses a Green's function approach and a simple treatment of scattering based on the idea of so-called Buttiker probes. The double gate device geometry permits an efficient mode space approach that dramatically lowers the computational burden and permits use as a design tool. Also implemented for comparison are a ballistic solution of the Boltzmann transport equation and the drift-diffusion approaches. The program is described and some examples of the use of nanoMOS for 10 nm double gate MOSFETs are presented.     

Ballistic Spin Hall Transistor Using a Heterostructure Channel and Its Application to Logic Devices

In a ballistic spin transport channel, spin Hall and Rashba effects are utilized to provide a gate-controlled spin Hall transistor. A ferromagnetic electrode and a spin Hall probe are employed for spin injection and detection, respectively, in a two-dimensional Rashba system. We utilize the spin current of which polarization direction is controlled by the gate electric field which determines the strength of the Rashba effective field. By observing the spin Hall voltage, spin injection and coherent spin precession are electrically monitored. From the original Datta–Das technique, we measure the channel conductance oscillation as the gate voltage is varied. When the magnetization orientation of the injector is reversed by 180°, the phase of the Datta–Das oscillation shifts by 180° as expected. Depending on the magnetization direction, the spin Hall transistor behaves as an n- or p-type transistor. Thus, we can implement the complementary transistors which are analogous to the conventional complementary metal oxide semiconductor transistors. Using the experimental data extracted from the spin Hall transistor, the logic operation is also presented.     

Co-integration of resonant tunneling and double heterojunctionbipolar transistors on InP

The authors report the first co-integration of resonant tunneling and heterojunction bipolar transistors. Both transistors are produced from a single epitaxial growth by metalorganic molecular beam epitaxy, on InP substrates. The fabrication process yields 9-μm²-emitter resonant tunneling bipolar transistors (RTBTs) operating at room temperature with peak-to-valley current ratios (PVRs) in the common-emitter transistor configuration, exceeding 70, at a resonant peak current density of 10 kA/cm², and a differential current gain at resonance of 19. The breakdown voltage of the In_0.53Ga_0.47As-InP base/collector junction, V_CBO, is 4.2 V, which is sufficient for logic function demonstrations. Co-integrated 9-μm²-emitter double heterojunction bipolar transistors (DHBTs) with low collector/emitter offset voltage, 200 mV, and DC current gain as high as 32 are also obtained. On-wafer S-parameter measurements of the current gain cutoff frequency (f_T) and the maximum frequency of oscillation (f_max) yielded f _T and f_max values of 11 and 21 GHz for the RTBT and 59 and 43 GHz for the HBT, respectively     

Semiconductor devices for RF applications: evolution and current status

This paper reviews the history, evolution, current status, and applications of semiconductor devices for radio frequency (RF) applications. The most important developments and major milestones leading to modern high-performance RF transistors are presented. Heterostructures, which are key elements for some advanced RF transistors, are described, and an overview of the different transistor types and their figures of merit is given. Applications of RF transistors in civil RF systems with special emphasis on wireless communication systems are addressed, and the issues of transistor reliability are also briefly discussed.     

Theory of ballistic nanotransistors

Numerical simulations are used to guide the development of a simple analytical theory for ballistic field-effect transistors. When two-dimensional (2-D) electrostatic effects are small (and when the insulator capacitance is much less than the semiconductor (quantum) capacitance), the model reduces to Natori's theory of the ballistic MOSFET. The model also treats 2-D electrostatics and the quantum capacitance limit where the semiconductor quantum capacitance is much less than the insulator capacitance. This new model provides insights into the performance of MOSFETs near the scaling limit and a unified framework for assessing and comparing a variety of novel transistors.     

A new charge-control model for single- and double-heterojunctionbipolar transistors

A new charge-control relation is derived for heterojunction bipolar transistors. The relation is valid for arbitrary doping density profiles and for all levels of injection in the base. It is applicable to both single- and double-heterojunction transistors. The model is an improvement over another recently proposed charge-control model that was valid only for constant doping density and low injection in the base. Large- and small-signal equivalent circuit models are also presented for heterojunction bipolar transistors. Comparisons with numerical and experimental data show excellent agreement     

77K多晶硅发射区双极型晶体管

本文介绍了适于77K工作的多晶硅发射区双极型晶体管,给出了在不同工作电流条件下的电流增益的温度模型。结果表明在小电流条件下电流增益随温度下降而下降得更为剧烈,并且讨论了在不同注入情况下,浅能级杂质的陷阱作用对截止频率的影响。     

Experimental Investigations on Carrier Transport in Si Nanowire Transistors: Ballistic Efficiency and Apparent Mobility

As devices continue scaling down into nanometer regime, carrier transport becomes critically important. In this paper, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top–down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is adopted, which takes into account the impact of temperature dependence of parasitic source resistance in SNWTs. The highest ballistic efficiency at room temperature is observed in sub-40-nm n-channel SNWTs due to their quasi-1-D carrier transport. The apparent mobility of GAA SNWTs are also extracted, showing their close proximity to the ballistic limit as shrinking the gate length, which can be explained by Shur's model. The physical understanding of the apparent mobility in SNWTs is also discussed using flux's scattering matrix method.      

Lateral Injection Utilized for Improving the Performance of Microwave Bipolar Transistors

An experimental evaluation is presented concerning the common-emitter parameters and output current–voltage characteristics of chip n–p–n transistors that are designed for pulsed conditions and have gain–bandwidth products, f _T, higher than 300 MHz. The configuration of the emitter and collector junctions essentially embodies a new concept whereby injection efficiency is increased by lateral injection. It is shown that the new approach enables one to improve transistor performance. Some process techniques for the transistors are described.     

Non-quasi-static models including all injection levels and DC, AC,and transient emitter crowding in bipolar transistors

Two-dimensional equivalent-circuit models for bipolar junction transistors are systematically derived by solving the continuity equations for DC, AC, and transient excitations. These models take into account carrier propagation delay, all injection levels, as well as exponential doping profiles. They include analytically DC, AC, and transient emitter crowding in a more detailed and accurate manner than previously available. Extensions of the models to accommodate arbitrarily doped and heavily doped quasi-neutral layers and to include energy-gap narrowing due to the electron-hole plasma present at high current density are described. The analysis leads to compact large- and small-signal equivalent-circuit lumped models, suitable for use in circuit simulators such as SPICE. The analytical solutions obtained reveal the two-dimensional distribution of the current and carrier densities in the intrinsic base layer and the onset of emitter crowding. They also provide information for the extraction of the intrinsic base resistance. Several assumptions made in the derivations are assessed by the computer program PISCES. The methods presented apply to both homojunction and heterojunction bipolar transistors     

Low frequency noise in complementary npn and pnp polysilicon emitter bipolar junction transistors

Low frequency noise characteristics of high voltage, high performance complementary polysilicon emitter bipolar transistors are described. The influence of the base biasing resistance, emitter geometry and temperature on the noise spectra are discussed. The npn transistors studied exhibited 1/f and shot noise, but the pnp transistors are characterized by significant generation–recombination noise contributions to the total noise. For both types of transistors, the measured output noise is determined primarily by the noise sources in the polysilicon–monosilicon interface. The level of the 1/f noise is proportional to the square of the base current for both npn and pnp transistors. The contribution of the 1/f noise in the collector current is also estimated. The area dependence of 1/f noise in both types of transistors as well as other npn bipolar transistors are presented.     

Integrated injection logic-present and future

Integrated injection logic (I/SUP 2/L) or merged transistor logic (MTL) incorporating lateral p-n-p transistors as current sources and multicollector n-p-n transistors as invertors, are discussed. Speed-power products of 0.13 pJ per gate have been measured in a five-stage closed-loop invertor chain, and packing densities of 400 gates/mm/SUP 2/ have been achieved. A layout comparison with MOS logic is presented. A possible way of producing faster circuits is proposed.     

Compact voltage-mode multi-valued literal gate using nanoscale ballistic MOSFETs

A CMOS voltage-mode multi-valued literal gate is presented. The ballistic electron transport characteristic of nanoscale MOSFETs is smartly used to compactly achieve universal radix-4 literal operations. The proposed literal gates have small numbers of transistors and low power dissipations, which makes them promising for future nanoscale multi-valued circuits. The gates are simulated by HSPICE.     

Minority carrier injection characteristics of the diffused emitter junction

For the double-diffused transistor, a one-dimensional analysis is presented on the minority carrier injection properties of a diffused emitter junction. This junction is bounded on one side by a reverse biased collector and on the other by an ohmic contact of arbitrary recombination velocity. Furthermore, arbitrary magnitudes of minority carrier lifetime are assumed in both the emitter and base regions of this semiconductor device. Injection efficiency characteristics are graphically illustrated throughout a wide range of physical and geometrical parameters. Assuming, for example, variations in the emitter junction depth, injection properties are demonstrated for transistors exhibiting a fixed collector location and also for transistors exhibiting a fixed base width. A comparison is also shown between the calculated minority carrier injection from this analysis and from other, more approximate, methods.     

Scaling of Nanowire Transistors

This paper considers the scaling of nanowire transistors to 10-nm gate lengths and below. The 2-D scale length theory for a cylindrical surrounding-gate MOSFET is reviewed first, yielding a general guideline between the gate length and the nanowire size for acceptable short-channel effects. Quantum confinement of electrons in the nanowire is discussed next. It gives rise to a ground-state energy and, therefore, a threshold voltage dependent on the radius of the nanowire. The scaling limit of nanowire transistors hinges on how precise the nanowire size can be controlled. The performance limit of a nanowire transistor is then assessed by applying a ballistic current model. Key issues such as the density of states of the nanowire material are discussed. Comparisons are made between the model results and the published experimental data of nanowire devices.      

一种基于单电子晶体管的二阶低通滤波器

在研完单电子晶体管(SET)I-V特性的基础上，阐明了一种分区处理法，设计了一个SET积分器电路。并据此实现了一个SET二阶低通滤波器，说明了该滤波器的工作条件、结构、性能、参数和特点。仿真结果表明，该滤波器的传输特性与采用其它两种方法描述SET I-V特性所构成的滤波器的传输特性有良好的一致性。文中所提出的SET I-V特性分区处理法，同样适用于SET在其它功能电路中的应用。