A 14-bit 125 MS/s IF/RF Sampling Pipelined ADC With 100 dB SFDR and 50 fs Jitter

This paper describes a 14-bit, 125 MS/s IF/RF sampling pipelined A/D converter (ADC) that is implemented in a 0.35$muhbox m$BiCMOS process. The ADC has a sample-and-hold circuit that is integrated in the first pipeline stage, which removes the need for a dedicated sample-and-hold amplifier (i.e., “SHA-less”). It also has a sampling buffer that is turned off during the hold clock phases to save power. To accurately estimate and minimize the clock jitter, a new jitter simulation technique was used whose results were verified on silicon. The measured silicon results indicate the highest published IF sampling performance to date and prove the viability of the “SHA-less” architecture for IF/RF sampling ADCs. The ADC is calibration-free and achieves a DNL of less than 0.2 LSB and INL of 0.8 LSB. The SNR is 75 dB below Nyquist, and stays above 71 dB up to 500 MHz. The low-frequency SFDR is about 100 dB, and stays above 90 dB up to about 300 MHz. This is also the first ADC to achieve 14-bit level performance for input signal frequencies up to 500 MHz and to have a total RMS jitter of only 50 fs.     

Sampling Jitter Effect on a Reconfigurable Digital IF Transceiver to WiMAX and HSDPA

This paper outlines the time jitter effect of a sampling clock on a software‐defined radio technology‐based digital intermediate frequency (IF) transceiver for a mobile communication base station. The implemented digital IF transceiver is reconfigurable to high‐speed data packet access (HSDPA) and three bandwidth profiles: 1.75 MHz, 3.5 MHz, and 7 MHz, each incorporating the IEEE 802.16d worldwide interoperability for microwave access (WiMAX) standard. This paper examines the relationship between the signal‐to‐noise ratio (SNR) characteristics of a digital IF transceiver with an under‐sampling scheme and the sampling jitter effect on a multichannel orthogonal frequency‐division multiplexing (OFDM) signal. The simulation and experimental results show that the SNR of the OFDM system with narrower band profiles is more susceptible to sampling clock jitter than systems with relatively wider band profiles. Further, for systems with a comparable bandwidth, HSDPA outperforms WiMAX, for example, a 5 dB error vector magnitude improvement at 15 picoseconds time jitter for a bandwidth of WiMAX 3.5 MHz profile.     

孔径抖动对中频采样系统信噪比影响的研究

孔径抖动对中频(或射频)带通采样系统信噪比的影响非常严重.理论上,尽管相同带宽的中频信号和基带信号可以用相同的频率进行采样,但中频采样受孔径抖动等因素的影响更大,其采样技术要求也更高.如果在中频采样系统中解决不好孔径抖动问题,很可能根本采集不到正确的信号.本文通过分析孔径抖动产生的原因,孔径抖动与ADC (模数转换器)的信噪比以及与被采样信号上限频率之间的关系,找出了由孔径抖动决定的被采样信号的上限频率与ADC模拟带宽之间存在差距的原因,并发现了过采样率与处理增益及孔径抖动之间的关系.最后,介绍了几项减小孔径抖动的具体措施.     

A 16-bit 65-MS/s 3.3-V pipeline ADC core in SiGe BiCMOS with 78-dB SNR and 180-fs jitter

The analog-to-digital converter presented in this work demonstrates the efficiency of the straight 2.5 bit-per-stage approach for the implementation of pipelined switched-capacitor architectures targeting up to 16-bit resolution and 65-MS/s sampling rate. The test chip has been fabricated in a 45-GHz f/sub T/, 0.4-/spl mu/m 3.3-V SiGe BiCMOS process that makes it suitable for integration with an RF front-end toward an antenna-to-DSP communication processor. Performance of 78.3 dBFS SNR, 88dBc SFDR at 65 MS/s, 1 MHz input is obtained without trimming or calibration, dissipating 970 mW total with external references. Since the 4 V/sub p-p/ signal range chosen for high SNR could lead to distortion in the Sample/Hold and the pipelined quantizer with only 3.3-V supply, a fast and accurate SPICE simulation technique for INL investigation is described that enabled detailed diagnosis of potential nonlinearity sources. Theoretical analysis and practical implementation of the clock circuit are also discussed allowing the design of a CMOS-based clock featuring 180-fs jitter, which preserves high SNR against input frequency: state-of-the-art 73.5dBFS have been observed at 150 MHz input, popular intermediate frequency (IF) for single-heterodyne BTS receivers. Finally, the figures of merit encompassing power, effective resolution, and speed rank the dynamic performance of the ADC core among the best in its class.     

Characterization of the jitter in a mode-locked Er-fiber laser and its application in photonic sampling for analog-to-digital conversion at 10 gsample/s

This paper compares two approaches for evaluating the amplitude and timing jitters of an Er-fiber laser mode-locked at 10 GHz. Using a low-noise oscillator as the clock drive for the mode-locking, relative amplitude jitter was measured as low as 0.0384% and timing jitter as low as 0.0153% (/spl Delta/f=100 Hz-40 MHz). Applying the mode-locked pulse train in a photonic sampling experiment at 10 Gsample/s, a spurious free dynamic range (SFDR) of /spl sim/48.5 dB (over the Nyquist bandwidth of 5 GHz) for multiple analog inputs at L band (1-2.6 GHz). These results correspond to an analog-to-digital conversion resolution of /spl sim/8 SFDR bits at 10 Gsample/s. Finally, the use of "instantaneous companding" is demonstrated to correct for third-order distortions generated by a Mach-Zehnder modulator used in the photonic sampling link.     

射频直接采样系统中等效相位噪声模型分析

为了分析射频直接采样系统中的等效相位噪声模型,文中给出了射频直接采样接收机的简化构架,然后理论推导了射频直接采样接收机采样输出信噪比与采样时钟之间的关系表达式。最后,通过建立仿真实验平台对推导结论进行了实验验证,结果表明:射频直接采样系统对采样时钟的频谱纯度要求高,采样输出的信噪比和无杂散动态范围会在时钟信号频谱的基础上恶化。射频直接采样系统可视为射频本振混频和量化采样的过程,其等效相位噪声模型与常规超外差式接收机是一致的。     

A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR

An ultra-low-voltage CMOS two-stage algorithm ADC featuring high SFDR and efficient background calibration is presented. The adopted low-voltage circuit technique achieves high-accuracy high-speed clocking without the use of clock boosting or bootstrapping. A resistor-based input sampling branch demonstrates high linearity and inherent low-voltage operation. The proposed background calibration accounts for capacitor mismatches and finite opamp gain error in the MDAC stages via a novel digital correlation scheme involving a two-channel ADC architecture. The prototype ADC, fabricated in a 0.18 /spl mu/m CMOS process, achieves 77-dB SFDR at 0.9 V and 5MSPS (30 MHz clocking) after calibration. The measured SNR, SNDR, DNL, and INL at 80 kHz input are 50 dB, 50 dB, 0.6 LSB, and 1.4 LSB, respectively. The total power consumption is 12 mW, and the active die area is 1.4 mm/sup 2/.     

基于MATLAB的新型Pipeline ADC的建模和仿真

在MATLAB/Simulink的平台上,设计并实现了一种新的10 bit Pipeline ADC的系统仿真模型.针对2 bit,共9级的结构的精度不足以及4 bit首级结构的功耗较大的特点,提出了一种首级3 bit,共8级的结构.这种结构可以实现精度和功耗的平衡.经过系统仿真,在输入信号为10 MHz,采样时钟频率为40 MHz时,系统最大的SNR=60.36 dB,SFDR=82.177dB.创建的系统模型可为ADC系统中的误差和静态特性研究提供借鉴.     

一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。     

Effect of jitter on asynchronous sampling with finite number of samples

In modern communication systems, the conversion of analog signals into digital form [analog-digital conversion (ADC)] is one of the most critical functions. A fundamental limit of the signal-to-noise ratio (SNR) achievable in this conversion is given by the jitter of the sampling clock. The requirements on the maximum jitter tolerable are typically specified using SNR expressions which hold in the case of an infinite number of samples. However, there are good reasons to investigate the resulting SNR when only a finite number of samples is taken into account. This paper evaluates the effective impact of jitter on the SNR of the ADC process when the observation interval is limited to a finite number of samples. It will be shown that, in this case, the jitter constraints on the sampling clock can be more relaxed.     

80-MHz bandpass /spl Delta//spl Sigma/ modulators for multimode digital IF receivers

Three fully differential bandpass (BP) /spl Delta//spl Sigma/ modulators are presented. Two double-delay resonators are implemented using only one operational amplifier. The prototype circuits operate at a sampling frequency of 80 MHz. The BP /spl Delta//spl Sigma/ modulators can be used in an intermediate-frequency (IF) receiver to combine frequency downconversion with analog-to-digital conversion by directly sampling an input signal from an IF of 60 MHz to a digital IF of 20 MHz. The measured peak signal-to-noise-plus-distortion ratios are 78 dB for 270 kHz (GSM), 75 dB for 1.25 MHz (IS-95), 69 dB for 1.762 MHz (DECT), and 48 dB for 3.84 MHz (WCDMA/CDMA2000) bandwidths. The circuits are implemented with a 0.35-/spl mu/m CMOS technology and consume 24-38 mW from a 3.0-V supply, depending on the architecture.     

High performance 14-bit pipelined redundant signed digit ADC

A novel architecture of a pipelined redundant-signed-digit analog to digital converter(RSD-ADC) is presented featuring a high signal to noise ratio(SNR), spurious free dynamic range(SFDR) and signal to noise plus distortion(SNDR) with efficient background correction logic. The proposed ADC architecture shows high accuracy with a high speed circuit and efficient utilization of the hardware. This paper demonstrates the functionality of the digital correction logic of 14-bit pipelined ADC at each 1.5 bit/stage. This prototype of ADC architecture accounts for capacitor mismatch, comparator offset and finite Op-Amp gain error in the MDAC(residue amplification circuit) stages. With the proposed architecture of ADC, SNDR obtained is 85.89 dB, SNR is 85.9 dB and SFDR obtained is 102.8 dB at the sample rate of 100 MHz. This novel architecture of digital correction logic is transparent to the overall system, which is demonstrated by using 14-bit pipelined ADC. After a latency of 14 clocks, digital output will be available at every clock pulse. To describe the circuit behavior of the ADC, VHDL and MATLAB programs are used. The proposed architecture is also capable of reducing the digital hardware. Silicon area is also the complexity of the design.     

80 MHz bandpass delta-sigma modulator using switched-capacitorresonator structure

A fully differential 80 MHz fourth-order bandpass ΔΣ modulator, meant for a 100 MHz GSM/WCDMA multimode IF receiver, is presented. The modulator is based on a double-delay single opamp SC-resonator structure which is well suited for low supply voltages. Furthermore, the centre frequency of the topology is insensitive to different component variances. The measured peak SNR is 78 dB and 43.3 dB for 270 kHz (GSM) and 3.84 MHz (WCDMA) bandwidths, respectively     

低压工作的高速10bit Pipelined ADC

本文提出了一种低压工作的高速1Obit Pipelined ADC。采用自举时钟采样和Cascode频率补偿等方法,该ADC可以在低电压下工作,并达到较高的带宽。该ADC在HJTC 0.18-μm CMOS数模混合工艺下进行了设计仿真和流片测试,结果表明：当供电电压为1．8V,采样频率为62．5MSample／s时,所设计的ADC对于1MHz的输入信号转换有效位数可以达到52．2dB SFDR、44．8dB SNR和44．3dB SNDR。     

Radio frequency digital-to-analog converter

Dynamic performance of high-speed high-resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization, and clock jitter are all culprits. A DAC output controlled by an oscillating waveform is proposed to mitigate the effects of switching distortion and clock jitter. This architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency, allowing a high-frequency image of the input to be used as the output. This has the potential for better noise performance and power and hardware savings relative to a conventional DAC+mixer architecture. A narrow-band sigma-delta (/spl Sigma//spl Delta/) DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept in a 1.8-V 0.18-/spl mu/m CMOS technology. Measured single-tone SFDR is -75 dBc, SNR is 53 dB, and two-tone IMD3 is -70.8 dBc for a 17.5-MHz band centered at 942 MHz. SNR performance is shown to have the predicted dependence on the phase alignment of the data clock and oscillating pulse.     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

ADC对接收机测量性能的影响

作为模拟信号通向数字信号的桥梁,ADC是数字接收机发展的关键和瓶颈所在。为了研究ADC的采样时钟抖动及量化位数对接收机测量性能的影响程度。采用了理论分析并数学建模的方法,通过Matlab仿真实验,得到了ADC的采样时钟抖动及量化对接收机性能的影响程度,得出结论：相较于量化（N≥4）,采样时钟抖动对接收机的测量性能影响更大。相比于之前独立分析ADC采样时钟抖动及量化对接收机的影响,使用Matlab Guide将两者联合仿真。     

一种用于数字PFC的嵌入式SARADC

设计了一个用于数字PFC(功率因数校正)的12位精度的逐次逼近(SAR)A/D转换器.对DAC模块中出现的电容寄生问题进行了详细分析,针对性提出了一种1-6-5式的新型电容分段结构,并采用伪差分结构消除电荷注入和时钟馈通引入的一阶效应,使ADC性能有很大提高.上述设计在0.35μm CMOS工艺下完成,目前该芯片正在流片中.仿真结果表明,在采样频率为0.98MSPS,输入信号为50kHz时,新型分段结构ADC的信噪比SNR与无杂散动态范围SFDR较六六分段约有6%的提高.     

机场天气雷达双通道数字中频处理系统的实现

机场天气雷达要求能够从复杂的天气环境中识别不同的天气状况以保障航空飞行安全,其接收机大动态以及抗噪性能设计对雷达至关重要。在分析模数转换器（ADC）对雷达中频接收机动态范围制约的基础上,根据中频带通采样和数字下变频的原理,实现了基于现场可编程门阵列的双通道ADC采样数字中频处理系统,并给出了系统的设计原理、方法以及测试结果。通过对双通道ADC采样的数字中频处理系统的实现,能够很好地提高天气雷达接收机的动态范围,并应用于机场多普勒天气雷达数字中频接收机。     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.