Short-channel GaAs FET fabricated like a MESFET but operating like a JFET

Normally-on GaAs field-effect transistors (FETs) having 1 ?m gate lengths and 4 ?m channel lengths were fabricated in structures grown by molecular beam epitaxy (MBE). The unique part of this device is the very thin p+/n+ structure used to replace the conventional Schottky barriers. The device fabrication procedure is identical to that of a Schottky barrier FET (MESFET), but the devices exhibit characteristics similar to that of a junction field-effect transistor (JFET). This new device, the `camel diode gate FET?, is expected to have applications in both logic and power devices.     

The Comparative Performance of FET and Bipolar Transistors at VHF

The relative performance of FET and bipolar transistors 200 MHz AGC amplifiers in a TV tuner is discussed. It is concluded that both junction and insulated gate FET's have better overload capability than the bipolar transistor though they have a lower stable gain. The noise figure of the IG FET increases less rapidly with AGC than does the noise figure of the bipolar transistor. The performance of all three semiconductor devices is compared with that of a popular vacuum tube (6DS4) in its tuner.     

Reduction of optical shot noise from light emitting diodes

The mechanism responsible for the reduction of optical shot noise from high impedance driven light-emitting diodes is addressed. It is shown that the electronic feedback mechanism is the same as that for laser diodes with spontaneous recombination. Quantum noise reduction below the optical shot noise level is due to the effect of negative feedback on the recombination rate that occurs when the junction voltage and carrier number are permitted to respond to the underlying (Poisson) stochastic recombination process as in a light-emitting diode or laser diode driven by a high impedance source. Extensive measurements on light-emitting diodes confirm the magnitude of the noise suppression predicted from semiclassical theory     

Investigation of the Device Degradation Mechanism in Pentacene-Based Thin-Film Transistors Using Low-Frequency-Noise Spectroscopy

The degradation process in pentacene-based organic thin-film transistors (OTFTs) is investigated. Pentacene-based OTFTs were fabricated with and without octadecyl trichlorosilane (OTS) treatment, and their device characteristics during lifetime test are evaluated using low-frequency-noise (LFN) spectroscopy. It is found that the devices exhibited the $hbox{1}/f$ type of noise behavior with generation and recombination noise superimposed. The drain-current noise was found to vary proportionally with drain current according to Hooge's empirical relation of flicker noise. Devices without any treatment show obvious interface traps and deep-level traps, while devices with OTS treatment show nonexistence of interface traps and suppression of deep-level traps. The LFN intensity is found to decrease during the device lifetime test initially, while upon the device failure, the noise level is observed to increase again. The viability of using LFN as a diagnostic tool in the organic transistor is demonstrated.      

Noise effects in bipolar junction transistors at cryogenic temperatures: Part II

In Part II of this investigation, a characterization of the output noise current generator i0of modern planar bipolar junction transistors (BJT's) for common-base configuration with the input ac open circuited is developed and verified at temperatures ranging from 60 to 300 K. It is shown that at low temperatures, for those devices where recombination processes in the emitter-base space-charge region become very pronounced, the resulting noise for these processes shows less than full shot noise. This noise reduction can show up at temperatures slightly below room temperature for such devices. (Generation-recombination effects described in Part I may still become important at temperatures below 110 K.) Also, it is demonstrated that an important parameter to monitor in taking these measurements, at least at low temperatures, is the alpha cutoff frequency fα if the low-frequency theory is to be realized.     

Low-frequency noise measurements on submicrometre n-channel and p-channel MOSFETs at various operating regions

Silicon founders give in their MOS transistor card models some low-frequency noise parameters for SPICE-based circuit simulators corresponding to pure 1/f ^a or flicker noise, with a very close to unity. MOS transistors used in analogue circuit applications are usually devices with large channel length and width. In low-noise applications, methods such as correlated double sampling are used to suppress the low frequency noise generated by them. Nevertheless, the transistors presently are submicrometre devices exhibiting very different low-frequency noise behaviour. In this paper, experimental low-frequency noise results obtained at room temperature on NMOS and PMOS transistors fabricated using a 0.7 μm process are presented. Both large and small devices on the same process are considered. All regions of operation of transistors are considered. We show that the low-frequency noise behaviour of small area MOSFETs is very different from that of large area devices and that the spectrum is the summation of Lorentzian spectra generated by the switching of individual active traps.     

Distribution of recombination current in emitter-base junctions of silicon transistors

Sah, Noyce and Shockley have attributed the decrease in the current gain of silicon transistors to recombination in the space-charge region of the emitter-base junction. It is suggested that for oxide-masked diffused structures the space-charge recombination current is concentrated at the junction periphery at or just under the surface. An analysis is presented which shows that measurement of the base current of transistor structures with two base contacts, as a function of voltage applied between the two base contacts, may be used to distinguish between recombination current which is concentrated at or near the surface periphery of the junction space-charge region, and recombination current distributed over the area of the junction. For the diffused structures examined, it is shown experimentally that the recombination takes place mainly at or near the junction surface periphery.     

Advanced CAD tool for noise modeling of RF/microwave field effect transistors with large gate widths

In the millimeter-wave frequency range, electromagnetic (EM) effects can significantly influence a device behavior. As the core of modern communication systems, active devices such as field effect transistors (FETs) require up-to-date models to accurately integrate such effects, especially in terms of noise performance since most of communication systems operate in noisy environments. Furthermore, to keep low-noise amplification over a wide frequency band, the transistor noise resistance R_n must be substantially reduced to make the system insensitive to impedance matching. Since this can be realized through large gate-width devices, a novel large gate-width FET noise model is proposed which efficiently integrates EM wave propagation effects, one of the most important EM effects in mm-wave frequencies.     

Flicker (1/f) noise generated by a random walk of electrons in interfaces

Flicker noise can be generated by a random walk of mobile electrons in interfaces via interface states. It is proposed that these electrons interact with surface phonons to form polarons, which have very low mobilities. The flicker-noise model is a general one and may be used to explain flicker noise on MOSFET's, clean Si surfaces, metallic resistors, grain boundaries, amorphous layers, electron tubes, metal-insulator-metal junctions, diodes, and transistors. The dependence of the noise intensity is calculated as a function of device parameters such as interface state density, source-drain current, source-drain voltage, gate voltage, oxide layer thickness, grain size, temperature, size of the cathode, diode current, base current, and the surface recombination in the emitter-base area. Hooge's parameter is calculated quantitatively for several devices.     

Noise in high-gain transistors and its application to the measurement of certain transistor parameters

Noise performance of a high-gain transistor is presented. It is shown that both burst noise and flicker noise in high-gain transistors are not as important as those in low-gain units. At very small biases, less than 10 µA for the given transistor, the limiting noise of the transistor is dominated by the shot noise. In the higher bias region the thermal noise of the base resistance is the dominant noise of the transistor. It is also demonstrated that from noise measurement the base resistance rb'b, the transconductance gm, and the small signal common emitter-current gain β can be accurately determined.     

Noise in phototransistor optical isolators

Noise measurements were performed on several commercially available phototransistor optical isolators in order to examine the signal detection limits of typical devices. It was found that, in general, phototransistor optical isolators are very noisy devices exhibiting all of the common types of noise usually found in bipolar junction transistors. A large number of devices exhibited burst noise which dominated their low-frequency noise performance. The noise performance of devices without burst noise was dominated by 1/f noise or flicker noise at low frequencies and by shot noise at high frequencies. Experimental data indicates that in most cases the electrical noise contribution of the LED is negligible and that the dominant source of noise is the phototransistor.     

Carrier trapping and recombination in avalanche diodes

The differential equations describing an avalanching p⁺nn⁺junction in the presence of multiple-level carrier traps have been solved numerically for trap densities as high as two orders of magnitude greater than the n-region background doping. The results compare quantitatively with a number of past, as well as new, experimentally observed changes in avalanche microwave diode performance with neutron damage. In particular, trapped charge in the space-charge region tends to localize the avalanche region near the p⁺n junction, which raises the frequencies of operation. Carrier trapping at the edges of the space-charge region explains the increase in operating voltage and decrease in small-signal capacitance. The localization of the avalanche region, through carrier trapping in the space-charge region, and recombination effects at high avalanche current densities combine to cause eventual RF failure of IMPATT and TRAPATT diodes with neutron damage.     

Double channel field effect transistors (DCT) and demonstration of static single transistor bit cell

A double channel structure was implemented in standard field effect transistors (FET) by implants. The resulting transfer slopes of these modified FETs show a clear on and off-state as well as a local extreme in between, if the body is forced. Exploring the new functionality of these novel devices a static single transistor bit cell is built for demonstration, pin compatible to standard bit cells.     

The Complete Semiconductor Transistor and Its Incomplete Forms

This paper describes the definition of the complete transistor. For semiconductor devices, the complete transistor is always bipolar, namely, its electrical characteristics contain both electron and hole currents controlled by their spatial charge distributions. Partially complete or incomplete transistors, via coined names or/and designed physical geometries, included the 1949 Shockley p/n junction transistor (later called Bipolar Junction Transistor,BJT), the 1952 Shockley unipolar 'field-effect' transistor (FET, later called the p/n Junction Gate FET or JGFET), as well as the field-effect transistors introduced by later investigators. Similarities between the surface-channel MOS-gate FET (MOSFET) and the volume-channel BJT are illustrated. The bipolar currents, identified by us in a recent nanometer FET with 2-MOS-gates on thin and nearly pure silicon base, led us to the recognition of the physical makeup and electrical current and charge compositions of a complete transistor and its extension to other three or more terminal signal processing devices, and also the importance of the terminal contacts.     

Effects of ionizing radiation on oxidized silicon surfaces and planar devices

This paper examines in detail the effects of high and low energy electron, X-ray, and ultraviolet radiation on oxidized silicon surfaces and planar devices. Two permanent effects of ionizing radiation on oxidized silicon surfaces are distinguished: 1) The buildup of a positive space charge within the oxide, and 2) The creation of fast surface states at the oxide-silicon interface resulting in increased surface recombination velocity. The dependence of these effects on dose and dose rate, on bias applied during irradiation, and on structural parameters is discussed and a theory is presented which accounts for the observed features of the space-charge buildup. This theory involves trapping of holes which are generated within the oxide by the radiation. It is shown that all details of the experimental observations can be accounted for by assuming a high density of hole traps near the oxide-silicon interface which decays rapidly with distance into the oxide. Radiation-induced changes in the characteristics of MOS and junction field-effect transistors, p-n junction diodes, and p-n-p and n-p-n transistors are reported and examined in terms of the above two effects. It is shown that the charge buildup causes shifts in the operating point of MOS transistors, catastrophic increases in the reverse current of p-n junctions, and variations in their breakdown voltage. The increase in fast surface-state density is responsible for the lowering of the transconductance of MOS transistors and, in combination with the space-charge buildup, for the degradation of the current gain in bipolar transistors. It is shown that junction field-effect transistors are relatively insensitive to both effects of ionizing radiation and therefore offer the most promise for use in ionizing radiation environments.     

Ge-ZnSSe Spatial Wavefunction Switched (SWS) FETs to Implement Multibit SRAMs and Novel Quaternary Logic

This paper describes novel multibit static random-access memories (SRAMs) implemented using four-channel spatial wavefunction switched field-effect transistors (SWS FETs) with Ge quantum wells and ZnSSe barriers. A two-bit SRAM cell consists of two back-to-back connected four-channel SWS FETs, where each SWS FET serves as a quaternary inverter. This architecture results in a reduction of the field-effect transistor (FET) count by 75% and data interconnect density by 50%. The designed two-bit SRAM cell is simulated using Berkeley short-channel insulated-gate field-effect transistor equivalent-channel models (for 25-nm FETs). In addition, the binary interface logic and conversion circuitry are designed to integrate the SWS SRAM technology. Our motivation is to stack up multiple bits on a single SRAM cell without multiplying the transistor count. The concept of spatial wavefunction switching (SWS) in the FET structure has been verified experimentally for two- and four-well structures. Quantum simulations exhibiting SWS in four-well Ge SWS FET structures, using the ZnSe/ZnS/ZnMgS/ZnSe gate insulator, are presented. These structures offer higher contrast than Si-SiGe SWS FETs.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

1/f noise as a reliability indicator for subsurface Zener diodes

It is shown from accelerated life tests and noise measurements that the degradation in reference voltage for subsurface Zener diodes is strongly correlated with 1/f noise in the devices. The larger the initial 1/f noise of a diode is, the earlier its degradation occurs. Compared with dc parameters, 1/f noise is more sensitive to the slight change in the structure of the devices subjected to operation or test stresses. In the mechanism analysis, the degradation and the 1/f noise are attributed to similar physical origin, and both are related to dislocations in the space-charge region of p–n junction. Based on the results, a 1/f noise screening approach is proposed for the high reliability application of the devices.     

Profiling interface traps in MOS transistors by the DCcurrent-voltage method

Position profiling the interface trap density along the channel length of metal-oxide-silicon transistors by the Direct-Current Current-Voltage method is illustrated for five density variations: zero, peaked in drain junction space-charge layer, constant in channel, nonconstant in channel, and peaked in drain junction space-charge layer and nonconstant in channel. The interface trap densities were monitored by MOS transistor's d.c. body current and the density profiles were obtained from the body-drain and body-source differential conductance versus drain or source bias voltage. An experimental demonstration is given for a 1.6 μm n-channel Si MOS transistor with about 10¹¹ traps/cm² generated by channel hot electron stress