Deep-Implant 1-/spl mu/m MOSFET Structure with Improved Threshold Control for VLSI Circuitry

MOSFET structures with an optimized doping profile show improved threshold control and subthreshold performance. This is achieved by a low-dose shallow implant defining the level of the threshold and a higher dose deep implant improving short-channel effects like SDIBL and VDIBL. Besides surface and volume barrier lowering, body effect, parasitic capacitance, avalanche multiplication, and breakdown voltage have been investigated. In spite of the increased substrate sensitivity and junction capacitances, the deep-implant concept only provides transistors with reasonable terminal characteristics in the 1-/sub mu/m and sub-micrometer range.     

抑制亚微米NMOS穿通效应的Taurus WorkBench--TCAD优化

Taurus WorkBench是用于超深亚微米层次下的TCAD一体化仿真优化平台.在介绍了TWB的主要功能及实施要点之后,以亚微米NMOSFET器件的阈值电压及源漏穿通电压为响应变量,采用DOE方法进行仿真,并以仿真结果阐述了注入剂量及注入能量对阈值电压`和源漏穿通电压Vbrk的影响.     

Reduction of threshold voltage sensitivity in SOI MOSFET's

The threshold voltage sensitivity, of fully depleted SOI MOSFET's to variations in SOI silicon film thickness was examined through both simulation and device experiments. The concept of designing the channel V_th implant to achieve a constant dose within the film, rather than a constant doping concentration, was studied for a given range of film thicknesses. Minimizing the variation in retained dose reduced the threshold voltage sensitivity to film thickness for the range of t_si examined. One-dimensional process simulations were performed to determine the optimal channel implant condition that would reduce the variation in retained dose using realistic process parameters for both NMOS and PMOS device processes. SOI NMOS transistors were fabricated. The experimental results confirmed the simulation findings and achieved a reduced threshold voltage sensitivity     

The effect of dose rate and implant temperature on transient enhanced diffusion in boron implanted silicon

The effect of ion implantation dose rate and implant temperature on the transient enhanced diffusion (TED) of low energy boron implants into silicon was investigated. The implant temperature was varied between 5 and 40°C. The beam current was varied from 0.035 to 0.35 mA/cm². Three different defect regimes were investigated. The first regime was below the formation of any extended defects (5 keV B⁺ 2 × 10¹⁴/cm²) visible in the transmission electron microscope. The second regime was above the {311} formation threshold (2×10¹⁴/cm²) but below the subthreshold (type I) dislocation loop formation threshold. The final regime was above both the {311} and dislocation loop formation threshold (10 keV 5×10¹⁴/cm²). TED for these conditions is shown to be over after annealing at 750°C for 15–30 min. Secondary ion mass spectroscopy results for the three different damage regimes indicate that there is no measurable effect of dose rate or implant temperature on TED of boron implanted silicon for any of the damage regimes. It should be emphasized that the dose and energy of the boron implants is such that none of these implants approached the amorphization threshold. Above amorphization dose rate and implant temperature have dramatic effects on TED, but it appears that below the amorphization threshold there is little effect. These results suggest that for a given energy it is the ion dose not the extent of the implant damage that determines the extent of TED in boron implanted silicon.     

A low-power high-speed ion-implanted JFET for InP-based monolithic optoelectronic IC's

We describe a high-performance fully ion-implanted planar InP junction FET fabricated by a shallow (4000-Å) n-channel implant, an n⁺source-drain implant to reduce FET series resistance, and a p-gate implant to form a shallow (2000-Å) abrupt p-n junction, followed by a rapid thermal activation. From FET's with gates 2 µm long, a transconductance of 50 mS/mm and an output impedance of 400 Ω.mm are measured at zero gate bias with a gate capacitance of 1.2 pF/mm. The FET has a threshold voltage of -2.4 V, and a saturated drain current of 60 mA/mm at Vgs= 0 V with negligible drift.     

Simultaneous growth of different thickness gate oxides in siliconCMOS processing

A method is proposed that allows the growth of gate oxides of different thicknesses on a single wafer. The method does not require masking the gate oxide during oxidation with its inherent risk to the oxide quality, but rather relies on the implant of nitrogen into the silicon wafer before both oxide growth and preoxidation cleans. This implant is performed at the same step as the normal threshold voltage implants, avoiding possible contamination. Using nitrogen implant doses of the order of 3×10¹⁴-3×10¹⁵ cm^-2, it is shown that it is possible to grow oxides of 30-70 Å, for a process with a nominal oxide thickness of 90 Å     

Proton implanted singlemode holey vertical-cavity surface-emitting lasers

Wedge-shaped holes have been fabricated in the top mirror of proton implant confined vertical-cavity surface-emitting lasers. The index confinement and selective loss introduced by these patterns improved the performance by both increasing the singlemode power and reducing the threshold current of the lasers. A maximum single fundamental mode power of 3.5 mW with a simultaneous reduction of lasing threshold compared to an unmodified laser was observed. Multimode operation was suppressed over the entire laser operating range.     

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

The impact of halo implantation angle on the low-frequency noise of short channel n-MOSFET is reported. The low-frequency noise is degraded with larger tilt angle for the same implant dose and energy. The higher dose/energy of the halo implant with larger tilt angle further enhances the degradation of low-frequency noise. The larger halo angle introduces non-uniform doping distribution and creates the non-uniform threshold voltage along the channel. Additional traps can be created near the oxide/semiconductor interface due to boron pileup due to larger tilt angle. A quantitative analysis supported by experimental results confirm that the degradation of 1/f noise is due to the combined effect of non-uniformity in threshold voltage along the channel and the creation of extra trap charges near the oxide-semiconductor interface (near-interfacial charges).     

边缘注入对H型栅SOI pMOSFETs亚阈值泄漏电流的影响

就不同边缘注入剂量对H型栅SOI pMOSFETs亚阈值泄漏电流的影响进行了研究。实验结果表明不足的边缘注入将会产生边缘背栅寄生晶体管,并且在高的背栅压下会产生明显的泄漏电流。分析表明尽管H型栅结构的器件在源和漏之间没有直接的边缘泄漏通路,但是在有源扩展区部分,由于LOCOS技术引起的硅膜减薄和剂量损失仍就促使了边缘背栅阈值电压的降低。     

Performance, uniformity, and yield of 850-nm VCSELs deposited by MOVPE

Vertical-cavity surface-emitting lasers (VCSELs) emitting near 850 nm and fabricated with the metal-organic vapor phase epitaxy (MOVPE) epitaxial growth technique and a planar proton implant process have been demonstrated with excellent performance, uniformity, and yield across a 3-in wafer. Four thousand lasers were tested on a three-inch-diameter wafer, with a yield of 99.8%. This translates into a yield of 94% for fully functional 34/spl times/1 arrays. The average threshold current, threshold voltage, and dynamic resistance at 10 mA operating current were 3.07 mA, 1.59 V, and 34 ohms, respectively. Uniformity of better than /spl plusmn/9% in threshold current, /spl plusmn/1% in threshold voltage, and /spl plusmn/1.5% in maximum optical output power across a 34-element array was demonstrated.     

Ion-implanted threshold tailoring for insulated gate field-effect transistors

This paper develops a general threshold equation for long-channel insulated gate field-effect transistors which accounts for the effects of ion-implant profiles used in threshold tailoring. Although any integrable function used to describe the nonuniform doping will yield an analytical expression for threshold, a Gaussian function is chosen because it accurately describes the implanted profile following proper annealing, regardless of subsequent high-temperature steps during fabrication. Most profiles of interest are quasi-neutral, i.e., the spatial dependence of the majority carriers in the undepleted bulk is adequately described by the doping profile, but the threshold equation is shown to be an excellent approximation for non quasi-neutral profiles as well. Comparison with experimental results show the analytical expression to be in good agreement with data over a wide range of implant conditions and starting substrate resistivity.     

Preventing boron penetration through 25-Å gate oxides withnitrogen implant in the Si substrates

For gate oxides thinner than 40 Å, conventional schemes of incorporating N in the oxides might become insufficient in stopping B penetration. By implanting N into the Si substrates with a sacrificial oxide layer; we have grown 25 Å gate oxide and prevented B penetration in the presence of F after 90 min of 850°C and 10 s of 1050°C anneals. SIMS analyses surprisingly reveal a N peak formed within the thin oxide layer, while no N is left in the Si substrate beyond the oxide layer. In addition, no B is seen in the substrate, either. As a consequence, threshold voltage of pMOSFETs is shifted to a more negative value which agrees with calculations assuming no B penetration. Meanwhile, threshold voltage of nMOSFETs is not affected by the N implant, which confirms that B penetration is the only explanation for the pMOSFET data. Prevention of B penetration also improves the short-channel effects for 0.25-μm pMOSFETs, while no difference is seen in nMOSFETs with and without N implant     

Reduction of the parasitic charge generation during silicon nitride deposition in a LOCOS isolation without field implant

MOS integrated circuits use the Local oxidation of silicon to isolate laterally adjacent devices (LOCOS isolation). The insulation structure is typically formed by a semiconductor region doped by ion implantation (field implant) and covered by a thick thermal oxide (field oxide). Other insulators (plasma enhanced chemical vapor deposited (PECVD) silicon oxides and LPCVD silicon nitride) and metal interconnection are subsequently deposited on the field oxide. The ion implant together with the thick insulator ensure a high threshold voltage value of the parasitic MOS transistor formed by source and drain of the adjacent active devices and by the insulator/interconnection gate.However, economical purpose leads to the extension of the application field of lower cost technology, addressing the problem of LOCOS isolation without any field implant. As already shown in a previous work [Fay JL, Beluch J, Allirand L, Brosset D, Despax B, Bafleur M, Sarrabayrose G. Jpn J Appl Phys 38(9A):5012–7] for inter-layer dielectric applications, our PECVD oxides suffer from excessive concentration of fixed positive charges brought about by the silicon nitride deposition, and causing the N-channel field threshold voltage to decrease.Characterization reveals that these charges are generated by diffusion of species coming from the gas phase during the silicon nitride process. These generated charges can be reduced either by increasing the O₂/tetra-ethyl orthosilicate ratio or by doping the oxide with boron and phosphorus. To avoid diffusion and generation of charges, we minimized the thermal budget using a PECVD silicon nitride. With this process, we have achieved a high threshold voltage and an acceptably low leakage current of the NMOS parasitic transistor.     

Model for the channel-implanted enhancement-mode IGFET

A simple dc four-terminal "channel-implanted model" is developed for the enhancement-mode IGFET. The model accurately predicts the dependence of transistor threshold voltage and current gain on substrate bias. Modeled and measured threshold voltages are shown to agree to within 25 mV across a 15-V range of VSB. Modeled and measured transistor currents agree to within 5 percent across a 10-V range of VSBfor medium- to long-channel length transistors (L_{drawn} ge 2.5µm). The channel impurity profile is approximated as a constant effective impurity concentration NAEextending from the semiconductor surface through the implanted region to an effective implant depth XDE("box" profile approximation). At depths greater than XDE, the bulk substrate impurity concentration is approximated as a constant, NA. The model is composed of two threshold voltage equations, three drain current equations, two saturation voltage equations, and two boundary equations. All first-order model equations and all of their first derivatives are continuous at all boundaries. The model's continuity and its accuracy make it useful for circuit simulation. Extrapolation of channel concentration profile parameters NAE, XDE, and NAfrom measured threshold voltages yields information on implant profile and on field-implant impurity encroachment into the transistor channel.     

Effects of field implants on small geometry CMOS devices

The various aspects of field implants have been studied with reference to a 3 μm CMOS p-well process developed at the author's organisation. It has been found that p-field (adjacent to p-channel tranistors) implant is not required for a low voltage (1.5 V) process. Both p- and n-field implants are, however, essential for a high voltage (5 V) process. The threshold voltage for a narrow width n-channel transistor is found to be increased from 0.3 V to 2.5 V as compared to that of a large width transistor if the field implant is followed by a long high temperature step. The increase in threshold in the case of a narrow p-channel transistor is observed to be from 0.35 V to 1.65 V under the same conditions. Such a large increase in the threshold voltage can, however, be prevented by a proper design of the process. It has also been observed that arsenic is an unsuitable species for p-field implants.     

Effects of “fast” rapid thermal anneals on sub-keV boron and BF2 ion implants

The effects of “fast” ramp-rates (up to 425°C/s) and spike anneals are investigated for 0.25 keV, 0.5 keV, and 1.0 keV ¹¹B+ and for 1.1 and 2.2 keV BF₂ at a dose of 1e 15/cm². Below an implant energy threshold where no extended defects form, fast ramp-rates become important in minimizing the thermal diffusion component and reducing the junction depth. Above this implant energy threshold, TED minimizes the advantages of these fast ramp-rates. Annealing in a low and controlled O₂ ppm in N₂ ambient further reduces diffusion by minimizing/eliminating oxygen related enhanced diffusion effects, while simultaneously optimizing anneal reproducibility and across-the-wafer uniformity.     

Impact of the interaction between nitrogen implant and NO anneal on narrow-width transistors

This study reports a new behavior in narrow-width transistors resulting from the interaction of oxides grown with nitrogen implant with the nitridation associated with growing other oxides. Nitric oxide (NO) annealing of 28-/spl Aring/ oxides grown on nitrogen-implanted silicon results in the decrease of NMOS threshold voltage and in the increase (absolute value) of PMOS threshold with decreasing width. This effect arises from the positive charge from NO anneal interacting with the parasitic transistor associated with the shallow trench isolation edge recess. The parasitic impact becomes more pronounced for narrower widths due to higher effect of recess on total transistor width.     

Analysis of monophasic and biphasic electrical stimulation of nerve

In an earlier study, biphasic and monphasic electrical stimulation of the auditory nerve was performed in cats with a cochlear implant. Single-unit recordings demonstrated that spikes resulting from monophasic and biphasic stimuli have different thresholds and latencies. Monophasic thresholds are lower and latencies are shorter under cathodic stimulation. Results from stochastic simulations of a biophysical model of electrical stimulation are similar. A simple analysis of a linear, "integrate to threshold" membrane model accounts for the threshold and latency differences observed experimentally and computationally. Since biphasic stimuli are used extensively in functional electrical stimulation, this analysis greatly simplifies the biophysical interpretation of responses to clinically relevant stimuli by relating them to the responses obtained with monophasic stimuli.     

Threshold voltage shift of n-channel Si-gate MOSFET's

The relationship between the threshold voltage shift of the n-channel Si-gate MOSFET and the implant dose of boron ions has been examined theoretically and experimentally when these ions are implanted with an energy of 60 keV through a gate oxide of 1200 Å into a p-type silicon substrate of the acceptor concentration of 7 × 10¹⁴/cm³. The effect of high-temperature treatment after ion implantation on the threshold voltage shift has been considered. The good agreement between the theory and the experiment verifies that the model used is reasonable. The threshold voltage shift with the dose is expressed by about 5 × 10^-12V.cm²below a dose of 5 × 10¹¹ions/cm². Above this value, the increase of the threshold voltage shift becomes slow and the slope takes the value of about 2 × 10^-12V.cm²due to the maximum surface depletion layer.     

Improved CMOS field isolation using germanium/boron implantation

A novel germanium/boron implantation technique for improving the electrical field isolation of high-density CMOS circuits is demonstrated. Germanium implantation causes a reduction in dopant diffusion and segregation during field oxidation and is shown to increase the p-well field threshold voltage by as much as 40% with no significant degradation to junction or device performance. Selective germanium implantation with a blanket boron field implant can also improve the electrical field isolation behavior for CMOS circuits