High-density MIM capacitors (/spl sim/85 nF/cm/sup 2/) on organic substrates

For the first time, transferring the prefabricated capacitors on a silicon wafer onto FR-4 has been used to realize high-density metal-insulator-metal (MIM) capacitors on an organic substrate. A high capacitance density /spl sim/85 nF/cm/sup 2/ was achieved on FR-4 substrate with PECVD silicon nitride as the dielectric layer. Excellent voltage coefficient (/spl sim/2.2 ppm/V/sup 2/) and temperature coefficient (/spl sim/38 ppm//spl deg/C) were obtained for capacitors on FR-4. Dielectric leakage and breakdown characteristics have been assessed, and the results demonstrated acceptable performance. Thus, this technology provides a new method to embed/integrate high-density capacitors on organic substrates for the system-in-package applications.     

Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs

Control of on-chip power supply noise has become a major challenge for continuous scaling of CMOS technology. Conventional passive decoupling capacitors (decaps) exhibit significant area and leakage penalties. To improve the efficiency of power supply regulation, this paper proposes a distributed active decap circuit for use in digital integrated circuits (ICs). The proposed design uses an operational amplifier to boost the performance of conventional decaps. Simulations proved its enhanced decoupling effect in comparison with passive decaps. The proposed active decap also shows advantages in providing additional damping to the on-chip resonant noise. To verify the performance from the proposed circuit, a 0.18-$mu$ m test chip with on-chip noise generators and sensors has been fabricated. Measurements show a 4-11$times$ boost in decap value over conventional passive decaps for frequencies up to 1 GHz with a total area saving of 40%. Local supply noise distribution and decap gating capability were also examined from the test chip.      

MIM capacitors using atomic-layer-deposited high-/spl kappa/ (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ dielectrics

Metal-insulator-metal (MIM) capacitors with (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ high-/spl kappa/ dielectric films were investigated for the first time. The results show that both the capacitance density and voltage/temperature coefficients of capacitance (VCC/TCC) values decrease with increasing Al/sub 2/O/sub 3/ mole fraction. It was demonstrated that the (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitor with an Al/sub 2/O/sub 3/ mole fraction of 0.14 is optimized. It provides a high capacitance density (3.5 fF//spl mu/m/sup 2/) and low VCC values (/spl sim/140 ppm/V/sup 2/) at the same time. In addition, small frequency dependence, low loss tangent, and low leakage current are obtained. Also, no electrical degradation was observed for (HfO/sub 2/)/sub 1-x/(Al/sub 2/O/sub 3/)/sub x/ MIM capacitors after N/sub 2/ annealing at 400/spl deg/C. These results show that the (HfO/sub 2/)/sub 0.86/(Al/sub 2/O/sub 3/)/sub 0.14/ MIM capacitor is very suitable for capacitor applications within the thermal budget of the back end of line process.     

RF, DC, and reliability characteristics of ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for Si RF IC applications

High-performance metal-insulator-metal capacitors using atomic layer-deposited HfO/sub 2/-Al/sub 2/O/sub 3/ laminate are fabricated and characterized for RF and mixed-signal applications. The laminate capacitor can offer high capacitance density (12.8 fF//spl mu/m/sup 2/) up to 20 GHz, low leakage current of 4.9/spl times/10/sup -8/ A/cm/sup 2/ at 2 V and 125/spl deg/C, and small linear voltage coefficient of capacitance of 211 ppm/V at 1 MHz, which can easily satisfy RF capacitor requirements for year 2007 according to the International Technology Roadmap for Semiconductors. In addition, effects of constant voltage stress and temperature on leakage current and voltage linearity are comprehensively investigated, and dependences of quadratic voltage coefficient of capacitance (/spl alpha/) on frequency and thickness are also demonstrated. Meanwhile, the underlying mechanisms are also discussed.     

Optical and electrical properties of nanostructured metal-silicon-metal photodetectors

We report an experimental evaluation of the performance of silicon (Si) photodetectors incorporating one-dimensional (1-D) arrays of rectangular and triangular-shaped nanoscale structures within their active regions. A significant (/spl sim/2/spl times/) enhancement in photoresponse is achieved in these devices across the 400- to 900-nm spectral region due to the modification of optical absorption properties that results from structuring the Si surface on physical optics scales smaller than the wavelength, which both reduces the reflectivity and concentrates the optical field closer to the surface. Both patterned (triangular and rectangular lineshape) and planar Ni-Si back-to-back Schottky barrier metal-semiconductor-metal photodetectors on n-type (/spl sim/5/spl times/10/sup 14/ cm/sup -3/) bulk Si were studied. 1-D /spl sim/50-250-nm linewidth, /spl sim/1000-nm depth, grating structures were fabricated by a combination of interferometric lithography and dry etching. The nanoscale grating structures significantly modify the absorption, reflectance, and transmission characteristics of the semiconductor: air interface. These changes result in improved electrical response leading to increased external quantum efficiency (from /spl sim/44% for planar to /spl sim/81% for structured devices at /spl lambda/=700 nm). In addition, a faster time constant (/spl sim/1700 ps for planar to /spl sim/600 ps for structured at /spl lambda/=900 nm) is achieved by increasing the absorption near the surface where the carriers can be rapidly collected. Experimental quantum efficiency and photocurrents results are compared with a theoretical photocurrent model based on rigorous coupled-wave analysis of nanostructured gratings.     

Edge-coupled InGaAs PIN photodiode with a light funnel waveguide

We have successfully fabricated InGaAs edge-coupled photodiodes (EC-PDs) with a light funnel integrated (LIFI) in front of the coupling aperture, called LIFI EC-PD, based on the self-terminated oxide polish (STOP), the crystallographic slope etching of InP, and the self-aligned diffusion (SAD) techniques. The LIFI EC-PD presents not only a lower dark current density (/spl sim/ 4.4 mA/cm/sup 2/) but also a higher responsivity (/spl sim/ 0.4 A/W) than that of the mesa EC-PD (27 mA/cm/sup 2/ and 0.26 A/W, respectively). Furthermore, the thick oxide film serves as the funnel in front of active-region aperture to enhance the coupling efficiency and to lower the bonding pad capacitance down to 50 fF. The lowered bonding pad capacitance can be beneficial in designing a device with a higher transit-time-limited frequency response of beyond 30 GHz. The LIFI EC-PD with a 1-/spl mu/m thick absorption layer exhibits a 3-dB bandwidth of 20 GHz and a responsivity of /spl sim/ 0.4 A/W.     

Plasma-based lens for microwave beam steering

Lenses based on plasma could offer an alternative to electronic beam steering at high frequencies (/spl sim/100 GHz) and high powers. Presented are beam deflection measurements for a lens which exhibits wide angle deflections (25/spl deg/), good collimation and rapid beam steering (/spl sim/100 /spl mu/s). A practical prototype is described.     

Simulation of interconnect inductive impact in the presence of process variations in 90 nm and beyond

The on-chip inductive impact on signal integrity has been a problem for designs in deep-submicrometer technologies. The inductive impact increases the clock skew, max timing, and noise of bus signals. In this letter, circuit simulations using silicon-validated macromodels show that there is a significant inductive impact on the signal max timing (/spl sim/ 10% pushout versus RC delay) and noise (/spl sim/2/spl times/RC noise). In nanometer technologies, process variations have become a concern. Results show that device and interconnect process variations add /spl sim/ 3% to the RLC max-timing impact. However, their impact on the RLC signal noise is not appreciable. Finally, inductive impact in 65- and 45-nm technologies is investigated, which indicates that the inductance impact will not diminish as technology scales.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

A 310/spl deg//3.6-dB K-band phaseshifter using paraelectric BST thin films

Ferro- and para-electric BaSrTiO/sub 3/ (/spl epsiv//sub r//spl sim/350 and tg/spl delta//spl sim/5/spl times/10/sup -2/ at 0V) thin films were deposited by low-cost sol-gel techniques. Subsequently, the films were used for fabricating coplanar waveguide phaseshifters using tunable finger-shaped capacitors. A 310/spl deg/ phaseshift was obtained at 30GHz and 35V of tuning voltage with 3.6dB of insertion loss yielding a figure of merit of 85/spl deg//dB.     

High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices

This paper demonstrates gate-all-around (GAA) n- and p-FETs on a silicon-on-insulator with /spl les/ 5-nm-diameter laterally formed Si nanowire channel. Alternating phase shift mask lithography and self-limiting oxidation techniques were utilized to form 140- to 1000-nm-long nanowires, followed by FET fabrication. The devices exhibit excellent electrostatic control, e.g., near ideal subthreshold slope (/spl sim/ 63 mV/dec), low drain-induced barrier lowering (/spl sim/ 10 mV/V), and with I/sub ON//I/sub OFF/ ratio of /spl sim/10/sup 6/. High drive currents of /spl sim/ 1.5 and /spl sim/1.0 mA//spl mu/m were achieved for 180-nm-long nand p-FETs, respectively. It is verified that the threshold voltage of GAA FETs is independent of substrate bias due to the complete electrostatic shielding of the channel body.     

Integrated high-/spl kappa/ (/spl kappa/ /spl sim/19) MIM capacitor with Cu/low-/spl kappa/ interconnects for RF application

We demonstrate a high-performance metal-high /spl kappa/ insulator-metal (MIM) capacitor integrated with a Cu/low-/spl kappa/ backend interconnection. The high-/spl kappa/ used was laminated HfO/sub 2/-Al/sub 2/O/sub 3/ with effective /spl kappa/ /spl sim/19 and the low-/spl kappa/ dielectric used was Black Diamond with /spl kappa/ /spl sim/2.9. The MIM capacitor (/spl sim/13.4 fF//spl mu/m/sup 2/) achieved a Q-factor /spl sim/53 at 2.5 GHz and 11.7 pF. The resonant frequency f/sub r/ was 21% higher in comparison to an equivalently integrated Si/sub 3/N/sub 4/-MIM capacitor (/spl sim/0.93 fF//spl mu/m/sup 2/) having similar capacitance 11.2 pF. The impacts of high-/spl kappa/ insulator and low-/spl kappa/ interconnect dielectric on the mechanism for resonant frequency improvement are distinguished using equivalent circuit analysis. This letter suggests that integrated high-/spl kappa/ MIM could be a promising alternative capacitor structure for future high-performance RF applications.     

The impact of uniform strain applied via bonding onto plastic substrate on MOSFET performance

For the first time, this letter presents a novel post-backend strain applying technique and the study of its impact on MOSFET device performance. By bonding the Si wafer after transistor fabrication onto a plastic substrate (a conventional packaging material FR-4), a biaxial-tensile strain (/spl sim/0.026%) was achieved globally and uniformly across the wafer due to the shrinkage of the bonded adhesive. A drain-current improvement (average /spl Delta/I/sub d//I/sub d//spl sim/10%) for n-MOSFETs uniformly across the 8-in wafer is observed, independent of the gate dimensions (L/sub g//spl sim/55 nm -0.530 /spl mu/m/W /spl sim/2-20 /spl mu/m). The p-MOSFETs also exhibited I/sub d/-improvement by /spl sim/7% under the same biaxial-tensile strain. The strain impact on overall device characteristics was also studied, including increased gate-induced drain leakage and short-channel effects.     

SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology

Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-/spl mu/m CMOS process with a gate-oxide thickness of /spl sim/50 /spl Aring/, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.     

Impact of poly-gate depletion on MOS RF linearity

The distortion behavior for thin oxide MOS transistors can be degraded due to polysilicon-gate depletion effects. The nonlinear, bias-dependent gate capacitance for thin oxide MOSFET's results in significant 2nd-order derivatives in gate capacitance, (/spl part//sup 2/C(V/sub gs/)//spl part/V/sub gs//sup 2/), which in turn results in substantial 3rd-order derivative contributions to drain current, (/spl part//sup 3/I/sub ds///spl part/V/sub gs//sup 3/). This may restrict the use of very-thin oxide MOSFET's in RF applications.     

Turn-on voltage investigation of GaAs-based bipolar transistors with Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ base layers

The fundamental lower limit on the turn on voltage of GaAs-based bipolar transistors is first established, then reduced with the use of a novel low energy-gap base material, Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/. InGaP/GaInAsN DHBTs (x/spl sim/3y/spl sim/0.01) with high p-type doping levels (/spl sim/3/spl times/10/sup 19/ cm/sup -3/) and dc current gain (/spl beta//sub max//spl sim/68 at 234 /spl Omega///spl square/) are demonstrated. A reduction in the turn-on voltage over a wide range of practical base sheet resistance values (100 to 400 /spl Omega///spl square/) is established relative to both GaAs BJTs and conventional InGaP/GaAs HBTs with optimized base-emitter interfaces-over 25 mV in heavily doped, high dc current gain samples. The potential to engineer turn-on voltages comparable to Si- or InP-based bipolar devices on a GaAs platform is enabled by the use of lattice matched Ga/sub 1-x/In/sub x/As/sub 1-y/N/sub y/ alloys, which can simultaneously reduce the energy-gap and balance the lattice constant of the base layer when x/spl sim/3y.     

Manufacturing benefits of disilane as a precursor for polycrystalline silicon films for the advanced CMOS gate electrode

The polycrystalline silicon deposited by single-wafer rapid thermal chemical vapor deposition with both silane (SiH/sub 4/) and disilane (Si/sub 2/H/sub 6/) precursors have been characterized for across wafer uniformity, thickness repeatability, and basic material properties such as grain structure and surface topography. The results show that the disilane process greatly improves the manufacturability of the single-wafer polycrystalline silicon process. Specifically, a /spl sim/50% improvement in the thickness uniformity, /spl sim/25% improvement in surface roughness, and a significantly less sensitivity of the process to hardware have been achieved with similar particle performance. The grain structure of as-deposited and postimplant and anneal films have been compared by X-ray diffraction and transmission electron microscope. NMOS and PMOS capacitors have been fabricated with polycrystalline silicon using silane and disilane precursors. The grain structure and electrical parameters, such as gate leakage currents and gate capacitance, show no significant difference between these two precursors.     

The impact of postbreakdown gate leakage on MOSFET RF performances

When the gate-oxide of a MOSFET breaks down, a leakage path is created between channel and gate. In this work, we demonstrate that a simple leakage current increase model can predict the impact of gate-oxide breakdown on MOSFET performance from dc to microwave frequency. We show that severe reduction in RF performance due to input/output mismatch and a gain reduction can result from gate-oxide breakdown     

A 6.7-fF//spl mu/m/sup 2/ bias-independent gate capacitor (BIGCAP) with digital CMOS process and its application to the loop filter of a differential PLL

A linear bias-independent gate capacitor (BIGCAP) with large intrinsic capacitance and low parasitic capacitance is proposed. BIGCAP is composed of a pair of accumulation-mode n-poly gate capacitors in an n-well and a pair of pMOS gate capacitors, which requires no additional fabrication process steps. Measured results with 1.5-V 0.13-/spl mu/m digital CMOS technology show that the intrinsic capacitance is 6.7 fF//spl mu/m/sup 2/ (6.7 times bigger than that of typical MIM capacitors) and the parasitic capacitance is 1.9% of the intrinsic capacitance (1/5 that of typical MIM capacitors). The linearity is /spl plusmn/2.9% and capacitance variation across a wafer is as small as /spl sigma/= 0.096%. For a 0.1-V threshold voltage variation, the capacitance variation was only /spl sigma/= 0.69% and the linearity ranged from /spl plusmn/2.84% to /spl plusmn/2.93%. For three types of BIGCAP using 1.5-V, 2.5-V, and 3.3-V MOSFETs, less than /spl plusmn/4% linearity is achievable by optimizing the ratio (x) of the pMOS gate capacitors' area to the area of the n-poly gate capacitors, and the optimum x value is within a range of 15%-25%. BIGCAP has been applied to the loop filter of a differential phase-locked loop (PLL) and reduces the gate area of the largest loop filter capacitor to only 35% of that of the conventional design while achieving reasonable jitter of 7.0 ps (rms) and 74.4 ps (peak-to-peak) at 840 MHz with a 1.5-V supply.     

Very high-density (23 fF//spl mu/m/sup 2/) RF MIM capacitors using high-/spl kappa/ TaTiO as the dielectric

A very high density of 23 fF//spl mu/m/sup 2/ has been measured in RF metal-insulator-metal (MIM) capacitors which use high-/spl kappa/ TaTiO as the dielectric. In addition, the devices show a small reduction of 1.8% in the capacitance, from 100 kHz to 10 GHz. Together with these characteristics the MIM capacitors show low leakage currents and a small voltage-dependence of capacitance at 1 GHz. These TaTiO MIM capacitors should be useful for precision RF circuits.