Amorphous Silicon Thin-Film Transistor Backplanes Deposited at 200 °C on Clear Plastic for Lamination to Electrophoretic Displays

The transition of thin-film transistor (TFT) backplanes from rigid plate glass to flexible substrates requires the development of a generic TFT backplane technology on a clear plastic substrate. To be sufficiently stable under bias stress, amorphous-silicon (a-Si:H) TFTs must be deposited at elevated temperatures, therefore the substrate must withstand high temperatures. We fabricated a-Si:H TFT backplanes on a clear plastic substrate at 200degC. The measured stability of the TFTs under gate bias stress was superior to TFTs fabricated at 150degC. The substrate was dimensionally stable within the measurement resolution of 1, allowing for well-aligned 8 times 8 and 32 times 32 arrays of pixels. The operation of the backplane is demonstrated with an electrophoretic display. This result is a step toward the drop-in replacement of glass substrates by plastic foil.     

Low-Temperature Materials and Thin Film Transistors for Flexible Electronics

This paper addresses the low-temperature deposition processes and electronic properties of silicon based thin film semiconductors and dielectrics to enable the fabrication of mechanically flexible electronic devices on plastic substrates. Device quality amorphous hydrogenated silicon (a-Si:H), nanocrystalline silicon (nc-Si), and amorphous silicon nitride (a-SiN/sub x/) films and thin film transistors (TFTs) were made using existing industrial plasma deposition equipment at the process temperatures as low as 75/spl deg/C and 120/spl deg/C. The a-Si:H TFTs fabricated at 120/spl deg/C demonstrate performance similar to their high-temperature counterparts, including the field effect mobility (/spl mu//sub FE/) of 0.8 cm/sup 2/V/sup -1/s/sup -1/, the threshold voltage (V/sub T/) of 4.5 V, and the subthreshold slope of 0.5 V/dec, and can be used in active matrix (AM) displays including organic light emitting diode (OLED) displays. The a-Si:H TFTs fabricated at 75/spl deg/C exhibit /spl mu//sub FE/ of 0.6 cm/sup 2/V/sup -1/s/sup -1/, and V/sub T/ of 4 V. It is shown that further improvement in TFT performance can be achieved by using n/sup +/ nc-Si contact layers and plasma treatments of the interface between the gate dielectric and the channel layer. The results demonstrate that with appropriate process optimization, the large area thin film Si technology suits well the fabrication of electronic devices on low-cost plastic substrates.     

High mobility nanocrystalline silicon transistors on clear plastic substrates

We demonstrate nanocrystalline silicon (nc-Si) top-gate thin-film transistors (TFTs) on optically clear, flexible plastic foil substrates. The silicon layers were deposited by plasma-enhanced chemical vapor deposition at a substrate temperature of 150/spl deg/C. The n-channel nc-Si TFTs have saturation electron mobilities of 18 cm/sup 2/V/sup -1/s/sup -1/ and transconductances of 0.22 /spl mu/S/spl mu/m/sup -1/. With a channel width to length ratio of 2, these TFTs deliver up to 0.1 mA to bottom emitting electrophosphorescent organic light-emitting devices (OLEDs) which were fabricated on a separate glass substrate. These results suggest that high-current, small-area OLED driver TFTs can be made by a low-temperature process, compatible with flexible clear plastic substrates.     

Amorphous-Silicon Thin-Film Transistors Fabricated at 300 °C on a Free-Standing Foil Substrate of Clear Plastic

We have made hydrogenated amorphous-silicon thin-film transistors (TFTs) at a process temperature of 300^degC on free-standing clear-plastic foil substrates. The key to the achievement of flat and smooth samples was to design the mechanical stresses in the substrate passivation and transistor layers, allowing us to obtain functional transistors over the entire active surface. Back-channel-passivated TFTs made at 300 ^degC on glass substrates and plastic substrates have identical electrical characteristics and gate-bias-stress stability. These results suggest that free-standing clear-plastic foil can replace display glass as a substrate from the points of process temperature, substrate and device integrity, and TFT performance and stability.     

High-performance TFTs fabricated on plastic substrates

Poly-Si thin-film transistors (TFTs) have recently been introduced to commercial glass flat-panel displays. This letter presents a manufacturable process for fabricating poly-Si TFTs directly on plastic substrates that exceed TFT parameter requirements for active-matrix displays. Plastic sheets are laminated onto carrier wafers, to allow use of automated tools for manufacturing. In order to maintain adhesion through the whole process, the wafer temperature is kept below 105/spl deg/C. Laser crystallization is used to grow poly-Si, and a quarter-wavelength stack layer is deposited to protect plastic from the laser processing. In order to achieve state-of-the-art poly-Si TFTs on plastic, the gate oxide is optimized. Using a higher temperature anneal after delamination minimizes leakage currents.     

A CMOS smart temperature sensor with a 3/spl sigma/ inaccuracy of /spl plusmn/0.5/spl deg/C from -50/spl deg/C to 120/spl deg/C

A low-cost temperature sensor with on-chip sigma-delta ADC and digital bus interface was realized in a 0.5 /spl mu/m CMOS process. Substrate PNP transistors are used for temperature sensing and for generating the ADC's reference voltage. To obtain a high initial accuracy in the readout circuitry, chopper amplifiers and dynamic element matching are used. High linearity is obtained by using second-order curvature correction. With these measures, the sensor's temperature error is dominated by spread on the base-emitter voltage of the PNP transistors. This is trimmed after packaging by comparing the sensor's output with the die temperature measured using an extra on-chip calibration transistor. Compared to traditional calibration techniques, this procedure is much faster and therefore reduces production costs. The sensor is accurate to within /spl plusmn/0.5/spl deg/C (3/spl sigma/) from -50/spl deg/C to 120/spl deg/C.     

Thin-film transistors on plastic and glass substrates using silicon deposited by microwave plasma ECR-CVD

Thin-film transistors (TFTs) were fabricated on polyimide and glass substrates at low temperatures using microwave ECR-CVD deposited amorphous and nanocrystalline silicon as active layers. The amorphous Si TFT fabricated at 200 /spl deg/C on the polyimide foil had a saturation region field effect mobility of 4.5 cm/sup 2//V-s, a linear region mobility of 5.1 cm/sup 2//V-s, a threshold voltage of 3.7 V, a subthreshold swing of 0.69 V/decade, and an ON/OFF current ratio of 7.9 /spl times/ 10/sup 6/. This large mobility and high ON/OFF current ratio were attributed to the high-quality channel materials with less dangling bond defect states. Nanocrystalline Si TFTs fabricated on glass substrates at 400 /spl deg/C showed a saturation region mobility of 14.1 cm/sup 2//V-s, a linear region mobility of 15.3 cm/sup 2//V-s, a threshold voltage of 3.6 V, and an ON/OFF current ratio of 6.7 /spl times/ 10/sup 6/. TFT performance was mostly independent of substrate type when fabrication conditions were the same.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

1-GHz, 200/spl deg/C, SiC MESFET Clapp oscillator

A SiC Clapp oscillator fabricated on an alumina substrate with chip capacitors and spiral inductors is designed for high-temperature operation at 1GHz. The oscillator operated from 30/spl deg/C to 200/spl deg/C with an output power of 21.8dBm at 1GHz and 200/spl deg/C. The efficiency at 200/spl deg/ C is 15%. The frequency variation over the temperature range is less than 0.5%.     

Low-Temperature Deposition of Hydrogenated Amorphous Silicon in an Electron Cyclotron Resonance Reactor for Flexible Displays

Electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECR-PECVD) is investigated as a technique for depositing hydrogenated amorphous silicon (a-Si : H) at a temperature of 80/spl deg/C, which is compatible with the use of transparent, plastic substrates. The ECR-PECVD reactor is described and the principles underlying its operation explained. In particular, the factors controlling the deposition of a-Si : H by this technique are investigated, and it is shown that control of gas phase reactions between silane and hydrogen species is essential. High-quality a-Si : H is deposited in a narrow processing window with a photosensitivity greater than 10/sup 6/. Thin-film transistors (TFTs) fabricated at 125/spl deg/C incorporating low-temperature a-Si : H as the channel layer have a switching ratio of almost 10/sup 5/. With further optimization of the other material layers, such TFTs could be used for the active matrix transistors in flexible liquid crystal displays on plastic substrates.     

160/spl deg/C pulsed laser operation of AlGaInP-based vertical-cavity surface-emitting lasers

Pulsed lasing operation of a 670 nm AlGaInP-based oxide-confined vertical-cavity surface-emitting laser (VCSEL) at high temperatures is demonstrated. At +120/spl deg/C heatsink temperature output power exceeded 0.5 mW and at +160/spl deg/C 25 /spl mu/W output power was achieved     

High-performance poly-Si TFTs on plastic substrates using a nano-structured separation layer approach

We demonstrate a manufacturable, large-area separation approach for producing high-performance polycrystalline silicon thin-film transistors on flexible plastic substrates. The approach allows the use of high growth-temperature gate oxides and removes the need for hydrogenation. The process flow starts with the deposition of a nano-structured high surface-to-volume ratio film on a reuseable "mother" substrate. This film functions as a sacrificial release layer and is Si-based for process compatibility. After high-temperature TFT fabrication (up to 1100/spl deg/C) is carried to completion on the sacrificial film coated mother substrate, a thick plastic top layer film is applied, and the sacrificial layer is removed by chemical attack. By using this separation process, the temperature, smoothness, and mechanical limitations posed by plastic substrates are completely circumvented. Both excellent n-channel and p-channel TFTs on plastic have been produced. We report here on p-channel TFTs on separated plastic with a linear field effect (hole) mobility of 174 cm/sup 2//V/spl middot/s, on/off current ratio of >10/sup 8/ at V/sub ds/=-0.1 V, off current of <10/sup -11/ A//spl mu/m-channel-width at V/sub ds/=-0.1 V, sub-V/sub t/ swing of /spl sim/200 mV/dec, and threshold voltage of -1.1 V.     

Stable mode-locked operation up to 80 /spl deg/C from an InGaAs quantum-dot laser

We demonstrate the mode-locked operation of a two-section quantum-dot laser in a broad temperature range. Stable mode-locking was observed at temperatures ranging from 20 /spl deg/C to 70 /spl deg/C, with signal-to-noise ratios well over 20 dB and a -3-dB linewidth smaller than 80 kHz. In the temperature range between 70 /spl deg/C and 80 /spl deg/C, the mode-locking was less stable. It was found that in order to provide stable mode-locked operation with increasing temperature, the reverse bias on the absorber section must be reduced accordingly.     

Active-Matrix Amorphous-Silicon TFTs Arrays at 180$^circhboxC$on Clear Plastic and Glass Substrates for Organic Light-Emitting Displays

An amorphous-silicon thin-film transistor (TFT) process with a 180$^circhboxC$maximum temperature using plasma-enhanced chemical vapor deposition has been developed on both novel clear polymer and glass substrates. The gate leakage current, threshold voltage, mobility, and on/off ratio of the TFTs are comparable with those of standard TFTs on glass with deposition temperature of 300$^circhboxC$–350$^circhboxC$. Active-matrix pixel circuits for organic light-emitting displays (LEDs) on both glass and clear plastic substrates were fabricated with these TFTs. Leakage current in the switching TFT is low enough to allow data storage for video graphics array timings. The pixels provide suitable drive current for bright displays at a modest drive voltage. Test active matrices with integrated polymer LEDs on glass showed good pixel uniformity, behaved electrically as expected for the TFT characteristics, and were as bright as 1500$hboxcd/hboxm^2$.     

Complementary metal-oxide-semiconductor thin-film transistor circuits from a high-temperature polycrystalline silicon process on steel foil substrates

We fabricated CMOS circuits from polycrystalline silicon films on steel foil substrates at process temperatures up to 950/spl deg/C. The substrates were 0.2-mm thick steel foil coated with 0.5-/spl mu/m thick SiO/sub 2/. We employed silicon crystallization times ranging from 6 h (600/spl deg/C) to 20 s (950/spl deg/C). Thin-film transistors (TFTs) were made in either self-aligned or nonself-aligned geometries. The gate dielectric was SiO/sub 2/ made by thermal oxidation or from deposited SiO/sub 2/. The field-effect mobilities reach 64 cm/sup 2//Vs for electrons and 22 cm/sup 2//Vs for holes. Complementary metal-oxide-silicon (CMOS) circuits were fabricated with self-aligned TFT geometries, and exhibit ring oscillator frequencies of 1 MHz. These results lay the groundwork for polycrystalline silicon circuitry on flexible substrates for large-area electronic backplanes.     

90/spl deg/C continuous-wave operation of 1.83-/spl mu/m vertical-cavity surface-emitting lasers

Excellent lasing performance is demonstrated for a 1.83-/spl mu/m InGaAlAs-InP vertical-cavity surface-emitting laser (VCSEL) utilizing the buried tunnel junction technology. Threshold currents as low as 190 /spl mu/A at 20/spl deg/C and operating temperatures as high as 90/spl deg/C have been measured. These values are the best ones reported so far for long-wavelength VCSELs.     

Reliability of Active-Matrix Organic Light-Emitting-Diode Arrays With Amorphous Silicon Thin-Film Transistor Backplanes on Clear Plastic

We have fabricated active-matrix organic light emitting diode (AMOLED) test arrays on an optically clear high-temperature flexible plastic substrate at process temperatures as high as 285 degC using amorphous silicon thin-film transistors (a-Si TFTs). The substrate transparency allows for the operation of AMOLED pixels as bottom-emission devices, and the improved stability of the a-Si TFTs processed at higher temperatures significantly improves the reliability of the light emission over time.     

Integration and characterization of amorphous silicon thin-filmtransistor and Mo-tips for active-matrix cathodes

We have designed and monolithically integrated amorphous silicon thin-film transistor (a-Si TFT) with Mo-tip field emitter arrays (FEAs) on glass substrate for active-matrix cathodes (AMCs) in field-emission display (FED) application. In our AMCs, a light shield layer of metal was introduced to reduce the photo leakage and back channel currents of a-Si TFT. The light shield was designed to have the role of focusing grid to focus emitted electron beams from the AMC on the corresponding anode pixel by forming it around the Mo-tip FEAs as well as above the a-Si TFT. The thin film depositions in a-Si TFTs were performed at a high temperature of above 360°C to guarantee the postvacuum packaging process of cathode and anode plates in FED. Also, a novel wet etching process was developed for n⁺-doped-a-Si etching with high etch selectivity to intrinsic a-Si and good etch controllability and was used in the fabrication of inverted stagger TFT with a very thin active layer. The developed a-Si TFTs had good enough performance to be used as control devices for AMCs with Mo-tip emitters. The fabricated AMCs exhibited very effective aging process for field emitters     

1 V CMOS current reference with 50 ppm//spl deg/C temperature coefficient

A CMOS current reference circuit is presented, which can work properly with a supply voltage higher than 1 V. By compensating the temperature performance of the resistor, this circuit gives out a current with a temperature coefficient of 50 ppm//spl deg/C over the temperature range of (0/spl deg/C, 110/spl deg/C) and a 0.5% variation for a supply voltage of 1 to 2.3 V.     

High transmittance TFT-LCD panels using low-/spl kappa/ CVD films

Thin-film transistor liquid crystal display (TFT-LCD) panels of a high transmittance structure were fabricated by using a low-/spl kappa/ dielectric film as a passivation layer. The low-dielectric films were successfully deposited and patterned using a conventional plasma-enhanced chemical vapor deposition (PECVD) and plasma-assisted etching techniques. The interface between the a-Si channel and the overlaying passivation was modified by appropriate plasma treatment prior to the low-/spl kappa/ deposition. TFTs having the a-Si:C:O:H passivation showed a transfer characteristics similar to that of conventional TFTs. The high transmittance panel showed brightness approximately 30% higher than that of a standard panel without degrading other display characteristics, such as crosstalk.