Characteristics of the metal-Oxide-semiconductor transistors

The theory of the MOS transistor in the gradual channel approximation is presented with the assumption of constant surface and bulk charge, and constant surface mobility. From the simple theory, the complete design equations are derived and design curves are calculated. From the analysis, the equivalent circuit parameters of the device are related to the basic properties of the material and geometry of the device. The simple theory is then critically compared with experimental measurements of MOS transistors with circular geometry. The comparison shows good general agreement with the theory of the dc characteristics but discrepancies are found for the differential characteristics such as the transconductance and the gate capacitance. The possible sources of the discrepancies are discussed.     

Limitations of shift-and-ratio based Leff extractiontechniques for MOS transistors with halo or pocket implants

The shift-and-ratio method has been considered as one of the most accurate and consistent techniques for extracting the effective channel-length of the MOS transistor. This method assumes the effective mobility of a long channel and a short channel transistor to be equal. Scaling down the MOS transistor urges the need of including halo (or pocket) implants in the fabrication process. Due to this implant, however, the short channel MOSFET features a degraded effective mobility compared to the long channel reference device. This affects the channel-length extraction and results in unrealistic high values for the extracted effective channel-length for deep submicron transistors with high-dose halo (or pocket) implants     

Analytical I-V relationship incorporating field-dependent mobility for a symmetrical DG MOSFET with an undoped body

A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current-voltage relationship of a DG MOS field-effect transistor. The effects of mobility degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson's equation. Further implications of the model are derived by simplifying the expression in different regimes of operation using various approximations.     

MOS功率晶体管特性的温度效应

已设计的实验能够在同一仪器上方便地测量MOS功率管的脉冲I-V输出特性、直流I-V输出特性和器件内部的温度。对实验结果进行的综合分析表明,阈值电压随温度的增加而减小将引起MOS功率管的热不稳定,而表面迁移率随温度的增高而下降使MOS功率管的直流I-V特性在大电流区域呈观负阻。本文提出了反映热特性的两个特征点,给出了这两点处的栅源电压与器件设计参数的关系,作为MOS功率管热特性设计的依据。     

Study of hot electron degradation in submicrometer gate length MOS transistor fabricated with selectively doped substrate engineering

Investigations are made on the performance and hot electron degradation of sub-μm MOS transistors fabricated with an improved selectively doped substrate (SDS) and with the conventional deep punch through implant (DPI) structures. The sub-μm gate length of the transistor was defined by a novel subtractive photolithography technique. The technique is described and the process details are given. The sub-μm transistor performance is characterised by electron mobility, inverse subthreshold slope, substrate sensitivity and drain induced barrier lowering (DIBL) for the two structures. The substrate current and hot electron degradation effect (HED) were measured and the results are compared for SDS and DPI techniques. It is shown that SDS structure reduces HED and surface punchthrough effects in sub-μm MOS transistors.     

Study of performance scaling of 22-nm epitaxial delta-doped channel MOS transistor

Epitaxial delta-doped channel (EδDC) profile is a promising approach for extending the scalability of bulk metal oxide semiconductor (MOS) technology for low-power system-on-chip applications. A comparative study between EδDC bulk MOS transistor with gate length L_g = 22 nm and a conventional uniformly doped channel (UDC) bulk MOS transistor, with respect to various digital and analogue performances, is presented. The study has been performed using Silvaco technology computer-aided design device simulator, calibrated with experimental results. This study reveals that at smaller gate length, EδDC transistor outperforms the UDC transistor with respect to various studied performances. The reduced contribution of the lateral electric field in the channel plays the key role in this regard. Further, the carrier mobility in EδDC transistor is higher compared to UDC transistor. For moderate gate and drain bias, the impact ionisation rate of the carriers for EδDC MOS transistor is lower than that of the UDC transistor. In addition, at 22 nm, the performances of a EδDC transistor are competitive to that of an ultra-thin body silicon-on-insulator transistor.     

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

Remarks on Analysis, Design and Amplitude Stability of MOS Colpitts Oscillator

The small-signal analysis shows that the MOS Colpitts oscillator is described by a third order characteristic equation. The procedure for finding the second order approximation is defined, and the solution corresponding to this approximation is found. Then the equations for transistor transconductance describing function are analyzed, and the design procedure corresponding to the "convenient" operation point is given. The same equations are also used for the analysis of amplitude stability in this oscillator. It is shown that the amplitude self-modulation (squegging) in the considered oscillator is absent for any conducting angle of the transistor.     

Measurements on depletion-mode field effect transistors and buried channel MOS capacitors for the characterization of bulk transfer charge-coupled devices

The properties of bulk transfer charge-coupled devices (BCCD's) may be characterized from measurements obtained using MOS capacitors and field effect transistors. Models are presented for the MOS capacitor and field effect transistor for the case where a shallow doped layer of polarity opposite to that of the substrate is incorporated between the oxide and the substrate. These models explain the observed frequency dependence of the capacitance-voltage (C-V) characteristics of these devices.Techniques are presented for determining the impurity profile of the buried layer from the low frequency C-V measurements made on MOS transistors. The majority carrier mobilities in the buried layer and at the surface are measured for the BCCD's and compared to the surface minority carrier mobility measured for the surface channel CCD's. Generation lifetimes at the surface, in the buried layer and in the underlying substrate are determined from capacitance-time (pulse bias C-t) measurements and leakage current measurements of the MOS capacitors and transistors. Methods are demonstrated whereby the depth from the oxide interface of the potential minimum (depth of the buried channel) and its potential can be determined as a function of the various applied biases.     

Thermal noise in buried-channel MOSFET

A new model for the thermal noise in long buried-channel MOS transistors is presented. The model calculates the dependence of the transistor noise performance on both device fabrication parameters and the four terminal voltages. The noise calculations are based on the gradual channel approximation, using simple charge-voltage relations. Analytic models are obtained for the different regions of operation of the transistor. Noise measurements are presented and compared with results predicted by the model     

Modeling of the MOSFET inversion charge and drain current, inmoderate inversion

The widespread use of MOS technology in analog circuit design demands a precise and efficient circuit simulation model of the MOS transistor valid in all regions of inversion. Currently available circuit simulation models fail in the intermediate range of gate voltages, known as the moderate inversion region. Expressions characterizing the large-signal behavior of the long-channel MOS transistor in the moderate inversion region are derived. The correct dependencies on all the physical and process parameters are preserved by a careful approximation to the physical equations, based on the charge sheet assumption. Another goal is to develop expressions that treat the moderate inversion as a small, voltage-dependent correction to currently existing simplified models. This approach should allow a simple modification of the existing circuit simulation models to improve the accuracy in moderate inversion. The model was compared with a numerical charge sheet model and with experimental measurements of a long-channel, ion-implanted NMOS transistor. The expressions could serve as a basis for a comprehensive MOSFET circuit simulation model     

Characteristics of inversion-channel and buried-channel MOS devicesin 6H-SiC

Inversion-channel and buried-channel gate-controlled diodes and MOSFET's are investigated in the wide bandgap semiconductor 6H-SiC. These devices are fabricated using thermal oxidation and ion implantation. The gate-controlled diodes allow room temperature measurement of surface states, which is difficult with MOS capacitors due to the 3 eV bandgap of 6H-SiC. An effective electron mobility of 20 cm²/Vs is measured for the inversion-channel devices and a bulk electron mobility of 180 cm²/Vs is found in the channel of the buried-channel MOSFET. The buried-channel transistor is the first ion-implanted channel device in SIC and the first buried-channel MOSFET in the 6H-SiC polytype     

Electrical characteristics of a DSA MOS transistor with a fine structure

Fabrication technologies and electrical characteristics of a diffusion self-aligned MOS transistor (DSA MOST) or a double-diffused MOS transistor (DMOST) are discussed in comparison with a conventional short-channel MOS transistor as a fundamental device for a VLSI. The symmetrical DSA MOS LSI with enhancement depletion configurations requires six photolithographic steps and the number of the steps is the same as that of an NMOS LSI with small physical dimensions. The only difference is the step orders of the enhancement channel doping in these devices. The lowering effects of the threshold voltage and the source drain breakdown voltage are smaller in the DSA MOST than in the conventional MOS transistor. The drain current IDof the symmetrical DSA MOS transistor is, respectively, 1.13 (in the nonsaturation region) and 1.33 (in the saturation region) times larger than that of the conventional short-channel NMOS transistor at the effective gate voltage of 3.0 V. The improvement of the short-channel effect, the current voltage characteristics, and the power-delay product are obtained by the scaling of the DSA MOS transistor.     

Comparative Study of Energy Quantization Approaches in Nanoscale MOSFETs

An analytical model has been developed to study inversion layer quantization in the ultra thin oxide MOS(metal oxide semiconductor)structures using variation and triangular well approaches.Accurate modeling of the inversion charge density using the continuous surface potential equations has been done.No approximation has been taken to model the inversion layer quantization process.The results show that the variation approach describes inversion layer quantization process accurately as it matches well with the BSIM 5(Berkeley short channel insulated gate field effect transistor model 5)results more closely compared with triangular well approach.     

Changes of mobility along a depletion type MOS transistor channel

The characteristics of a depletion type N-channel MOS transistor, with a built-in inversion layer, show considerable deviation from the behaviour expected of a device with a constant effective mobility along its channel. Experiment indicates reduction of the mobility in the direction of the drain due to the action of the drain induced field. A functional dependence of mobility on this field leading to a constant velocity is assumed and a set of equations describing this method is derived for various ranges of drain voltage. A special device, with voltage probes situated along its channel, was constructed and the drain characteristics, saturation point and potential distribution along the channel for the drain-field dependent mobility model and the constant mobility model were compared with experimental results obtained from it. The variable mobility model was shown to be in much better agreement with experiment.     

Measurements and modeling of the n-channel MOSFET inversion layermobility and device characteristics in the temperature range 60-300 K

Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q _b, and inversion layer charge Q_i. The experimental data for Q_b and Q_i were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) μ(E_eff) dependence, which becomes more pronounced at low temperatures and low E_eff, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures     

Noise in DMOS transistors in a BICMOS-technology

An experimental and theoretical study of the 1/f noise and the thermal noise in double-diffused MOS (DMOS) transistors in a BICMOS-technology has been carried out. By using an analytical model that consists of an enhancement MOS transistor in series with a depletion MOS transistor and a resistance, and by attributing noise sources to each device, the noise in DMOS devices is simulated accurately. Three distinct regions of operation are defined: enhancement transistor control, depletion transistor control and the linear region. In the first region, the noise is strictly determined by the enhancement transistor. It was found that the 1/f noise in this region is caused by mobility fluctuations and is very low. In the depletion transistor control region both transistors influence the total noise. Here the 1/f noise is dominated by the depletion transistor. The series resistance is only of importance in the linear region     

A High-Frequency MOS Transistor Model and its Effects on Radio-Frequency Circuits

Accurate modeling and efficient parameter extraction of a small signal equivalent circuit of MOS transistors for high-frequency operation are presented. The small-signal equivalent circuit is based on the quasi-static approximation which was found to be adequate up to 10 GHz for MOS transistors fabricated by a 20 GHz cutoff frequency technology. The extrinsic components and substrate coupling effects are properly included. Direct extraction is performed by Y-parameter analysis on the equivalent circuit in the linear and saturation regions of operation. A low-noise amplifier is used to illustrate the effects on circuit performance due to accurate inclusion of extrinsic components in the model. Good agreement between simulated results and measured data on high-frequency transistor characteristics has been achieved.     

Theory of the surface depletion region for semiconductors with linearly graded impurity profiles

The theory of the surface depletion region for a semiconductor with a linearly graded impurity profile is described in this paper. Using the depletion approximation, expressions for the electric field, potential and surface potential are derived as functions of the profile parameters. The theoretical high frequency CV characteristics of an MOS structure built on such a surface are generated and compared with the experimental results obtained on MOS capacitors fabricated on implanted surfaces. The agreement between the theory and experimental results is very good. Since many diffused and implanted profiles can be approximated by piecewise-linear segments, the theory presented here can be extended and used in the modelling and simulation of a variety of ion-implanted MOS structures.