Thermally stable Ge/Ag/Ni Ohmic contact for InAlAs/InGaAs/InP HEMTs

Excellent annealed ohmic contacts based on Ge/Ag/Ni metallization have been realized in a temperature range between 385 and 500/spl deg/C, with a minimum contact resistance of 0.06 /spl Omega//spl middot/mm and a specific contact resistivity of 2.62 /spl times/10/sup -7/ /spl Omega//spl middot/cm/sup 2/ obtained at an annealing temperature of 425/spl deg/C for 60 s in a rapid thermal annealing (RTA) system. Thermal storage tests at temperatures of 215 and 250/spl deg/C in a nitrogen ambient showed that the Ge/Ag/Ni based ohmic contacts with an overlay of Ti/Pt/Au had far superior thermal stabilities than the conventional annealed AuGe/Ni ohmic contacts for InAlAs/InGaAs high electron mobility transistors (HEMTs). During the storage test at 215/spl deg/C, the ohmic contacts showed no degradation after 200 h. At 250/spl deg/C, the contact resistance value of the Ge/Ag/Ni ohmic contact increased only to a value of 0.1 /spl Omega//spl middot/mm over a 250-h period. Depletion-mode HEMTs (D-HEMTs) with a gate length of 0.2 /spl mu/m fabricated using Ge/Ag/Ni ohmic contacts with an overlay of Ti/Pt/Au demonstrated excellent dc and RF characteristics.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

InAlN/GaN HEMTs: a first insight into technological optimization

High-electron mobility transistors (HEMTs) were fabricated from heterostructures consisting of undoped In/sub 0.2/Al/sub 0.8/N barrier and GaN channel layers grown by metal-organic vapor phase epitaxy on (0001) sapphire substrates. The polarization-induced two-dimensional electron gas (2DEG) density and mobility at the In/sub 0.2/Al/sub 0.8/N/GaN heterojunction were 2/spl times/10/sup 13/ cm/sup -2/ and 260 cm/sup 2/V/sup -1/s/sup -1/, respectively. A tradeoff was determined for the annealing temperature of Ti/Al/Ni/Au ohmic contacts in order to achieve a low contact resistance (/spl rho//sub C/=2.4/spl times/10/sup -5/ /spl Omega//spl middot/cm/sup 2/) without degradation of the channels sheet resistance. Schottky barrier heights were 0.63 and 0.84 eV for Ni- and Pt-based contacts, respectively. The obtained dc parameters of 1-/spl mu/m gate-length HEMT were 0.64 A/mm drain current at V/sub GS/=3 V and 122 mS/mm transconductance, respectively. An HEMT analytical model was used to identify the effects of various material and device parameters on the InAlN/GaN HEMT performance. It is concluded that the increase in the channel mobility is urgently needed in order to benefit from the high 2DEG density.     

Design and fabrication of RESURF MOSFETs on 4H-SiC(0001), (112~0), and 6H-SiC(0001)

Design and fabrication of lateral SiC reduced surface field (RESURF) MOSFETs have been investigated. The doping concentration (dose) of the RESURF and lightly doped drain regions has been optimized to reduce the electric field crowding at the drain edge or in the gate oxide by using device simulation. The optimum oxidation condition depends on the polytype: N/sub 2/O oxidation at 1300/spl deg/C seems to be suitable for 4H-SiC, and dry O/sub 2/ oxidation at 1250/spl deg/C for 6H-SiC. The average inversion-channel mobility is 22, 78, and 68 cm/sup 2//Vs for 4H-SiC(0001), (112~0), and 6H-SiC(0001) MOSFETs, respectively. RESURF MOSFETs have been fabricated on 10-/spl mu/m-thick p-type 4H-SiC(0001), (112~0), and 6H-SiC(0001) epilayers with an acceptor concentration of 1/spl times/10/sup 16/ cm/sup -3/. A 6H-SiC(0001) RESURF MOSFET with a 3-/spl mu/m channel length exhibits a high breakdown voltage of 1620 V and an on-resistance of 234 m/spl Omega//spl middot/cm/sup 2/. A 4H-SiC(112~0) RESURF MOSFET shows the characteristics of 1230 V-138 m/spl Omega//spl middot/cm/sup 2/.     

Microwave performance of GaAs MOSFET with wet thermally oxidized InAlP gate dielectric

This paper reports the first demonstration of a microwave-frequency operation of a GaAs MOSFET fabricated using a wet thermal oxidization of InAlP lattice-matched to GaAs to form a native-oxide gate insulator. Devices with 1-/spl mu/m gate lengths exhibit a cutoff frequency (f/sub t/) of 13.7 GHz and a maximum frequency of oscillation (f/sub max/) of 37.6 GHz, as well as a peak extrinsic transconductance of 73.6 mS/mm. A low-leakage current density of 3.8/spl times/10/sup -3/ A/cm/sup 2/ at 1-V bias for an MOS capacitor demonstrates the good insulating properties of the /spl sim/ 11-nm thick native gate oxide.     

Lateral RESURF MOSFET fabricated on 4H-SiC(0001/sup ~/) C-face

Lateral reduced surface field (RESURF) metal-oxide-semiconductor field-effect transistors (MOSFETs) have been fabricated on 4H-SiC(0001/sup ~/) carbon face (C-face) substrates. The channel mobility of a lateral test MOSFET on a C-face was 41 cm/sup 2//V/spl middot/s, which was much higher than 5 cm/sup 2//V/spl middot/s for that on a Si-face. The specific on-resistance of the lateral RESURF MOSFET on a C-face was 79/spl Omega/ /spl middot/ cm/sup 2/, at a gate voltage of 25 V and drain voltage of 1 V. The breakdown voltage was 460 V, which was 79% of the designed breakdown voltage of 600 V. We measured the temperature dependence of R/sub on, sp/ for the RESURF MOSFET on the C-face. The R/sub on, sp/ increased with the increase in temperature.     

Nonalloyed ohmic contacts in AlGaN/GaN HEMTs by ion implantation with reduced activation annealing temperature

This letter reports AlGaN/GaN high-electron mobility transistors with capless activation annealing of implanted Si for nonalloyed ohmic contacts. Source and drain areas were implanted with an Si dose of 1/spl times/10/sup 16/ cm/sup -2/ and were activated at /spl sim/1260/spl deg/C in a metal-organic chemical vapor deposition system in ammonia and nitrogen at atmospheric pressure. Nonalloyed ohmic contacts to ion-implanted devices showed a contact resistance of 0.96 /spl Omega//spl middot/mm to the channel. An output power density of 5 W/mm was measured at 4 GHz, with 58% power-added efficiency and a gain of 11.7 dB at a drain bias of 30 V.     

GaAs MOSFET using InAlP native oxide as gate dielectric

GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) using wet thermally oxidized InAlP as the gate insulator are reported for the first time. Leakage current measurements show that the 11-nm-thick native oxide grown from an In/sub 0.49/Al/sub 0.51/P layer lattice-matched to GaAs has good insulating properties, with a measured leakage current density of 1.39/spl times/10/sup -7/ mA//spl mu/m/sup 2/ at 1 V bias. GaAs MOSFETs with InAlP native gate oxide have been fabricated with gate lengths from 7 to 2 /spl mu/m. Devices with 2-/spl mu/m-long gates exhibit a peak extrinsic transconductance of 24.2 mS/mm, an intrinsic transconductance of 63.8 mS/mm, a threshold voltage of 0.15 V, and an off-state gate-drain breakdown voltage of 21.2 V. Numerical Poisson's equation solutions provide close agreement with the measured sheet resistance and threshold voltage.     

BC high-/spl kappa//metal gate Ge/C alloy pMOSFETs fabricated directly on Si (100) substrates

Buried-channel (BC) high-/spl kappa//metal gate pMOSFETs were fabricated on Ge/sub 1-x/C/sub x/ layers for the first time. Ge/sub 1-x/C/sub x/ was grown directly on Si (100) by ultrahigh-vacuum chemical vapor deposition using methylgermane (CH/sub 3/GeH/sub 3/) and germane (GeH/sub 4/) precursors at 450/spl deg/C and 5 mtorr. High-quality films were achieved with a very low root-mean-square roughness of 3 /spl Aring/ measured by atomic force microscopy. The carbon (C) content in the Ge/sub 1-x/C/sub x/ layer was approximately 1 at.% as measured by secondary ion mass spectrometry. Ge/sub 1-x/C/sub x/ BC pMOSFETs with an effective oxide thickness of 1.9 nm and a gate length of 10 /spl mu/m exhibited high saturation drain current of 10.8 /spl mu/A//spl mu/m for a gate voltage overdrive of -1.0 V. Compared to Si control devices, the BC pMOSFETs showed 2/spl times/ enhancement in the saturation drain current and 1.6/spl times/ enhancement in the transconductance. The I/sub on//I/sub off/ ratio was greater than 5/spl times/10/sup 4/. The improved drain current represented an effective hole mobility enhancement of 1.5/spl times/ over the universal mobility curve for Si.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

GaAs MOSFET with oxide gate dielectric grown by atomic layer deposition

For the first time, a III-V compound semiconductor MOSFET with the gate dielectric grown by atomic layer deposition (ALD) is demonstrated. The novel application of the ALD process on III-V compound semiconductors affords tremendous functionality and opportunity by enabling the formation of high-quality gate oxides and passivation layers on III-V compound semiconductor devices. A 0.65-/spl mu/m gate-length depletion-mode n-channel GaAs MOSFET with an Al/sub 2/O/sub 3/ gate oxide thickness of 160 /spl Aring/ shows a gate leakage current density less than 10/sup -4/ A/cm/sup 2/ and a maximum transconductance of 130 mS/mm, with negligible drain current drift and hysteresis. A short-circuit current-gain cut-off frequency f/sub T/ of 14.0 GHz and a maximum oscillation frequency f/sub max/ of 25.2 GHz have been achieved from a 0.65-/spl mu/m gate-length device.     

Use of Au/Te/Ni films for ohmic contact to GaAs

Ohmic contacts to n-type GaAs are usually fabricated by alloying AuGe/Ni films on GaAs. Ge acts as a donor to GaAs for fabrication of the ohmic contact. In an attempt to replace Ge, which is an amphoteric impurity, with a group VI element to improve on the ohmic contact resistivity, experiments were done with AuTe and AuTe/Ni contacts. A very low resistivity of ∼5 × 10^-7Ω.cm²was obtained by alloying 1700 Å of AuTe film with 300 Å of nickel on top at 510°C. This is the lowest contact resistivity obtained with any material other than AuGe/Ni on n-type GaAs.     

Low loss, thin p-clad 980-nm InGaAs semiconductor laser diodes with an asymmetric structure design

Thin p-clad InGaAs ridge waveguide quantum-well lasers having an asymmetric structure design were fabricated. The internal absorption coefficient is as low as 2.5 cm/sup -1/, due to the restricted field extension in the 0.3-/spl mu/m-thick p-type top AlGaAs cladding layer. Ti-Pt-Au metallization is used outside the ridge to provide adherence on the oxide while Au directly contacts the ridge region. It is shown that the most likely source of loss in these thin p-clad devices is scattering at the rough interface between Au and the p/sup ++/ top GaAs layer, after ohmic contact heat treatment.     

Implant-free high-mobility flatband MOSFET: principles of operation

Principles of operation of implant-free enhancement-mode MOSFETs (flatband MOSFET) are discussed. Epitaxial-layer structures designed for use in implant-free enhancement-mode devices and employing a high-/spl kappa/ dielectric (/spl kappa//spl cong/20) and a strained InGaAs channel layer with a thickness of 10 nm have been manufactured on GaAs substrate. Proceeding from measured electron mobility /spl mu/ as a function of the sheet-carrier concentration, enhancement-mode design considerations, saturation current I/sub Dss/, and mobility requirements are discussed using two-dimensional device simulations. For the flatband MOSFET to compete successfully with other device designs, certain minimum channel mobilities are required. For RF applications, /spl mu/ should exceed 5000 cm/sup 2//Vs while high-performance MOSFETs for digital applications may require even higher mobility for optimum operation. Finally, measured data of first 1-/spl mu/m-GaAs-flatband enhancement-mode MOSFETs are presented; the saturation velocity of the InGaAs channel layer is derived; and measured I/sub Dss/ data are compared to the results obtained by simulations.     

Effect of extrinsic impedance and parasitic capacitance on figure of merit of RF MOSFET

This paper investigates the impact of source/drain impedance, gate-to-bulk capacitance, and gate resistance on device properties from 0 to 50 GHz for 0.13-/spl mu/m MOSFETs. Better device characteristics (g/sub m/ and C/sub gg/) can be found on MOSFETs with lower metal (or source/drain) resistance. But the best frequency characteristics (f/sub T/ and f/sub max/) occurred on MOSFETs with medium metal (or source/drain) resistance due to the increased interconnection capacitances. For radio frequency MOSFETs with finger-gate structure, better high-frequency behavior occurred on devices with medium finger-gate width W/sub f/ because of the tradeoff between gate (or source/drain) resistance and parasitic capacitance.     

High-performance nonhydrogenated nickel-induced laterally crystallized P-channel poly-Si TFTs

High-performance nickel-induced laterally crystallized (NILC) p-channel poly-Si thin-film transistors (TFTs) have been fabricated without hydrogenation. Two different thickness of Ni seed layers are selected to make high-performance p-type TFTs. A very thin seed layer (e.g., 5 /spl Aring/) leads to marginally better performance in terms of transconductance (Gm) and threshold voltage (V/sub th/) than the case of a 60 /spl Aring/ Ni seed layer. However, the p-type poly-Si TFTs crystallized by the very thin Ni seeding result in more variation in both V/sub th/ and G/sub m/ from transistor to transistor. It is believed that differences in the number of laterally grown polycrystalline grains along the channel cause the variation seen between 5 /spl Aring/ NILC TFTs compared to 60-/spl Aring/ NILC TFTs. The 60 /spl Aring/ NILC nonhydrogenated TFTs show consistent high performance, i.e., typical electrical characteristics have a linear field-effect hole mobility of 156 cm/sup 2//V-S, subthreshold swing of 0.16 V/dec, V/sub th/ of -2.2 V, on-off ratio of >10/sup 8/, and off-current of <1/spl times/10/sup -14/ A//spl mu/m when V/sub d/ equals -0.1 V.     

Improvement of the luminous intensity of light-emitting diodes by using highly transparent Ag-indium tin oxide p-type ohmic contacts

We have investigated Ag-indium tin oxide (ITO) scheme for obtaining high-quality p-type ohmic contacts for GaN-based light-emitting diodes (LEDs). The Ag(1 nm)-ITO(200 nm) contacts exhibit greatly improved electrical characteristics when annealed at temperatures in the range 400/spl deg/C-600/spl deg/C for 1 min in air, yielding specific contact resistances of /spl sim/10/sup -4/ /spl Omega//spl middot/cm/sup 2/. In addition, the contacts give transmittance of about 96% at 460 nm, which is far better than that of the conventionally used oxidized Ni-Au contacts. It is shown that the luminous intensity of blue LEDs fabricated with the Ag-ITO contacts is about three times higher than that of LEDs with oxidized Ni-Au contacts. This result strongly indicates that the Ag-ITO scheme can serve as a highly promising p-type ohmic contact for the realization of high brightness near ultraviolet LEDs.     

Evolution of surface morphology of alloyed AuGe/Ni/Au ohmic contacts to GaAs microwave FETs

During post-deposition alloying of AuGe/Ni/Au ohmic contacts to microwave transistors, there is interdiffusion of alloy materials and GaAs into each other. Outdiffusion from substrate greatly influences the surface roughness of the contacts as a function of alloying temperature. During our experiments, we have observed that the RMS roughness of the contact surface followed the trend of contact resistance with alloying temperature. We seek to explain this evolution of surface morphology using a model involving the phenomena of coalescence and outdiffusion occurring simultaneously.     

Ohmic contact penetration and encroachment in GaAs/AlGaAs and GaAsFETs

Hypoeutectic AuGe/Ni ohmic contacts on GaAs and GaAs/AlGaAs were characterized by SEM, TEM, and energy dispersive X-ray analysis. The two main components of the contact were confirmed to be NiGeAs islands distributed in an Au-Ga alloy. The NiGeAs islands were larger and more evenly distributed on GaAs MESFETs than on GaAs/AlGaAs MODFETs. Vertical penetration was impeded but not halted by AlGaAs. Since the contacts did not melt during the alloying cycle, there was no lateral encroachment observed