A fourth-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors

This paper presents the design and implementation of a high-order /spl Sigma//spl Delta/ interface for micromachined inertial sensors, which employs an electronic filter in series with the mechanical sensor element to reject the excessive in-band quantization noise inherently present in state-of-the-art second-order solutions. A fourth-order prototype was fabricated in a standard 0.5-/spl mu/m CMOS process. The active circuit area measures 0.9 mm/sup 2/, and the interface consumes 13 mW from a 5-V supply and achieves resolution of 1/spl deg//s//spl radic/Hz with a gyroscope and 150/spl mu/g//spl radic/Hz with an accelerometer. Comparison between the measured and simulated behavior of the system shows that the contribution of the quantization error to the total noise is negligible.     

A low-noise low-offset capacitive sensing amplifier for a 50-/spl mu/g//spl radic/Hz monolithic CMOS MEMS accelerometer

This paper describes a CMOS capacitive sensing amplifier for a monolithic MEMS accelerometer fabricated by post-CMOS surface micromachining. This chopper stabilized amplifier employs capacitance matching with optimal transistor sizing to minimize sensor noise floor. Offsets due to sensor and circuit are reduced by ac offset calibration and dc offset cancellation based on a differential difference amplifier (DDA). Low-duty-cycle periodic reset is used to establish robust dc bias at the sensing electrodes with low noise. This work shows that continuous-time voltage sensing can achieve lower noise than switched-capacitor charge integration for sensing ultra-small capacitance changes. A prototype accelerometer integrated with this circuit achieves 50-/spl mu/g//spl radic/Hz acceleration noise floor and 0.02-aF//spl radic/Hz capacitance noise floor while chopped at 1 MHz.     

A high performance Σ-Δ readout circuitry for μg resolution microaccelerometers

This paper reports a second order electromechanical sigma-delta readout for micro-g resolution accelerometers in addition to other high-sensitivity capacitive microsensors with large base capacitance. The chip implements a switched-capacitor readout front-end and an oversampled sigma-delta modulator, and hence can be used for both open-loop analog readout and closed-loop control and readout with direct digital output. The readout circuit has more than 115 dB dynamic range and can resolve less than 3 aF/√Hz. Also this IC includes start-up circuit and feedback mechanism for closed-loop control of the accelerometer with a single 5 V supply in a ±4 g range. Together with the accelerometer, bandwidth of the overall system is limited with the sensor resonance frequency (1.53 kHz) in the open-loop mode. However in closed loop mode, oversampling of the acceleration data increases the bandwidth of the system up to few hundred kilohertz which is limited with the cut-off frequency of the low-pass filter placed at the output of the system. The start-up circuit allows rebalancing of a thick silicon proof mass with the limited 5 V supply after system start from power down or in the case of over-range input acceleration. The readout chip has been combined with a Silicon-On-Glass lateral accelerometer, which has a high sensitivity of 1.88 pF/g with large proof mass and long finger structures. A digital filtration and decimation circuitry is also implemented to signal process the output bit stream of the readout circuit. The complete module consumes 16 mW from a ±2.5 V supply and has an adjustable sensitivity up to 8 V/g with a noise level of 4.8 μg/√Hz in open-loop.     

Cryogenic capacitive transimpedance amplifier for astronomical infrared detectors

We have developed a new capacitive transimpedance amplifier (CTIA) that can be operated at 2 K, and have good performance as readout circuits of astronomical far-infrared array detectors. The circuit design of the present CTIA consists of silicon p-MOSFETs and other passive elements. The process is a standard Bi-CMOS process with 0.5 /spl mu/m design rule. The open-loop gain of the CTIA is more than 300, resulting in good integration performance. The output voltage swing of the CTIA was 270 mV. The power consumption for each CTIA is less than 10 /spl mu/W. The noise at the output showed a 1/f noise spectrum of 4 /spl mu/V//spl radic/Hz at 1 Hz. The performance of this CTIA nearly fulfills the requirements for the far-infrared array detectors onboard ASTRO-F, Japanese infrared astronomical satellite to be launched in 2005.     

Single wafer encapsulation of MEMS devices

Packaging of micro-electro-mechanical systems (MEMS) devices has proven to be costly and complex, and it has been a significant barrier to the commercialization of MEMS. We present a packaging solution applicable to several common MEMS devices, such as inertial sensors and micromechanical resonators. It involves deposition of a 20 /spl mu/m layer of epi-polysilicon over unreleased devices to act as a sealing cap, release of the encapsulated parts via an HF vapor release process, and a final seal of the parts in 7 mbar (700 Pa) vacuum. Two types of accelerometers, piezoresistive and capacitive sensing, were fabricated. Piezoresistive accelerometers with a footprint smaller than 3 mm/sup 2/ had a resolution of 10 /spl mu/g//spl radic/Hz at 250 Hz. Capacitive accelerometers with a 1 mm/sup 2/ footprint had a resolution of 1 mg/spl radic/Hz over its 5 kHz bandwidth. Resonators with a quality factor as high as 14,000 and resonant frequency from 50 kHz to 10 MHz have also been built. More than 100 capacitive accelerometers and 100 resonators were tested, and greater than 90% of the resonators and accelerometers were functional.     

High-order electromechanical /spl Sigma//spl Delta/ modulation in micromachined inertial sensors

Analysis of second-order electromechanical sigma-delta (/spl Sigma//spl Delta/) inertial sensors shows that in-band quantization error introduces a resolution penalty, which cannot be eliminated by oversampling. In addition, a tradeoff between resolution and phase compensation forces such systems to operate with reduced phase margin. This paper introduces high-order electromechanical /spl Sigma//spl Delta/ modulation as an approach, which eliminates the quantization noise overhead and allows for increased phase compensation without degrading the resolution. Quasi-linear analysis is used to evaluate the contribution of the individual noise sources to the output of the system and to examine the effect of noise interaction on the behavior of electromechanical /spl Sigma//spl Delta/ modulators.     

An offset-canceling low-noise lock-in architecture for capacitive sensing

We describe an offset-canceling low-noise lock-in architecture for capacitive sensing. We take advantage of the properties of modulation and demodulation to separate the signal from the DC offset and use nonlinear multiplicative feedback to cancel the offset. The feedback also attenuates out-of-band noise and further enhances the power of a lock-in technique. Experimentally, in a 1.5-/spl mu/m BiCMOS chip, a fabrication DC offset of 2 mV and an intentional offset of 100 mV were attenuated to 9 /spl mu/V. Our offset-canceling technique could also be useful for practical multipliers that need tolerance to fabrication errors. We present a detailed theoretical noise analysis of our architecture that is confirmed by experiment. As an example application, we demonstrate the use of our architecture in a simple capacitive surface-microelectromechanical-system vibration sensor where the performance is limited by mechanical Brownian noise. However, we show that our electronics limits us to 30 /spl mu/g//spl radic/Hz, which is at least six times lower than the noise floor of commercial state-of-the-art surface-micromachined inertial sensors. Our architecture could, thus, be useful in high-performance inertial sensors with low mechanical noise. In a 1-100-Hz bandwidth, our electronic detection threshold corresponds to a one-part-per-eight-million change in capacitance.     

Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers

This paper describes a novel low-power low-noise CMOS voltage-current feedback transimpedance amplifier design using a low-cost Agilent 0.5-/spl mu/m 3M1P CMOS process technology. Theoretical foundations for this transimpedance amplifier by way of gain, bandwidth and noise analysis are developed. The bandwidth of the amplifier was extended using the inductive peaking technique, and, simulation results indicated a -3-dB bandwidth of 3.5 GHz with a transimpedance gain of /spl ap/60 dBohms. The dynamic range of the amplifier was wide enough to enable an output peak-to-peak voltage swing of around 400 mV for a test input current swing of 100 /spl mu/A. The output noise voltage spectral density was 12 nV//spl radic/Hz (with a peak of /spl ap/25 nV//spl radic/Hz), while the input-referred noise current spectral density was below 20 pA//spl radic/Hz within the amplifier frequency band. The amplifier consumes only around 5 mA from a 3.3-V power supply. A test chip implementing the transimpedance amplifier was also fabricated using the low-cost CMOS process.     

Design and noise analysis of a sigma-delta capacitive micromachined accelerometer

A single-loop fourth-order sigma-delta (∑△) interface circuit for a closed-loop micromachined accelerometer is presented.Two additional electronic integrators are cascaded with the micromachined sensing element to form a fourth-order loop filter.The three main noise sources affecting the overall system resolution of a ∑Δ accelerometer,mechanical noise,electronic noise and quantization noise,are analyzed in detail.Accurate mathematical formulas for electronic and quantization noise are established.The ASIC is fabricated in a 0.5 μm two-metal two-poly n-well CMOS process.The test results indicate that the mechanical noise and electronic noise are 1 μg(Hz) and 8 μV/(Hz)respectively,and the theoretical models of electronic and quantization noise agree well with the test and simulation results.     

Amplifier techniques for combining low noise, precision, and high-speed performance

A monolithic operational amplifier is presented which optimizes voltage noise both in the audio frequency band, and in the low frequency instrumentation range. In addition, the design demonstrates that the requirements for low noise do not necessitate compromising the specifications in other respects. Techniques are set forth for combining low noise with high-speed and precision performance for the first time in a monolithic amplifier. Achieved results are: 3 nV//spl radic/Hz white noise, 80 nV/SUB p-p/ noise from 0.1 to 10 Hz, 17 V//spl mu/s slew rate, 63 MHz gain-bandwidth product, 10 /spl mu/V offset voltage, 0.2 /spl mu/V//spl deg/C drift with temperature, 0.2 /spl mu/V/month drift with time, and a voltage gain of two million.     

An NMOS comparator for a bubble memory

A low-noise low-offset comparator was designed for a bubble memory system. The measured noise performance was 25 /spl mu/V rms or 13 nV//spl radic/Hz and the worst case offset voltage was determined to be 158 /spl mu/V. This results in a 1.30 mV comparator gray region.     

A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation

A 1.5-V 100-mA capacitor-free CMOS low-dropout regulator (LDO) for system-on-chip applications to reduce board space and external pins is presented. By utilizing damping-factor-control frequency compensation on the advanced LDO structure, the proposed LDO provides high stability, as well as fast line and load transient responses, even in capacitor-free operation. The proposed LDO has been implemented in a commercial 0.6-/spl mu/m CMOS technology, and the active chip area is 568 /spl mu/m/spl times/541 /spl mu/m. The total error of the output voltage due to line and load variations is less than /spl plusmn/0.25%, and the temperature coefficient is 38 ppm//spl deg/C. Moreover, the output voltage can recover within 2 /spl mu/s for full load-current changes. The power-supply rejection ratio at 1 MHz is -30 dB, and the output noise spectral densities at 100 Hz and 100 kHz are 1.8 and 0.38 /spl mu/V//spl radic/Hz, respectively.     

A CMOS voltage reference based on weighted /spl Delta/V/sub GS/ for CMOS low-dropout linear regulators

A CMOS voltage reference, which is based on the weighted difference of the gate-source voltages of an NMOST and a PMOST operating in saturation region, is presented. The voltage reference is designed for CMOS low-dropout linear regulators and has been implemented in a standard 0.6-/spl mu/m CMOS technology (V/sub thn//spl ap/|V/sub thp/|/spl ap/0.9 V at 0/spl deg/C). The occupied chip area is 0.055 mm/sup 2/. The minimum supply voltage is 1.4 V, and the maximum supply current is 9.7 /spl mu/A. A typical mean uncalibrated temperature coefficient of 36.9 ppm//spl deg/C is achieved, and the typical mean line regulation is /spl plusmn/0.083%/V. The power-supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz are -47 and -20 dB, respectively. Moreover, the measured noise density with a 100-nF filtering capacitor at 100 Hz is 152 nV//spl radic/(Hz) and that at 100 kHz is 1.6 nV//spl radic/(Hz).     

MOS transistors operated in the lateral bipolar mode and their application in CMOS technology

Operation of an MOS transistor as a lateral bipolar is described and analyzed qualitatively. It yields a good bipolar transistor that is fully compatible with any bulk CMOS technology. Experimental results show that high /spl beta/-gain can be achieved and that matching and 1/f noise properties are much better than in MOS operation. Examples of experimental circuits in CMOS technology illustrate the major advantages that this device offers. A multiple current mirror achieves higher accuracy, especially at low currents. An operational transconductance amplifier has an equivalent input noise density below 0.1 /spl mu/V//spl radic/Hz for frequencies as low as 1 Hz and a total current of 10 /spl mu/A. A bandgap reference yields a voltage stable within 3 mV from -40 to +80/spl deg/C after digital adjustment at ambient temperature. Other possible applications are suggested.     

A low-noise high-precision operational amplifier

A low-noise high-precision operational amplifier has recently been fabricated in monolithic form with dielectric isolation. The amplifier exhibits a V/SUB OS/ of 10 /spl mu/V, V/SUB OS/T/SUB c/ of 0.3 /spl mu/V//spl deg/C, voltage gain of 140 dB with a 600 /spl Omega/ load, and an input noise voltage of 9 nV//spl radic/Hz. The settling time to within 0.01 percent of final value is 15 /spl mu/s for a 10 V pulse.     

新型电容式MEMS加速度计数字接口电路设计

MEMS加速度计接口电路主要采用传统sigma-delta架构实现,但这种方式中的电路失调电压很容易产生积分饱和现象．为解决这个问题,本文设计了一种可以用于钻井、石油勘探等微弱信号检测的新型数字电容接口电路．该设计在电容式MEMS加速度传感器基础上,采用FPGA实现数字三阶环路滤波器,构成5阶sigma-delta系统．采用数字环路滤波器降低了ASIC模拟电路版图设计与芯片测试难度,利于快速优化环路滤波器设计参数,改善系统稳定性和优化系统噪声性能．前置放大器采用一种相对简单的相关双采样技术,能够有效减小前置放大器的失调电压．根据MEMS加速度计前置放大器输出信号符合正态分布的特点,设计了带有一定预测功能的8-bit瞬时浮点ADC,实现模拟与数字环路滤波器互联．在200Hz带宽内,该接口电路系统噪声基底达到53．09ng／rt（Hz）,满足系统噪声设计要求．前置放大器与ADC采用XFAB XH018混合信号CMOS工艺流片,开环测试表明,前置放大器的灵敏度和噪声分别为0．69V／pF和3．20μV／rt（Hz）．     

A CMOS chopper amplifier

A highly sensitive CMOS chopper amplifier for low-frequency applications is described. It is realized with a second-order low-pass selective amplifier using a continuous-time filtering technique. The circuit has been integrated in a 3-/spl mu/m p-well CMOS technology. The chopper amplifier DC grain is 38 dB with a 200-Hz bandwidth. The equivalent input noise is 63 nV//spl radic/Hz and free from 1/f noise. The input offset is below 5 /spl mu/V for a tuning error less than 1%. The amplifier consumes only 34 /spl mu/W.     

Design of a low-noise preamplifier for nerve cuff electrode recording

This paper discusses certain important issues involved in the design of a nerve signal preamplifier for implantable neuroprostheses. Since the electroneurogram signal measured from cuff electrodes is typically on the order of 1 /spl mu/V, a very low-noise interface is essential. We present the argument for the use of BiCMOS technology in this application and then describe the design and evaluation of a complete preamplifier fabricated in a 0.8-/spl mu/m double-metal double-poly process. The preamplifier has a nominal voltage gain of 100, a bandwidth of 15 kHz, and a measured equivalent input-referred noise voltage spectral density of 3.3 nV//spl radic/Hz at 1 kHz. The total input-referred rms noise voltage in a bandwidth 1 Hz-10 kHz is 290 nV, the power consumption is 1.3 mW from /spl plusmn/2.5-V power supplies, and the active area is 0.3 mm/sup 2/.     

Simultaneous measurement of temperature and strain based on arc-induced long-period fibre gratings

A study on arc-induced long-period fibre gratings (LPFGs) revealed that their strain sensitivity depends on the electric current of the arc discharge. Based on that property, a sensor scheme comprising two concatenated LPFGs was implemented for discrimination of temperature and strain effects. This sensor presented resolutions of /spl plusmn/0.1/spl deg/C//spl radic/Hz and /spl plusmn/35 /spl mu//spl epsiv///spl radic/Hz, respectively.     

A sigma–delta interface ASIC for force-feedback micromachined capacitive accelerometer

A single-loop fourth-order sigma?Cdelta (????) interface circuit for micromachined accelerometer is presented in this study. Two additional electronic integrators are cascaded with the micromachine sensing element to form a fourth-order loop filter to eliminate quantization noise. A precise model for the overall system is set up based on nonlinear model of 1-bit quantizer. Three main noise sources affecting the overall system resolution of a ???? accelerometer: mechanical noise, electronic noise and quantization noise are analyzed in more detail. A switched-capacitor charge integrator and correlated double sampling are applied to reduce input-referred electronic noise. The ASIC is fabricated in 0.5???m two-metal two-poly n-well CMOS process, and test results show that the noise density floors of the open-loop and closed-loop modes are 12 and 80???g/Hz^1/2, respectively, the sensitivity is 1.25?V/g, the full measurement range can be achieved from ?2 to +2?g, and the power dissipation is 40?mW.