On the loop noise bandwidth of SCCL

SCCL, a new bit tracking loop based on the sample-correlate-choose-largest design principle, was shown to be an effective bit synchronizer. However, the analysis common in analyzing digital phase locked loops, proceeds on the assumption that the noise samples are independent which is not necessarily true in practice. The performance of SCCL, is analyzed without the independence assumption by considering the second-order statistics to complete the analysis. This approach is also useful to analyze other digital phase-locked loops or baseband digital signal processing schemes in digital communication systems     

Bit Synchronization in the Presence of Asymmetric Channel Noise

Bit synchronization in the presence of asymmetric channel noise has not appeared in the open literature. It is the purpose of this paper to study the tracking performance (clock jitter and cycle slip rate) of a popular digital clock synchronizer, the digital data transition tracking loop (DTTL), in the presence of asymmetric noise. Related parameters of interest, the transition density and data asymmetry, are also included. Acquisition performance (frequency acquisition time) is discussed in the absence of noise. A comparison of the DTTL and crossspectrum synchronization loop (CSSL) is also provided. Numerical results are Presented for the design of a bit synchronizer in this environment.     

Variable bandwidth DPLL bit synchronizer with rapid acquisitionimplemented as a finite state machine

A digital PLL bit synchronizer with variable loop bandwidth for rapid acquisition and good tracking performance is proposed, and its performance analyzed using Markov chain techniques. Results are presented for the distributions of acquisition time and time to first bit slip in terms of state transition probabilities. For burst mode data, results for the timing error and bit error rate as a function of the preamble bit number are obtained. All results are evaluated by repeated matrix products and verified by simulation. Comparison of the variable bandwidth DPLL to a fixed bandwidth DPLL shows significantly faster acquisition for a given tracking performance     

Quelques applications des boucles à verrouillage de phase aux problèmes de synchronisation dans les liaisons spatiales

This paper deals with a presentation of carrier and bit synchronizers used for low signal-to-noise ratio space digital communications. Such synchronizers are closed loop phase estimators and carry out a mechanization of the maximum likelihood criterium. The paper presents well known carrier synchronizers such as the decision feedback synchronizer, the Costas loop and the x² non-linearity synchronizer. Bit synchronizers such as the early late gate, the data transition tracking loop and others synchronizers associated with a non-linearity are also introduced.     

Anti-hangup binary quantized DPLL technique for timing recovery inQAM symbol-rate sampled receivers

This paper presents the statistical performance analysis of a decision directed timing recovery scheme based on a digital phase-locked loop (DPLL) that uses binary quantization and employs an adaptive sequential loop filter (LF) devised in order to prevent the adversary hang-up phenomenon. The proposed loop is analyzed by exercising Markovian analytical techniques on a simplified two-dimensional Markov chain approximation. Both the tracking and acquisition performances are examined in cases of M-ary quadrature amplitude modulation input signals. Numerical results, validated further by computer simulations, in essence show that the employed anti-hangup sequential LF speeds up the acquisition process by preventing the synchronizer from excessively long hang-ups. Compared to the classical nonadaptive binary quantized DPLL synchronizer, the loop with the proposed adaptation mechanism gains up to an order of magnitude in response time over the hang-up effect, at a minor cost in its steady-state tracking performance     

Zero-crossing DPLL bit synchronizer with pattern jittercompensation

A digital phase-locked loop (DPLL) bit synchronizer that tracks the zero crossings of a bandlimited binary signal is discussed. The synchronizer reduces pattern jitter or self noise with a compensation signal in the synchronizer feedback loop without using a prefilter. Analytical results are derived for the timing jitter variance (additive noise and self noise) of the synchronizer. Computer simulations and laboratory measurements are shown to verify the effectiveness of the pattern jitter compensation techinque for a synchronizer operating with both spectral raised cosine signaling pulses as well as for signaling pulses generated by a realizable filter network. Implementation of the pattern jitter compensation method in an adaptive synchronizer structure for applications where a priori knowledge of the signaling pulse shape is not available is also discussed     

Étude théorique et expérimentale d’un synchronisateur primaire numérique pour signaux MIC

Bit synchronizers are used in satellite data communications systems to restore the data rate. They provide means to data detection. The paper concerns the theoretical analysis supported by the simulation and the pratical measurements of a digital self bit synchronizer implemented with standart ttl logic. This self bit synchronizer is composed of a non linear element which delivers from the sampled and quantized pcm signal a spectral line at frequency twice the data rate. This spectral line is filtered by a digital phase locked loop and is used to drive a digital matched filter data detector. Theoretical and experimental results show a very small mean acquisition time (about 4 or 5 bit duration) and a degradation lower than 2 dB for snr ranging from +2 dB to +12 dB.     

早迟门同步器跟踪速度的改进方法

本文首先分析了传统早迟门同步器的性能,指出积分区间设置的不同和早迟门积分长短的不同会影响到鉴相曲线的形状,提出了一种改进的积分结构.新的结构使环路送往VCO的控制信号可以较好的随着同步误差的变化而变化.本文根据卡尔曼滤波器[2]在快速跟踪中的优良表现,在新的位同步器中设计了新的环路滤波器.Simulink仿真的结果表明,新的位同步方法较传统的早迟门位同步器有更快的跟踪速度.     

I/Q channel reversal correcting properties of anSQPSK Costas loop with integrated symbol synchronization

An integrated-carrier loop/symbol synchronizer, using a digital Costas loop with matched arm filters to demodulate staggered quaternary phase-shift keyed (QPSK) signals, is analyzed. An expression is derived for the S curve, parameterized by bit synchronization error. This result suggests that the demodulator structure offers an inherent I/Q channel reversal correcting capability. Computer simulation results are presented that support this conclusion, and suggest that ambiguity resolution performance depends on the ratio of carrier and synchronization loop bandwidths     

Analysis of a Digital Bit Synchronizer

A simple digital bit synchronizer utilizing discrete phase control is discussed. The proposed system is intended for operation with NRZ coded binary signals. A finite state Markov chain model is used to evaluate the steady-state phase jitter performance of the bit synchronizer in the presence of additive white Gaussian noise. The theoretical results are confirmed by computer simulation. The same mathematical model is used to investigate the transient (acquisition) performance of the synchronizer. Finally, the performance of the synchronizer as a data detector is discussed and the error probability performance is compared with that of the optimum detector.     

Symbol synchronization in digital communication systems usingpartial response CPM signaling

The applicability of standard symbol synchronization schemes in digital communication systems using partial-response CPM (continuous phase modulation) signaling has been analyzed. Using the theory of maximum a posteriori estimation of the unknown parameter in Gaussian noise, a theoretical structure for the optimum symbol synchronizer in a system using partial-response CPM signaling is derived. As the first approximation, a closed-loop configuration, known as the early-late loop, is derived and discussed. Due to signal correlation in adjacent symbol time intervals, even this configuration is impractical for a hardware realization. For these reasons, different approximations of the general maximum-likelihood function, leading to the discrete bit timing loop realizations, are derived and discussed. The influence of the carrier phase synchronization error on these synchronizers is also discussed     

A digital approach to clock recovery in generalized minimum shiftkeying

A method for clock recovery to be used with generalized minimum-shift-keying (MSK) modulations is presented. Attractive features of the method are that it is suited for digital implementation and that its performance is not affected by the carrier-phase recovery process. Clock reference is extracted by passing the sampled baseband waveform through the cascade of a nonlinearity, followed by a digital differentiator whose average output represents the error signal to be employed in a tracking loop. The performance of this scheme is analyzed by means of simulation in steady-state and in transient conditions. Tracking errors are compared with those attained by the well-known De Buda synchronizer and with the Cramer-Rao lower bound     

A 622-Mb/s bit/frame synchronizer for high-speed backplane datacommunication

A compact 622-Mb/s/port bit/frame synchronizer is presented. Sampling equally-phased clocks from a phase-locked loop (PLL) at the data transition edges, the bit synchronizer selects the optimum one as the extracted clock. An elastic serial-to-parallel converter is used for the frame synchronization. The circuit is designed for a 32-port ATM switch chip, achieving 622-Mb/s port capacity by four parallel 156-Mb/s bits. Using 0.5-μm CMOS technology, the circuit was verified by simulations. The bit synchronizer consumes only 15 mW under typical conditions     

一种大频偏和低信噪比条件下的全数字锁相环设计

全数字锁相环设计是相干解调全数字接收机载波同步和位同步的关键技术,而大频偏和低信噪比分别从两个方面增加了环路设计的难度.该文在此背景下,以捕获时间和跟踪性能为指标,从模拟环路分析出发,给出一种适用于大频偏和低信噪比条件的全数字锁相环设计.     

大动态PCM/FM信号的载波频率同步

针对大动态脉冲编码-频率调制(PCM/FM)遥测信号的载波频率同步,提出了基于快速傅里叶变换(FFT)及频谱重心的载波频率估计方法,并采用了频谱叠加及频谱截取的优化方法提高算法估计精度.相对于其他基于FFT的频率估计算法,频谱重心法有着更高的估计精度及更好的抗噪声性能,而且复杂度代价很小.仿真的均方误差结果表明,基于FFT长度为2048和2块叠加以及保留信号99.9%能量的频谱截取方案有最好的估计性能.在最大多普勒频率、多普勒一阶变化率及二阶变化率分别为0.5倍、0.3倍及0.2倍符号率的大动态条件下,基于频谱重心法的二阶锁频环能够较好地完成载波频率跟踪.误码率曲线表明,经过频偏校正后的多符号非相干解调(MSD)性能与无频偏情况相比,无性能损失.     

Timing Recovery in the Presence of a Residual Echo Signal

This paper deals with the problem of symbol timing recovery at the subscriber end of a full duplex two wire digital subscriber loop employing echo cancellation. Both nondecision-aided and decisionaided synchronization are considered. It is demonstrated that the presence of a residual echo signal can substantially degrade the synchronizer performance. This degradation is shown to be larger for nondecisionaided synchronizers than for decision-aided synchronizers. The smaller the synchronizer bandwidth and the signal-to-echo ratio, the more the decision-aided synchronizer outperforms the nondecision-aided synchronizer.     

Threshold reduction for demodulating a BPSK suppressed-carrier signal (Corresp.)

If a Costas loop is forced to have a relatively wide bandwidth, for example, to track phase variation due to platform motion, binary phase-shift keying (BPSK) demodulator performance is significantly degraded. However, if the data bits were known, the Costas loop would become equivalent to a phase-locked loop, which has approximately a 6-dB lower tracking threshold for the same loop bandwidth. A delayed-bit estimation algorithm with a recursive structure similar to the Viterbi algorithm is described. The memory in the tracking loop is exploited to correct preliminary bit decisions, as a means of realizing most of this theoretical threshold reduction. Experimental results for a practical digital implementation of the new algorithm for a 50-bit/s data rate and a 20-Hz loop noise bandwidth show a 4-dB improvement in demodulator threshold.     

A bit error probability analysis of a digital PLL based demodulatorof differentially encoded BPSK and QPSK modulation

Presents a bit error probability analysis of a digital phase-locked loop based demodulator, of differentially encoded BPSK and QPSK modulations. Differential decoding is a method of resolving a phase ambiguity, typical of fully modulated signals, that uses two consecutive demodulated symbols to estimate the information symbols. The effects of a noisy phase reference on demodulator performance are well documented for uncoded modulations (single symbol demodulation). The paper investigates performance for phase reference time variations between the two symbols. The time varying reference investigated is produced by a digital phase-locked loop. The noisy phase reference has negligible additional effect on the bit error probability for differentially encoded BPSK and QPSK     

The Minimum Likelihood--A New Concept for Bit Synchronization

A new bit synchronization concept based on the "minimum likelihood" criterion instead of the conventional "maximum likelihood" concept is developed. The minimum likelihood situation is even easier to reach than the maximum likelihood because the derivative of the log likelihood function becomes identically zero there. Minimum likelihood implies "least likely" for synchronization (the worst case synchronization error) or an "orthogonal" timing condition which simply means that the locally generated clock is synchronized correctly, but with a delay of a half bit period. The structure and performance of the minimum likelihood bit synchronizer are discussed in detail in this paper. The results indicate that the minimum likelihood bit synchronizer has a much simpler structure, but with performance very close to the optimal maximum likelihood synchronizer.     

An all-digital low-power IF GPS synchronizer

An all-digital intermediate frequency (IF) Global Positioning System (GPS) synchronizer for employment in portable electronic applications is presented. The chip performs code and carrier synchronization, decodes received data, and provides pseudorange estimates. To reduce the average power dissipation, the whole receiver is powered down and reactivated only when it needs to update its position estimate. With a lower duty cycle, the receiver spends more time in the power-down mode and the power consumption of the whole receiver is proportionately reduced. The synchronizer is therefore designed to minimize re-acquisition time between position readings. When powered up, the synchronizer searches in parallel over a window of timing uncertainty, then employs near-optimal tracking with a variable loop gain filter. With SNR=-20 dB, phase shift rate of 1 chip/s, and user velocity of 30 m/s, the synchronizer chip dissipates under 4 mW for pseudorange estimate rms error of under 7 m