Automatic Target Recognition with Dynamic Reconfiguration

This paper describes the acceleration of an infrared automatic target recognition (IR ATR) application with a co-processor board that contains multiple field programmable gate array (FPGA) chips. Template and pixel level parallelism is exploited in an FPGA design for the bottleneck portion of the application. The implementation of this design achieved a speedup of 21 compared to running on the host processor. The paper then describes an FPGA resource manager (RM) developed to support concurrent applications sharing the FPGA board. With the RM, the system is dynamically reconfigurable. That is, while part of the co-processor board is busy computing, another part can be reconfigured for other purposes. The IR ATR application was ported to work with the RM and has been shown to adapt to the amount of reconfigurable hardware that is available at the time the application is executed.     

Programmable interconnects speed system verification

A family of CMOS integrated circuits called field programmable interconnect components (FPICs) that can provide designers with the high-density interconnect architectures for making programmable hardware a reality is discussed. The FPIC devices address a broad spectrum of interconnect needs, including system prototypes and breadboards, user-specific/configurable printed circuit boards (PCBs), application configurable processors, test interfaces, and programmable connector and switching matrix applications. Using FPIC devices for system prototyping, in conjunction with other programmable components (programmable logic devices (PLDs), field programmable gate arrays (FPGAs), microprocessors, microcontrollers, DSP, and programmable memory) enhance the design verification process, allowing faster, more flexible, and thorough product integration. Field programmable circuit boards (FPCBs) designed to take advantage of the high density interconnect and observability of FPIC devices and a FPIC/FPCB development environment are described     

基于二维随机投影特征典型相关分析融合的SAR ATR方法

合成孔径雷达（Synthetic aperture radar,SAR）自动目标识别（Automatic target recognition,ATR）是现代战场情报侦察、精确打击的重要支撑技术。为提升SAR ATR整体性能,提出基于二维投影特征多重集典型相关分析（Multiset canonical correlations analysis,MCCA）的方法。首先,采用若干二维随机投影矩阵对SAR图像进行特征提取,获得多层次特征描述。考虑到这些结果之间的相关性和可能存在的冗余及干扰,进一步通过MCCA对它们进行融合处理,获取单一特征矢量。基于稀疏表示分类器（Sparse representation-based classification,SRC）对融合特征矢量进行处理,判决目标类别。实验基于MSTAR数据集开展,对方法性能进行检验确认,结果能够验证其有效性。     

一种基于中心矩特征的SAR图像目标识别方法

合成孔径雷达自动目标识别是目前国内外模式识别领域的重点研究课题之一.本文给出了一种内存需求小,低计算复杂度且具有较好识别性能的SAR图像目标识别方法,先通过自适应阈值分割来获得目标图像,然后提取其中心矩特征,采用SVM来进行识别.基于美国MSTAR实测数据的识别试验验证了该方法的有效性.     

Target-Centered Models and Information-Theoretic Segmentation for Automatic Target Recognition

We present an approach to automatic target recognition (ATR) from synthetic aperture radar (SAR) imagery which combines advantages of both model-based and template-based approaches. Prior observations are used to estimate the statistical properties of reflectance over regions in the training scene. These target-centered statistical models can then be used to estimate the statistical properties of sensor output for arbitrary pose. Two-sided hypothesis tests which are maximally powerful at the most likely alternative are developed in a information-theoretic framework to address target model segmentation and confuser rejection. Segmentation of target from clutter is performed in the target-centered coordinate system using all prior observations to produce a consistent segmentation over all poses. We present performance and computation complexity results as a function of segmentation threshold, confuser-rejection threshold, and operating conditions for publicly available SAR data.     

Reconfigurable Computing for Digital Signal Processing: A Survey

Steady advances in VLSI technology and design tools have extensively expanded the application domain of digital signal processing over the past decade. While application-specific integrated circuits (ASICs) and programmable digital signal processors (PDSPs) remain the implementation mechanisms of choice for many DSP applications, increasingly new system implementations based on reconfigurable computing are being considered. These flexible platforms, which offer the functional efficiency of hardware and the programmability of software, are quickly maturing as the logic capacity of programmable devices follows Moore's Law and advanced automated design techniques become available. As initial reconfigurable technologies have emerged, new academic and commercial efforts have been initiated to support power optimization, cost reduction, and enhanced run-time performance.This paper presents a survey of academic research and commercial development in reconfigurable computing for DSP systems over the past fifteen years. This work is placed in the context of other available DSP implementation media including ASICs and PDSPs to fully document the range of design choices available to system engineers. It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential. While individual implementations of PDSP, ASIC, and reconfigurable resources each offer distinct advantages, it is likely that integrated combinations of these technologies will provide more complete solutions.     

长波红外导引头空间自动目标识别系统（一）

本文给出了一个适合于流水阵列结构信息处理机实时处理的空间红外目标自动识别系统。其特色是采用了边检测、边识别、边跟踪的多目标跟踪技术及目标数据动态维护技术,从而使得系统具有良好的多目标跟踪性能及正确的再捕获被短暂遮档目标的能力。     

DL-assisted programmable multilayer network application awareness system for IP-over-EON

In order to realize real-time and fine-granularity network monitoring and adjustment,and satisfy the specific QoS demands of various applications,a deep learning (DL) assisted programmable multilayer network application performance awareness system for IP-over-EON was proposed.The distributed network monitoring based on network application performance awareness was combined with centralized network management.The multilayer and fine-grained network monitoring was implemented by distributed network monitoring,and the data analysis through DL was performed.Experimental results indicate that by combining distributed and centralized processing seamlessly,the proposed network monitoring system can not only realize timely and automatic network control and management but also provide superior scalability.     

CPLD实现雷达自动增益控制的优化

复杂的可编程逻辑器件可以完成较大规模的组合逻辑电路设计，提高系统的集成化。本文介绍了复杂可编程逻辑器件和电路设计的一般流程，以及数字自动增益控制电路的组成和采用CPLD设计的实现。     

基于扩展分形和CFAR特征融合的SAR图像目标识别

研究了多信息融合技术在SAR图像目标识别中的应用。将扩展分形特征(Extended Fractal)与双参数恒虚警特征(Double Parameter CFAR)形成的多信息进行融合处理。运用Dempster-Shafer证据理论，在决策层对SAR图像中的像素进行识别分类。实验结果表明通过融合对像素分类的准确性明显好于单特征的检测结果，减少了虚警概率，提高了系统的识别能力。     

Design, Debug, Deploy: The Creation of Configurable Computing Applications

Configurable Computing Machines (CCMs) are computing machines based on reconfigurable circuit technology such as field programmable gate-arrays. Early researchers recognized CCMs as a new, flexible, and powerful class of computer. The earliest CCMs featured rudimentary but significant integrated design, debug, and deployment (runtime) environments. This paper reviews those environments and the contributions they made and considers the progress made over the past 20 years in providing support for the “3 D’s” of configurable computing application development: design, debug, and deployment. It then introduces an integrated CAD framework for the creation of CCM CAD tools and describes a series of experiments in creating such a CAD tool suite — the JHDL system. The paper reviews lessons learned from that work and concludes by discussing the role integrated design, debug, and runtime environments will play in future CCM-based systems.     

基于测试系统的FPGA逻辑资源的测试

FPGA在许多领域已经得到广泛应用,其测试问题也显得越来越突出。文章针对基于SRAM结构FPGA的特点,以Xilinx公司的XC4000系列芯片为例,利用检测可编程逻辑资源的多逻辑单元(CLB)混合故障的测试方法,阐述了如何在BC3192V50测试系统上实现FPGA的在线配置以及功能和参数测试。它是一种基于测试系统的通用的FPGA配置和测试方法。     

星载SAR欺骗式干扰信号的实时产生技术研究

为了在电子战系统中对敌方星载合成孔径雷达（SAR）雷达进行有效干扰,文中提出了一种新颖的星载SAR欺骗式干扰信号的实时产生技术。该技术首先通过对分布式大场景的干扰调制函数的离线及分块并行计算,降低了干扰信号产生的复杂度和计算量; 然后,通过实时卷积产生欺骗干扰信号,从而实现对敌方星载SAR系统的实时欺骗干扰的目的; 最后,试验干扰机的测试数据和仿真结果说明了方法的有效性。结果表明：该方法不但可以提供可信赖的干扰效果,而且在实践应用中具有一定的实时性。     

基于隐马尔可夫模型的多孔径SAR目标检测

穿透叶簇的VHF/UHF超宽带(UWB)SAR具有相对带宽很宽,积累角大的特点,可同时获得距离、方位两个方向的高分辨能力,能用于探测叶簇隐蔽的军用车辆等人造目标而有着重要的军事应用价值。在多孔径SAR成像的基础上,本文用隐马尔可夫模型对人造目标和叶簇等杂波建模,可有效地检测目标,实现一个ATR系统的预筛选处理。     

A single-chip programmable platform based on a multithreaded processor and configurable logic clusters

This paper presents a single-chip programmable platform that integrates most of hardware blocks required in the design of embedded system chips. The platform includes a 32-bit multithreaded RISC processor (MT-RISC), configurable logic clusters (CLCs), programmable first-in-first-out (FIFO) memories, control circuitry, and on-chip memories. For rapid thread switch, a multithreaded processor equipped with a hardware thread scheduling unit is adopted, and configurable logics are grouped into clusters for IP-based design. By integrating both the multithreaded processor and the configurable logic on a single chip, high-level language-based designs can be easily accommodated by performing the complex and concurrent functions of a target chip on the multithreaded processor and implementing the external interface functions into the configurable logic clusters. A 64-mm/sup 2/ prototype chip integrating a four-threaded MT-RISC, three CLCs, programmable FIFOs, and 8-kB on-chip memories is fabricated in a 0.35-/spl mu/m CMOS technology with four metal layers, which operates at 100-MHz clock frequency and consumes 370 mW at 3.3-V power supply.     

新型相位式激光测距系统电路的设计

为了提高相位式激光测距系统的精度和可靠性,设计了一种新型的相位式激光测距系统的发射和两路几乎一致的接收电路。通过采用具有微小频差的低抖动时钟发生技术,差频测相技术等原理,系统可以实现特定环境下的高精度测量。系统由级联式PLL可编程时钟信号源、激光发射与接收模块、自动增益控制、混频滤波及数据采集组成。利用时钟源产生调制信号,并对反馈信号和接收信号进行放大、混频滤波等信号调理,进而采集数据并对数据进行处理分析。在电路的设计中,优化了激光的调制发射电路,采用低回波损耗的尾纤式激光器,增加简单实用的自动增益模块等。实验观察的波形和数据结果分析表明,此相位式激光测距系统电路简单实用,并且具有较高的稳定性和较高的测量精度。     

基于DBSCAN技术的SAR图像感兴趣区域鉴别

使用一种新奇的聚类方法从粗略检测后的SAR图像中提取感兴趣区域(ROI),再通过多特征提取和综合鉴别,去除虚警保留目标,为进一步的目标识别做准备。自动目标聚类是基于SAR图像的自动目标识别系统的难点之一,带有噪声的基于密度的聚类方法 (DBSCAN)可以发现任意形状的聚类目标,只依赖于两个不敏感的系统参数,通过区域判断缩减计算时间减少计算内存,很好地适应了自动目标识别的系统需要。多特征目标鉴别方案基于聚类结果,研究聚类得到的感兴趣区域,通过提取多种特征综合判断,有效去除了虚警。所述方法已应用于某SAR-ATR系统,得到了很好的应用体验。     

A New Field Programmable Gate Array: Architecture and Implementation

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a onetime, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below 20 Ω. The chip has been fabricated using a 0.8-μm n-well complementary metal oxide semiconductor technology with two layers of metalization.     

基于高性能数字芯片的多协议可编程接口设计

设计并制作了一种基于SMIC18混合信号工艺,可用于高性能数字芯片中的多协议、可编程输入接口电路.Cadence SPECTRE仿真及测试结果表明,电路可以在多种不同的JEDEC标准协议下工作并自由切换,并加入可控延迟,根据不同协议,电路可以编程选择不同的输入缓冲路径,在同一模块上集成10种JEDEC协议标准.电路同时可以在高至200 MHz的HSTL协议下工作,也可以满足LVTTL等协议的5 V耐压需求.     

The flexibility of configurable computing

There has been growing recent interest in configurable computing, which can be viewed as a hybrid between ASICs and programmable processors. Configurable computing machines are implemented with programmable logic: flexible hardware that can be structured to fit the natural organization and data flow of a computation. The enabling device for configurable computing is the field-programmable array (FPGA). For applications characterized by deeply pipelined, highly parallel, and integer arithmetic processing, configurable computing machines can outperform alternative solutions by up to an order of magnitude. The combination in a single device of dedicated hardware and rapid, submillisecond-scale reprogrammability constitutes an exciting and promising development whose implications are only just beginning to be exploited. We begin with a brief tutorial on FPGAs that describes the most common FPGA architectures and how these architectures are used to support computation, memory access, and data flow. We then present FPGAs as computing machines and focus on devices that are reconfigured during run time. Ongoing research involving FPGAs and future directions are also discussed