Novel approach to design high-performance large-port-count switches in low-index-contrast materials based on cascaded multimode interference couplers

Using a novel design approach, high-performance large-port-count switches based on cascaded multimode interference (MMI) couplers are shown to be feasible in low-index-contrast materials. This approach combines the transfer matrix method, optimization of the MMI dimensions, and mode propagation analysis (MPA) for calculation of phase shifts. 1/spl times/4, 1/spl times/8, 1/spl times/16, and 1/spl times/32 switches are designed, with insertion losses of 1 dB and crosstalk as low as -31.7 dB. Also, it is shown that this approach can balance the losses for different switch states.     

Low-power InP-HEMT switch ICs integrating miniaturized 2/spl times/2 switches for 10-Gb/s systems

This paper presents a wideband cold-FET switch with virtually zero power dissipation. The use of InP HEMTs with a low R/sub on//spl middot/C/sub off/ product enables us to configure a DC-to-over-10-GHz single-pole double-throw (SPDT) switch without using a shunt FET. The series-FET configuration offers a logic-level-independent interface and makes possible positive control voltage operation in spite of using depletion-mode FETs. A miniaturized 2/spl times/2 switch using two SPDT switches yields an insertion loss of less than 1.16 dB and isolation of more than 21.2 dB below 10 GHz, which allows us to increase the scale of the switch in a single chip easily. The add-drop operation combining two 2/spl times/2 switches in a single chip and a 4/spl times/4 switch IC integrating four 2/spl times/2 switches are presented. The packaged ICs achieve error-free operation up to 12.5 Gb/s with either positive or negative logic-level input. Extremely fast switching of /spl sim/140 ps is also successfully demonstrated.     

A DC-4-GHz true logarithmic amplifier: theory and implementation

A 40 dB dynamic range, DC-4 GHz parallel-summation logarithmic amplifier is presented in this paper. The amplifier realizes a piecewise approximation to an exact logarithmic response. A design procedure that yields breakpoints on the exact response is described, along with delay-matching networks for parallel-summation logarithmic amplifiers. The amplifier was constructed in a 35 GHz silicon bipolar process, has /spl plusmn/5 dB logarithmic conformity over a DC-4 GHz bandwidth and has rise and fall times of 100 ps. The integrated circuit has dimensions of 2/spl times/2 mm/sup 2/ and consumes 750 mW from a -5 V supply.     

Lightpath concentrators for all-optical networks

In some deployments of all-optical networks, it is necessary to concentrate the lightpaths from some fibers to fewer fibers. An N/spl times/M lightpath concentrator is an optical component for this purpose, and it concentrates the lightpaths from N incoming fibers to M outgoing fibers. In this paper, three designs of N/spl times/M lightpath concentrators are proposed. The first design is a generalization of optical crossconnects, and it requires M/spl times/M optical switches. The second design incorporates the concept of partial concentration so that it requires only m/spl times/m optical switches (where m相似文献   

High-density digital free-space photonic switches using micro-beam optical interconnections

We describe a compact free-space photonic-switching module that uses micro-beam optical interconnections based on stacked planar optics and exciton absorption reflection switch (EARS) arrays. The switching module has two-dimensional fiber array pigtails and a two-stage, 16-input, 16-output structure (four sets of 4/spl times/4 switches). The microbeam optical interconnections can provide a compact switching module (approximately 30/spl times/90/spl times/22 mm [60 cc]). A relay lens array inserted between stages eliminates beam spreading in the switch and decreases the coupling loss and crosstalk of interconnections. Two-stage switching at a data transmission rate of 4 Mbit/s is demonstrated.     

Broadband hitless bypass switch for integrated photonic circuits

A new microphotonic hitless switch is proposed. By enabling continuous, uninterrupted transition to a bypass path, it permits tuning of wavelength add-drop filters without disturbing intermediate channels. The scheme comprises two symmetrically actuated, 2 /spl times/ 2 /spl Delta//spl beta/-type optical switches, antisymmetrically cascaded in a balanced Mach-Zehnder configuration, and a /spl pi/ differential phase shift in the interferometer arms. By symmetry, it provides for wavelength-independent hitless operation before, during and after switch reconfiguration, permitting slow switching independent of bit rate. Compact implementations using high-index-contrast microelectromechanical-system (MEMS)-actuated switches are proposed.     

A 32-GHz non-uniform distributed amplifier in 0.18-/spl mu/m CMOS

This letter presents a fully integrated distributed amplifier in a standard 0.18-/spl mu/m CMOS technology. By employing a nonuniform architecture for the synthetic transmission lines, the proposed distributed amplifier exhibits enhanced performance in terms of gain and bandwidth. Drawing a dc current of 45mA from a 2.2-V supply voltage, the fabricated circuit exhibits 9.5-dB pass-band gain with a bandwidth of 32GHz while maintaining good input and output return losses over the entire frequency band. With a compact layout technique, the chip size of the distributed amplifier including the testing pads is 940/spl times/860/spl mu/m/sup 2/.     

1/spl times/2 and 1/spl times/4 electrooptic switches

We describe the design, fabrication, and testing of two packaged electrooptic switches built from poled LiTaO/sub 3/ crystals. The 1/spl times/2 switch requires a driving voltage of 1200 V and exhibits insertion loss of 2.4 dB and crosstalk of -39.2 dB; the 1/spl times/4 switch exhibits insertion loss and crosstalk of 2.8 dB and -40.6 dB, respectively, and operates using a 1100-V voltage source. The maximum deflection time between the channels is 86 ns.     

Active vertical-coupler-based optical crosspoint switch matrix for optical packet-switching applications

Packet-switching characteristics are optimized across an integrated 4 /spl times/ 4 optical crosspoint switch matrix consisting of active vertical-coupler-based switch cells. Optical gain difference between the shortest and the longest paths less than 3 dB is demonstrated. Bit error rate (BER) and power penalty measurements during packet routing have also been carried out over the entire 4 /spl times/ 4 matrix. At a 10-Gb/s packet data rate, a less than 1-dB power penalty is observed across the switch matrix, and the possibility for error-free packet routing is demonstrated with no BER floor observed.     

Optical packet switching and buffering by using all-optical signal processing methods

We present a 1 /spl times/ 2 all-optical packet switch. All the processing of the header information is carried out in the optical domain. The optical headers are recognized by employing the two-pulse correlation principle in a semiconductor laser amplifier in loop optical mirror (SLALOM) configuration. The processed header information is stored in an optical flip-flop memory that is based on a symmetric configuration of two coupled lasers. The optical flip-flop memory drives a wavelength routing switch that is based on cross-gain modulation in a semiconductor optical amplifier. We also present an alternative optical packet routing concept that can be used for all-optical buffering of data packets. In this case, an optical threshold function that is based on a asymmetric configuration of two coupled lasers is used to drive a wavelength routing switch. Experimental results are presented for both the 1 /spl times/ 2 optical packet switch and the optical buffer switch.     

Fabrication of semiconductor optical switch module using laser welding technique

The 4/spl times/4, 1/spl times/2, and 1/spl times/4 semiconductor optic-switch modules for 1550 nm optical communication systems were fabricated by using the laser welding technique based on the 30-pin butterfly package. For better coupling efficiency between a switch chip and an optical fiber, tapered fibers of 10-15 /spl mu/m lens radius were used to provide the coupling efficiency up to 60%. The lens to lens distance of the assembled tapered fiber array was controlled within /spl plusmn/1.0 /spl mu/m. A laser hammering technique was introduced to adjust the radial shift, which was critical to obtain comparable optical coupling efficiencies from all the channels at the same time. The fabricated optical switch modules showed good thermal stability, with less than 5% degradation after a 200 thermal cycling. The transmission characteristics of the 4/spl times/4 switch module showed good sensitivities, providing error free transmissions below -30 dBm for all the switching paths. The dynamic ranges for the 4/spl times/4 and 1/spl times/2 switch modules were about 8 dB for a 3 dB penalty and about 17 dB for a 2 dB penalty, respectively.     

A high dynamic range current-mode amplifier for computed tomography

In this paper, we show a high dynamic range current-mode detector for computed tomography application. A regulated current mirror structure has been implemented at pixel level that provides with 17 bits dynamic range and a noise floor below 3 pARMS. Nonlinearity is kept below 2% and signal bandwidth is higher than 10 kHz. A test structure with 4/spl times/4 pixel array is presented is this paper. Both photodiode and current mode amplifier have been integrated into the same CMOS standard process.     

Rearrangeable nonblocking SOI waveguide thermooptic 4/spl times/4 switch matrix with low insertion loss and fast response

A rearrangeable nonblocking 4/spl times/4 thermooptic silicon-on-insulator waveguide switch matrix at 1.55-/spl mu/m integrated spot size converters is designed and fabricated for the first time. The insertion losses and polarization-dependent losses of the four channels are less than 10 and 0.8 dB, respectively. The extinction ratios are larger than 20 dB. The response times are 4.6 /spl mu/s for rising edge and 1.9 /spl mu/s for falling edge.     

A coplanar CMOS power switch

A 300 V power switch in a high-voltage CMOS technology compatible with a low-voltage MOS/bipolar technology is presented. This circuit can switch positive and negative 150 V pulses with rise and fall times of 100 ns for a 200 pF capacitive load. The switch has a low-voltage input control (/spl plusmn/15 V). Using earth-symmetrical non-overlapping high-voltage pulses as dynamic supply voltages, it is possible to reduce the power dissipation during the switching time considerably in comparison with the power dissipation of power switches, which use static (i.e., constant) supply voltages under the same conditions.     

A high port-count wavelength-selective switch using a large scan-angle, high fill-factor, two-axis MEMS scanner array

We present a high-port-count (scalable to 1 /spl times/ 32) wavelength-selective switch (WSS) using a large scan-angle, high fill-factor, two-axis analog micromirror array in conjunction with a densely packed two-dimensional array of fiber collimators. A partially populated (1 /spl times/ 9) WSS exhibits a fiber-to-fiber insertion loss of 5.57 /spl plusmn/ 1.4 dB and an extinction ratio of 51 /spl plusmn/ 11 dB. The channel spacing is 100 GHz.     

15-GHz fully integrated nMOS switches in a 0.13-/spl mu/m CMOS process

Two fully integrated nMOS switches have been demonstrated at 15 GHz in a 0.13-/spl mu/m CMOS foundry process. One incorporates on-chip LC impedance transformation networks (ITNs) while the second one does not. The switches with and without ITNs achieve the same 1.8-dB insertion loss at 15 GHz, but 21.5 and 15 dBm input P/sub 1dB/, respectively. The degradation of insertion loss due to use of ITNs is compensated by reducing the mismatch loss caused by the bond pad parasitics. The switch without ITNs is suitable for 3.1-10.6 GHz ultra-wide-band (UWB) applications. The switch with ITNs has /spl sim/5 dB worse isolation than the switch without. The difference is due to the larger transistor size of the switch with ITNs, which introduces lower parasitic impedance path between Tx/Rx ports and antenna port.     

Low-loss polarization-insensitive InP-InGaAsP optical space switches for fiber optical communication

High-performance InP-InGaAsP optical space switches are reported, which in monolithic four switch arrangements reach fiber-to-fiber losses as low as 5 dB. Polarization insensitivity is within /spl plusmn/0.5 dB. On-off ratios throughout the 1.53-1.56 /spl mu/m wavelength range exceed 15 dB. Switch rearrangement times are below 200 ps.     

Impact of crosstalk induced beat noise on the size of semiconductor laser amplifier based optical space switch structures

The size limitation of a semiconductor laser amplifier (SLA) based optical matrix-vector multiplier (MVM) switch structure arising from amplifier noise and crosstalk is investigated theoretically and experimentally. Computer simulation reveals that the number of input/output channels in such a switch structure may be limited to less than 60/spl times/60 if the contrast ratio of each SLA is 20 dB or lower.     

Power complexity of multiplexer-based optoelectronic crossbar switches

The integration of thousands of optical input/output (I/O) devices and large electronic crossbar switching elements onto a single optoelectronic integrated circuit (IC) can place stringent power demands on the CMOS substrates. Currently, there is no sufficiently general analytic methodology for power analysis and power reduction of large-scale crossbar switching systems. An analysis of the power complexity of single-chip optoelectronic switches is presented, assuming the classic broadcast-and-select crossbar architecture. The analysis yields the distribution of power dissipation and allows for design optimization. Both unpipelined and pipelined designs are analyzed, and a technique to reduce power dissipation significantly is proposed. The design of a 5.12 Tbit single-chip optoelectronic switch using 0.18-/spl mu/m CMOS technology is illustrated. The pipelined switch design occupies < 70 mm/sup 2/ of CMOS area, and consumes <80 W of power, which compares favorably to the power required in electrical crossbar switches of equivalent capacity.     

A K-band bi-phase modulator MMIC for UWB application

A 24-GHz-band, three-dimensional microwave monolithic integrated circuit (MMIC) bi-phase modulator, that is a combination of an active 0//spl pi/ splitter and a SPDT switch, is proposed and demonstrated. Comparing conventional K-band bi-phase modulators, this modulator is broadband, significantly MMIC compatible, and shrinks its chip area. A fabricated bi-phase modulator exhibits an area of 1.0/spl times/0.7mm/sup 2/ and a 1-dB bandwidth of nearly 10GHz. The SPDT switch is optimized in control-gate's time constant so that a very clear bi-phase modulated waveform can be generated from 1Gbps PN code. The insertion loss and the phase imbalance are 6.4 dB+/-0.6 dB and within 10/spl deg/, respectively, between 22GHz and 32GHz.