电信级核心路由器

华为公司的Quidway Net-Engine 80（简称NE80）以其高度的可靠性、线速的转发性能、完善的Diffserv/QoS机制、丰富的业务处理能力、非常适合Internet骨干网络建设和城域骨干网络(MAN)建设的需要。NE 80采用了目前业界先进的网络处理器技术,实现了2.5G接口的IP/MPLS线速转发,整机处理性能超过72Mpps。高可靠性NE80具备大容量、高端口密度的特性,支持128G的线速无阻塞交换。NE80采用全分布式快速转发处理引擎,实现IP/MPLS线速转发,整机满配置提供16个通用I/O槽位的线路处理单元,每块I/O槽位线路处理单元提供2.5G线速转…     

基于System V消息队列的I/O多路复用方法

<正>传统上通过采用select或poll等系统调用可以实现多个TCP网络连接的I/O复用，但该方式并不支持基于SystemV消息队列的报文传输。有名管道技术FIFO的描述符与Socket的描述符相类似，可以被select系统调用支持，因此可借助FIFO设计一种方法，达到对System V消息队列进行I/O复用的目的。方法中设计地从消息队列接收报文的处理流程，在不降低处理性能的前提下，有效解决了有名管道和消息队列的操作不是原子操作带来的不一致问题，实现单一网络通信线程可以同时处理来自网络连接和System V消息队列的报文。     

可重构路由器报文转发引擎设计与实现

网络处理功能的时空演化特性要求可重构路由器报文转发引擎除具有基本报文分组交换能力外,还应具有可重构能力。针对上述需求,构建了面向可重构路由器的报文转发引擎构件重构模型,并基于Pass-Through模式设计实现了可重构FPGA器件与网络处理器相结合的程序/电路构件运行环境。系统实现与应用测试结果表明,可重构路由器报文转发引擎在保证高吞吐率、低延迟的报文转发处理性能的同时,可有效支撑多样化业务构件灵活重构与映射。     

一种自适应多核处理器I/O一致性处理方法

 I/O引发的数据一致性问题是多处理器系统数据一致性问题不容忽视的重要因素.多核使得处理器中的I/O一致性问题变得更加突出.另一方面,I/O访问模式的多样性使得单一的I/O一致性处理方法很难满足多样的I/O应用需求.本文首先分析了I/O应用访问模式,提出了I/O数据访问的七种特性;并根据I/O数据的访问特性提出了一种新型的自适应多核处理器I/O一致性处理方法,使得I/O一致性处理可以自适应地根据I/O应用进行动态调整,从而满足不同应用需求;最后,我们对自适应的I/O一致性处理方法进行了性能评测,评测结果表明该方法对不同的I/O应用均能获得很好性能.     

一种支持事务内I/O操作的事务存储系统结构

本文提出了一种支持事务内I/O操作的硬件事务存储系统结构.该系统基于多核处理器结构和已有的cache一致性机制,通过增加事务缓冲区和相关硬软件,实现对事务的支持.事务内I/O操作的实现基于事务提交锁的部分提交以及事务线程的阻塞/唤醒机制,解决了事务内I/O操作所面临的回滚、事务迁移和缓冲区溢出等问题.系统在模拟器中实现,并利用5个测试程序对系统的性能进行了评价分析,结果表明事务程序在系统中的性能相对于锁程序得到提升.     

基于网络处理器的路由器体系结构

从路由器的体系结构出发,对通信处理器和网络处理器实现报文处理作了比较。最后对网络处理器转发引擎作了详细的分析。     

面向多核处理器的Linux网络报文缓冲区重用机制研究

提出一种多核架构下Linux网络报文缓冲区重用无锁算法.通过建立Linux网络转发模型,分析了Linux网络报文缓冲区重用机制的工作原理,指出其在多核处理器上扩展性不好的主要原因在于:互斥机制占用了较多的处理时间,较差的Cache行为特征降低了指令执行效率.设计并实现了MSRQ回收重用算法,实现无需互斥机制对重用队列的并行操作,并且具有更好的Cache行为特征.实验证明,MSRQ算法的小包转发性能比原有的缓冲区重用算法提高了67%.     

NI公司新一代M系列数据采集产品设定新标准

题为“NIDays　2004”的全球虚拟仪器技术大会近日在北京召开。会议期间,美国国家仪器有限公司推出新一代M系列数据采集产品。该系列产品基于全新的NI-STC2 系统定时控制器芯片、NI-PGIA2放大器技术和NI-Mcal技术,增加了多项功能和特性。在测量精度、采样速率和I/O通道数等方面取得了新的突破。 NI-STC2能控制系统的定时、同步以及所有输入/输出数据采集操作的数据路由功能。全新M系列数据采集设备包含板载直接内存访问(DMA)通道。应用该通道,数据采集设备上的数据可不经过处理器直接传送到PC。DMA 传输方式能高速传送数据并运讯空闲的处理器同时处理其他的任务。 新一代 M 系列数据采集设备拥有6 个 DMA 通道,采用NI-STC2 系统和定时控制器技术,单个设备可同时执行模拟输入/输出、数字输入/输出和两个计数器/定时器操作,并且这些操作不占用处理器,从而可以解放处理器,以便令其执行其他任务如数据换算和分析。具有NI-STC2 的 M 系列数据采集设备可同时高速执行6个操作,并能最大限度地防止潜在的数据丢失或内存溢出错误。 该系列设备还包含32个硬件定时数字I/O通路,它们的数字波形输...     

基于网络处理器的路由器体系结构

目前许多半导体厂商开始销售一种称为网络处理器的芯片。网络处理器和通用微处理器很相似，但在报文处理能力方面作了优化，从而特点适合于网络通信设备。文章从路由器的体系结构出发，对传统通用处理器和网络处理器实现报文处理的方法进行了比较，最后对网络处理器转发引擎作了详细的分析。     

支持I/O总线高速运行的HyPerTransPort技术

传统的单端I/O总线方案似乎已经走到了它的尽头,不再能满足快速处理器和先进I/O器件的要求.     

基于CN56xx网络处理器的网络控制器的研究

在网络处理器的平台上开发了用户管理控制系统,用于对用户上网内容和行为进行监控。网络处理器是可编程的高效网络数据处理芯片,网络控制器是用户管控系统中用于过滤数据的器件。通过实验,在硬件方面使用优化流水线这一高效的芯片处理数据的方法来提升数据处理效率,在软件方面通过使用不同的算法来优化性能,这些算法包括流过滤算法、潜在语义索引算法和IP碎片处理技术。实验结果表明,基于网络处理器的网络控制器在根据过滤和转发规则对数据过滤和转发时准确率高,速度快,非常好地达到了对用户上网内容和行为监控的效果。     

数字视频系统前端包处理器的设计与仿真

在MPEG-2和DVB标准的基础上,通过对TS包格式及流信息分析,提出一种可行的数字视频系统前端包处理器的设计方案。该方案兼容DVB标准,可将IP数据流转换为TS流在MPEG-2层传送,并可按用户设定提高码流流速,进行节目筛选 ,其中对于PCR抖动的消除提出新的两次修正法,适用于多节目及单节目流并便于硬件实现,同时对于IP数据的处理也提出一种建立新IP-TS流以取代在原TS流复用节目的新思路和方法。本设计方案简单易行,性能满足系统要求,仿真生成数据的播放效果与原数据无差别。     

Control-on-demand: an efficient approach to router programmability

Control-on-demand is a paradigm for network programmability at the network transport level. Prior work on active and programmable networking at this level either achieves flexibility by inserting significant software in the critical path of forwarding or achieves efficiency by sacrificing functionality and relegating programmability to connection management. In contrast, control-on-demand acts both in the control plane and in the data plane, still without adding software in the critical forwarding path. Rather than applying essential programs to every datagram, our approach is to apply the installed service logic asynchronously from data forwarding. This way we avoid essential processing in the critical forwarding path, applying the (user) installed service logic for service enhancement only. In this paper, we describe control-on-demand and how its service model provides sufficient richness to act in the data path. Set is restrictive enough to avoid the significant performance overhead of other in-data path approaches. The expressiveness of the programmable model is limited to observing and suggesting to the forwarding engine, but is never essential for correct processing, thus significantly reducing security and robustness concerns. Consequently, control-on-demand is efficient enough to make it viable for elementary services. Rather than replacing the interoperability layer, control-on-demand represents an evolution of router (switch) control functionality. As the required modification of router forwarding engines is insignificant, control-on-demand is viable in practice in the near future. These concepts have been prototyped as part of the Pronto Control Platform. In this paper, we describe our IPv6 router prototype implementation and discuss the application of control-on-demand on a number of interesting problems     

Analysis of Forwarding Mechanisms on Fine-Grain Gradient Sinking Model in WSN

The communication efficiency of large-scale WSNs with high node density is highly related with specific forwarding strategy in complicated wireless environments. Thus, it is the key problem that how to use the characteristic of high-density to select appropriate forwarding nodes to relieve the load imbalance and improve the communication efficiency. In this paper, we first propose a Fine-grain Gradient Sinking (FGS) model and several data forwarding strategies based on this model. Then we give the criteria of communication efficiency and emphatically analyze the communication efficiency of various forwarding strategies. Simulation results show that forwarding strategies under FGS model can achieve higher communication efficiency, and the efficiency can be further elevated by introducing the statistics of packet receive rate during the forwarding process.

Efficient user-space protocol implementations with QoS guaranteesusing real-time upcalls

Two important requirements for protocol implementations to be able to provide quality of service (QoS) guarantees within the endsystem are: (1) efficient processor scheduling for application and protocol processing and (2) efficient mechanisms for data movement. Scheduling is needed to guarantee that the application and protocol tasks involved in processing each stream execute in a timely manner and obtain their required share of the CPU. We have designed and implemented an operating system (OS) mechanism called the real-time upcall (RTU) to provide such guarantees to applications. The RTU mechanism provides a simple real-time concurrency model and has minimal overheads for concurrency control and context switching compared to thread-based approaches. To demonstrate its efficacy, we have built RTU-based transmission control protocol (TCP) and user datagram protocol (UDP) protocol implementations that combine high efficiency with guaranteed performance. For efficient data movement, we have implemented a number of techniques such as: (1) direct movement of data between the application and the network adapter; (2) batching of input-output (I/O) operations to reduce context switches; and (3) header-data splitting at the receiver to keep bulk data page aligned. Our RTU-based user-space TCP/Internet protocol (TCP/IP) implementation provides bandwidth guarantees for bulk data connections even with real-time and “best-effort” load competing for CPU on the endsystem. Maximum achievable throughput is higher than the NetBSD kernel implementation due to efficient data movement. Sporadic and small messages with low delay requirements are also supported using reactive RTUs that are scheduled with very low delay. We believe that ours is the first solution that combines good data path performance with application-level bandwidth and delay guarantees for standard protocols and OSs     

Real-Time 3-D Ultrasound Scan Conversion Using a Multicore Processor

Real-time 3-D ultrasound scan conversion (SC) in software has not been practical due to its high computation and I/O data handling requirements. In this paper, we describe software-based 3-D SC with high volume rates using a multicore processor, Cell. We have implemented both 3-D SC approaches: 1) the separable 3-D SC where two 2-D coordinate transformations in orthogonal planes are performed in sequence and 2) the direct 3-D SC where the coordinate transformation is directly handled in 3-D. One Cell processor can scan-convert a $192 times 192 times 192$ 16-bit volume at 87.8 volumes/s with the separable 3-D SC algorithm and 28 volumes/s with the direct 3-D SC algorithm.      

High speed IP address lookup architecture using hashing

One of the most important design issues for IP routers responsible for datagram forwarding in computer networks is the route-lookup mechanism. In this letter, we explore a practical IP address lookup scheme which converts the longest prefix matching problem into the exact matching problem. In the proposed architecture, the forwarding table is composed of multiple SRAM, and each SRAM represents an address lookup table in a single prefix. Hashing functions are applied to each address lookup table in order to find out matching entries in parallel, and the entry matched with the longest prefix among them is selected. Simulation using data from the MAE-WEST router shows that a large routing table with 37000 entries is compacted to a forwarding table of 189 kbytes in the proposed scheme and achieves one route lookup every two memory accesses in average.     

提高蜂窝网络中数据分发效率的D2D协作转发算法

Device-to-Device(D2D)通信是一种移动终端在蜂窝通信系统的控制下使用授权频段进行点到点通信的新型技术。通过允许接收终端间的数据转发,D2D通信可以用来提高蜂窝网络中的数据分发效率。现有的终端间转发算法,没有充分考虑D2D链路的差异,很难实现频谱资源的高效利用。为此,该文提出了一种基于多跳中继的D2D协作转发算法,包括多播和单播两个模式。该算法根据D2D链路质量自适应地选择最优的中继、路由及传输跳数,能够充分利用D2D链路的多信道分集增益。仿真结果表明,该文所提出的算法能够显著地提高D2D转发的资源利用率,进而提升数据分发业务的吞吐量。     

The interface processor for the Intel VLSI 432 32-bit computer

The Intel 43203 interface processor is designed to link conventional I/O subsystems and Intel's new 32-bit computer system, the iAPX432. The interface processor is an excellent example of how high density VLSI technology can be combined with innovative circuits to create highly functional systems on a single chip. This paper describes the function of the interface processor and some of the details of its implementation.     

一种信号处理机的高速I／O接口结构

本文介绍了一种以TMS320C25为核心的信号处理机的高速I/O接口.在数据流图分析的基础上,讨论了高速I/O接口的功能与性能要求,重点分析了I/O接口的硬件结构及其功能的实现原理,该I/O接口可以与PC机配合构成独立的、通用的数据采集处理与分析系统.