An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write

This paper describes a 4-Mb embedded DRAM macro using novel fast random cycle architecture with sense-synchronized read/write (SSR/SSW). The test chip has been fabricated with a 0.15-/spl mu/m logic-based embedded DRAM process and the 1.5-V 143-MHz no-wait row random access operation has been confirmed. Data retention power is suppressed to 92 /spl mu/W owing to the hierarchical power supply and SSR. The macro size is 4.59 mm/sup 2/. The cell occupation ratio of the macro is 46%, which is the same as that of a conventional embedded DRAM macro. The macro size and the data retention power are 30% and 4.6%, respectively, of a 4-Mb embedded SRAM macro fabricated by an identical process.     

An 8-ns random cycle embedded RAM macro with dual-port interleavedDRAM architecture (D2RAM)

A novel fast random cycle embedded RAM macro with dual-port interleaved DRAM architecture (D²RAM) has been developed. The macro exploits three key circuit techniques: dual-port interleaved DRAM architecture, two-stage pipelined circuit operation, and write before sensing. Random cycle time of 8 ns under worst-case conditions has been confirmed with a 0.25-μm embedded DRAM test chip. This is six times faster than conventional DRAM     

A 50-/spl mu/A standby 1M/spl times/1/256K/spl times/4 CMOS DRAM with high-speed sense amplifier

A 1M word/spl times/1-bit/256K word/spl times/4-bit CMOS DRAM with a test mode is described. The use of an improved sense amplifier for the half-V/SUB CC/ sensing scheme and a novel half-V/SUB CC/ voltage generator have yielded a 56-ns row access time and a 50-/spl mu/A standby current at typical conditions. High /spl alpha/-particle immunity has been achieved by optimizing the impurity profile under the bit line, based on a triple-layer polysilicon n-well CMOS technology. The RAM, measuring 4.4/spl times/12.32 mm/SUP 2/, is fit to standard 300-mil plastic packages.     

A circuit design of intelligent cache DRAM with automaticwrite-back capability

An intelligent cache based on a distributed architecture that consists of a hierarchy of three memory sections-DRAM (dynamic RAM), SRAM (static RAM), and CAM (content addressable memory) as an on-chip tag-is reported. The test device of the memory core is fabricated in a 0.6 μm double-metal CMOS standard DRAM process, and the CAM matrix and control logic are embedded in the array. The array architecture can be applied to 16-Mb DRAM with less than 12% of the chip overhead. In addition to the tag, the array embedded CAM matrix supports a write-back function that provides a short read/write cycle time. The cache DRAM also has pin compatibility with address nonmultiplexed memories. By achieving a reasonable hit ratio (90%), this cache DRAM provides a high-performance intelligent main memory with a 12 ns(hit)/34 ns(average) cycle time and 55 mA (at 25 MHz) operating current     

A Submicrometer Megabit DRAM Process Technology Using Trench Capacitors

This paper describes guidelines for developing a 1-4-Mbit DRAM process, and device/process technologies for fabricating an experimental 1-Mbit DRAM. A single transistor cell combined with a trench capacitor and on-chip ECC technologies has the potential to realize a cell size of 10 /spl mu/m/sup 2/ without degrading soft error immunity. A depletion trench capacitor, submicrometer n-well CMOS process, Mo-poly gate, and sub-micrometer pattern formation technologies are developed, and an experimental 1-Mbit DRAM with a cell size of 20 /spl mu/m/sup 2/ is successfully developed by using these technologies.     

A 0.18-/spl mu/m RF SiGe BiCMOS technology with collector-epi-free double-poly self-aligned HBTs

This paper describes an RF SiGe BiCMOS technology based on a standard 0.18-/spl mu/m CMOS process. This technology has the following key points: 1) A double-poly self-aligned SiGe-HBT is produced by adding a four-mask process to the CMOS process flow-this HBT has an SiGe epitaxial base selectively grown on an epi-free collector; 2) two-step annealing of CMOS source/drain/gate activation is utilized to solve the thermal budget tradeoff between SiGe-HBTs and CMOS; and 3) a robust Ge profile design is studied to improve the thermal stability of the SiGe-base/Si-collector junction. This process yields 73-GHz f/sub T/, 61-GHz f/sub max/ SiGe HBTs without compromising 0.18-/spl mu/m p/sup +//n/sup +/ dual-gate CMOS characteristics.     

A 60-ns 4-Mbit CMOS DRAM with built-in selftest function

A 4-Mb CMOS DRAM measuring 6.9/spl times/16.11 mm/SUP 2/ has been fabricated using a 0.9-/spl mu/m twin-tub CMOS, triple-poly, single-metal process technology. N-channel depletion-type trench cells, 2.5/spl times/5.5 /spl mu/m/SUP 2/ each, are incorporated in a p-well. A novel built-in selftest (BIST) function which enables a simultaneous and automatic test of all the memory devices on a board is introduced to reduce the RAM testing time in a system. This function is effective for system maintenance and a daily start-up test even in a relatively small system. A high-speed low-power 4-Mb CMOS DRAM with 60-ns access time, 50-mA active current, and 200-/spl mu/A standby current is realized by widening the DQ line bus which connects the sense amplifiers with DQ buffers, thereby reducing the parasitic capacitance of the DQ lines.     

DRAM macros for ASIC chips

DRAM macros in 4-Mb (0.8-μm) and 16-Mb (0.5-μm) DRAM process technology generations have been developed for CMOS ASIC applications. The macros use the same area efficient one transistor trench cells as 4-Mb (SPT cell) and 16-R Mb (MINT cell) DRAM products. It is shown that the trench cells with capacitor plates by the grounded substrate are ideal structures as embedded DRAM's. The trench cells built entirely under the silicon surface allow cost effective DRAM and CMOS logic merged process technologies. In the 0.8-μm rule, the DRAM macro has a 32-K×9-b configuration in a silicon area of 1.7×5.0 mm² . It achieves a 27-ns access and a 50-ns cycle times. The other DRAM macro in the 0.5-μm technology is organized in 64 K×18 b. It has a macro area of 2.1×4.9 mm and demonstrated a 23-ns access and a 40-ns cycle times. Small densities and multiple bit data configurations provide a flexibility to ASIC designs and a wide variety of application capabilities. Multiple uses of the DRAM macros bring significant performance leverages to ASIC chips because of the wide data bus and the fast access and cycle times. A data rate more than 1.3 Gb/s is possible by a single chip. Some examples of actual DRAM macro embedded ASIC chips are shown     

1.0-/spl mu/m n-Well CMOS/Bipolar Technology

High-performance 1.0-/spl mu/m n-well CMOS/bipolar on-chip technology was developed. For process simplicity, an n-well and a collector of bipolar transistors were formed simultaneously, and base and NMOS channel regions were also made simultaneously resulting in collector-isolated vertical n-p-n bipolar transistor fabrication without any additional process step to CMOS process. On the other hand, 1.0-/spl mu/m CMOS with a new "hot carrier resistant" seIf-defined Polysilicon sidewall spacer (SEPOS) LDD NMOS was developed. It can operate safely under supply voltage over 5 V without performance degradation of CMOS circuits. By evaluating ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors. it can be concluded that in a digital and in an analog combined system, CMOS has sufficiently high-speed performance for digital parts, while bipolar is superior for analog parts. In addition, bipolar transistors with an n/sup +/-buried layer were also fabricated to reduce collector resistance. Concerning the bipolar input/output buffers, the patterned n/sup +/-buried layer improves the drivability and high-frequency response. As a result, the applications of n-well CMOS/bipolar technology become clear. This technology was successfully applied to a high-speed 64-kbit CMOS static RAM, and improvement in access time was observed.     

A mixed-signal 0.18-μm CMOS SoC for DVD systems with432-MSample/s PRML read channel and 16-Mb embedded DRAM

This paper describes a fully integrated single-chip CMOS mixed-signal system on a chip (SoC) for DVD RAM and ROM systems. It integrates a 32-b RISC CPU, formatter, servo digital signal processor (DSP), 16-Mb DRAM, error correction code (ECC), ATA interface, and partial-response-maximum-likelihood (PRML) read channel with 7-b interpolated parallel analog-to-digital converter (ADC). Increasing the bus bandwidth by using embedded DRAM, a hardware ECC engine, and four parallel digital finite-impulse response (FIR) filters contributes to the high playback speed of 16×. PR(3,4,4,3) architecture has been used in the read channel system for optical disc systems. The obtained wide tangential tilt margin of ±0.6° is due to the use of this PRML read channel technique. The interpolated parallel scheme has attained a high number of effective bits of 6.3 for 72-Mz input frequency at 432-MSample/s operation without any calibration technique, with low power consumption of 180 mW in a small core size of 1.05 mm². This SoC has been fabricated in 0.18-μm 1PS3AL CMOS embedded DRAM technology. It contains 24 million transistors in a 144-mm ² die and consumes 1.2 W at 432-MSample/s operation. This low power consumption allows the use of a low-cost plastic package. As a result, we can compose highly reliable DVD RAM and ROM systems with this SoC and some tiny components     

A modular architecture for a 6.4-Gbyte/s, 8-Mb DRAM-integratedmedia chip

A modular architecture for a DRAM-integrated, multimedia chip with a data transfer rate of 6 to 12 Gbyte/s is proposed. The architecture offers the design flexibility in terms of both DRAM capacity and the logic-memory interface for use in a wide variety of applications. A DRAM macro built from cascadable DRAM bank modules having a 256-kb memory capacity and 128-b I/Os provides flexibility and reconfigurability of DRAM capacity and a high data transfer rate with an area of 6.4 mm² /Mb. A data transfer circuit (called the “reconfigurable data I/O attachment”), which is attached to the I/O lines of the DRAM macro, provides a flexible logic-memory interface by changing the data-transfer routes between the DRAM macro and logic circuits in real time. A 6.4-Gbyte/s test chip (called the “media chip”) for three-dimensional computer graphics was fabricated to test the proposed design methodology. It integrates an 8-Mb DRAM and four pixel processors on an 8.35×14.6-mm chip by using a 0.4-μm CMOS design rule     

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications

An embedded DRAM macro with a self-adjustable timing control (STC) scheme, a negative edge transmission scheme (NET), and a power-down data retention (PDDR) mode is developed. A 13.98-mm/sup 2/ 16-Mb embedded DRAM macro is fabricated in 0.13 /spl mu/m logic-based embedded DRAM process. Co-salicide word lines and MIM capacitors are used for high-speed array operation. The delay timing variation of 36 % for an RC delay can be reduced to 3.8% by using the STC scheme. The NET scheme transfers array control signals to local array blocks with high accuracy. Thereby, the test chip achieves 1.2-V 312-MHz random cycle operation even in the low-power process. 73-/spl mu/W data retention power is realized by using the PDDR mode, which is 5% of conventional schemes.     

Spotlight on memory: an optically biased, single-ended, three transistor, fully static RAM cell

A single-ended static memory scheme combining advantages of both a one-transistor dynamic RAM (DRAM) cell and a six-transistor static RAM (SRAM) cell is proposed in this article. For the first time, optical bias is introduced, converting the classical complementary metal-oxide semiconductor (CMOS) RAM to an optoelectronic device. The cell structure is highly scalable and cost effective. Various approaches and schemes were applied to combine advantages of static and dynamic RAM memories, striving to shorten access times, lower power dissipation, and decrease cell area. This is particularly true for system-on-a-chip (SoC) and embedded memories. Here, the novel approach towards the same goal is proposed and simulated, introducing standard CMOS technology. A single-ended, three-transistor, fully static RAM cell is demonstrated.     

1.5-V single work-function W/WN/n/sup +/-poly gate CMOS device design with 110-nm buried-channel PMOS for 90-nm vertical-cell DRAM

This letter reports on 1.5-V single work-function W/WN/n/sup +/-poly gate CMOS transistors for high-performance stand-alone dynamic random access memory (DRAM) and low-cost low-leakage embedded DRAM applications. At V/sub dd/ Of 1.5-V and 25/spl deg/C, drive currents of 634 /spl mu/A//spl mu/m for 90-nm L/sub gate/ NMOS and 208 /spl mu/A-/spl mu/m for 110-nm L/sub gate/ buried-channel PMOS are achieved at 25 pA//spl mu/m off-state leakage. Device performance of this single work function technology is comparable to published low leakage 1.5-V dual work-function technologies and 25% better than previously reported 1.8-V single work-function technology. Data illustrating hot-carrier immunity of these devices under high electric fields is also presented. Scalability of single work-function CMOS device design for the 90-nm DRAM generation is demonstrated.     

A 17-ns 4-Mb CMOS DRAM

A 17-ns nonaddress-multiplexed 4-Mb dynamic RAM (DRAM) fabricated with a pure CMOS process is described. The speed limitations of the conventional DRAM sensing technique are discussed, and the advantages of using the direct bit-line sensing technique are explained. A direct bit-line sensing technique with a two-stage amplifier is described. One readout amplifier is composed of a two-stage current-mirror amplifier and a selected readout amplifier is activated by a column decoder output before the selected word line rises. The amplifier then detects a small bit-line signal appearing on a bit-line pair immediately after the word-line rise. This two-stage amplification scheme is essential to improving access time, especially in the case of a CMOS process. The high sensitivity of the readout amplifier is discussed, and the electrical features and characteristics of the fabricated DRAM are reported     

An experimental 1-Mbit cache DRAM with ECC

A cache DRAM which consists of a dynamic RAM (DRAM) as main memory and a static RAM (SRAM) as cache memory is proposed. An error checking and correcting (ECC) scheme utilizing the wide internal data bus is also proposed. It is constructed to be suitable for a four-way set associated cache scheme with more than a 90% hit rate estimated to be obtained. An experimental cache DRAM with 1-Mb DRAM and 8-kb SRAM has been fabricated using a 1.2-μm, triple-polysilicon, single-metal CMOS process. A SRAM access time of 12 ns and a DRAM access time of 80 ns, including an ECC time of 12 ns, have been obtained. Accordingly, an average access time of 20 ns is expected under the condition that the hit rate is 90%. The cache DRAM has a high-speed data mapping capability and high reliability suitable for low-end workstations and personal computers     

New DRAM noise generation under half-Vccprecharge and its reduction using a transposed amplifier

Dynamic RAM (DRAM) data-line interface noise generated during amplification, the key problem in designing 16 Mbit and higher DRAMs, is investigated. It is reported that: (1) in the half-V_cc approach, specific combinations of signal types (high and low) and CMOS sense-amplifier operating sequences cause interference noise during amplification; (2) interference noise exists in sense amplifiers; and (3) the noise results in a detrimental effect on data holding time characteristics. The interference noise is overcome by a transposed amplifier structure combined with a transposed data-line structure     

A miniature 25-GHz 9-dB CMOS cascaded single-stage distributed amplifier

A 25-GHz complementary metal oxide semiconductor (CMOS) cascaded single-stage distributed amplifier (CSSDA) using standard 0.18-/spl mu/m CMOS technology is presented in this letter. It demonstrates the highest gain-bandwidth product (GBP) with smallest chip area reported for a fully-integrated CMOS wideband amplifier using a standard Si-based integrated circuit process. The chip size including testing pads is only 0.36mm/sup 2/, and the ratio of GBP to chip size achieves 552GHz/mm/sup 2/. This circuit is the first CSSDA realized in CMOS technology, and represents state-of-the-art performances.     

A 12 MHz data cycle 4 Mb DRAM with pipeline operation

A 12 MHz data-cycle 4 Mb DRAM (dynamic RAM) with pipeline operation was designed and fabricated using 0.8 μm twin-tub CMOS technology. The pipeline DRAM outputs data corresponding to addresses that were accepted in the previous inverted random access storage (RAS) input cycle. The latter half of the previous read operation and the first half of the next read operation take place simultaneously, so the inverted RAS input cycle time is reduced. This pipeline DRAM technology needs no additional chip area and no process modification. A 95 ns inverted RAS input cycle time was obtained under worst conditions while this value is 125 ns for conventional DRAMs     

A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip

A low-power three-dimensional (3-D) rendering engine is implemented as part of a mobile personal digital assistant (PDA) chip. Six-megabit embedded DRAM macros attached to 8-pixel-parallel rendering logic are logically localized with a 3.2-GB/s runtime reconfigurable bus, reducing the area by 25% compared with conventional local frame-buffer architectures. The low power consumption is achieved by polygon-dependent access to the embedded DRAM macros with line-block mapping providing read-modify-write data transaction. The 3-D rendering engine with 2.22-Mpolygons/s drawing speed was fabricated using 0.18-/spl mu/m CMOS embedded memory logic technology. Its area is 24 mm/sup 2/ and its power consumption is 120 mW.